1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
6 #include <linux/ioport.h>
10 struct pci_controller;
12 /* Allocate a new PCI host bridge structure */
13 extern struct pci_controller* pcibios_alloc_controller(void);
15 /* Get the PCI host controller for a bus */
16 extern struct pci_controller* pci_bus_to_hose(int bus);
19 * Structure of a PCI controller (host bridge)
21 struct pci_controller {
24 int index; /* PCI domain number */
25 struct pci_controller *next;
26 struct device *parent;
32 void __iomem *io_base_virt;
33 resource_size_t io_base_phys;
35 /* Some machines (PReP) have a non 1:1 mapping of
36 * the PCI memory space in the CPU bus space
38 resource_size_t pci_mem_offset;
41 volatile unsigned int __iomem *cfg_addr;
42 volatile void __iomem *cfg_data;
45 * Used for variants of PCI indirect handling and possible quirks:
46 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
47 * EXT_REG - provides access to PCI-e extended registers
48 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
49 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
50 * to determine which bus number to match on when generating type0
53 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
54 #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
55 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
58 /* Currently, we limit ourselves to 1 IO range and 3 mem
59 * ranges since the common pci_bus structure can't handle more
61 struct resource io_resource;
62 struct resource mem_resources[3];
65 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
70 /* These are used for config access before all the PCI probing
72 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
74 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
76 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
78 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
80 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
82 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
85 extern void setup_indirect_pci_nomap(struct pci_controller* hose,
86 void __iomem *cfg_addr, void __iomem *cfg_data);
87 extern void setup_indirect_pci(struct pci_controller* hose,
88 u32 cfg_addr, u32 cfg_data);
89 extern void setup_grackle(struct pci_controller *hose);
93 #include <linux/pci.h>
94 #include <linux/list.h>
97 * This program is free software; you can redistribute it and/or
98 * modify it under the terms of the GNU General Public License
99 * as published by the Free Software Foundation; either version
100 * 2 of the License, or (at your option) any later version.
104 * Structure of a PCI controller (host bridge)
106 struct pci_controller {
111 struct list_head list_node;
112 struct device *parent;
117 void __iomem *io_base_virt;
119 resource_size_t io_base_phys;
121 /* Some machines have a non 1:1 mapping of
122 * the PCI memory space in the CPU bus space
124 resource_size_t pci_mem_offset;
125 unsigned long pci_io_size;
128 volatile unsigned int __iomem *cfg_addr;
129 volatile void __iomem *cfg_data;
131 /* Currently, we limit ourselves to 1 IO range and 3 mem
132 * ranges since the common pci_bus structure can't handle more
134 struct resource io_resource;
135 struct resource mem_resources[3];
138 unsigned long dma_window_base_cur;
139 unsigned long dma_window_size;
145 * PCI stuff, for nodes representing PCI devices, pointed to
146 * by device_node->data.
148 struct pci_controller;
152 int busno; /* pci bus number */
153 int bussubno; /* pci subordinate bus number */
154 int devfn; /* pci device and function number */
155 int class_code; /* pci device class */
157 struct pci_controller *phb; /* for pci devices */
158 struct iommu_table *iommu_table; /* for phb's or bridges */
159 struct pci_dev *pcidev; /* back-pointer to the pci device */
160 struct device_node *node; /* back-pointer to the device_node */
162 int pci_ext_config_space; /* for pci devices */
165 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
167 int eeh_pe_config_addr; /* new-style partition endpoint address */
168 int eeh_check_count; /* # times driver ignored error */
169 int eeh_freeze_count; /* # times this device froze up. */
170 int eeh_false_positives; /* # times this device reported #ff's */
171 u32 config_space[16]; /* saved PCI config space */
175 /* Get the pointer to a device_node's pci_dn */
176 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
178 struct device_node *fetch_dev_dn(struct pci_dev *dev);
180 /* Get a device_node from a pci_dev. This code must be fast except
181 * in the case where the sysdata is incorrect and needs to be fixed
182 * up (this will only happen once).
183 * In this case the sysdata will have been inherited from a PCI host
184 * bridge or a PCI-PCI bridge further up the tree, so it will point
185 * to a valid struct pci_dn, just not the one we want.
187 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
189 struct device_node *dn = dev->sysdata;
190 struct pci_dn *pdn = dn->data;
192 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
193 return dn; /* fast path. sysdata is good */
194 return fetch_dev_dn(dev);
197 static inline int pci_device_from_OF_node(struct device_node *np,
202 *bus = PCI_DN(np)->busno;
203 *devfn = PCI_DN(np)->devfn;
207 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
210 return pci_device_to_OF_node(bus->self);
212 return bus->sysdata; /* Must be root bus (PHB) */
215 /** Find the bus corresponding to the indicated device node */
216 struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
218 /** Remove all of the PCI devices under this bus */
219 void pcibios_remove_pci_devices(struct pci_bus *bus);
221 /** Discover new pci devices under this bus, and add them */
222 void pcibios_add_pci_devices(struct pci_bus * bus);
223 void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
225 extern int pcibios_remove_root_bus(struct pci_controller *phb);
227 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
229 struct device_node *busdn = bus->sysdata;
231 BUG_ON(busdn == NULL);
232 return PCI_DN(busdn)->phb;
235 extern struct pci_controller *
236 pcibios_alloc_controller(struct device_node *dev);
237 extern void pcibios_free_controller(struct pci_controller *phb);
239 extern void isa_bridge_find_early(struct pci_controller *hose);
241 extern int pcibios_unmap_io_space(struct pci_bus *bus);
242 extern int pcibios_map_io_space(struct pci_bus *bus);
244 /* Return values for ppc_md.pci_probe_mode function */
245 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
246 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
247 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
250 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
252 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
255 #endif /* CONFIG_PPC64 */
257 /* Get the PCI host controller for an OF device */
258 extern struct pci_controller*
259 pci_find_hose_for_OF_device(struct device_node* node);
261 /* Fill up host controller resources from the OF node */
263 pci_process_bridge_OF_ranges(struct pci_controller *hose,
264 struct device_node *dev, int primary);
267 extern unsigned long pci_address_to_pio(phys_addr_t address);
269 static inline unsigned long pci_address_to_pio(phys_addr_t address)
271 return (unsigned long)-1;
277 #endif /* __KERNEL__ */