2 * Freescale DMA Controller
4 * Copyright 2006 Freescale Semiconductor, Inc.
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * Version 2 as published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _ASM_FSL_DMA_H_
26 #define _ASM_FSL_DMA_H_
28 #include <asm/types.h>
30 typedef struct fsl_dma {
31 uint mr; /* DMA mode register */
32 #define FSL_DMA_MR_CS 0x00000001 /* Channel start */
33 #define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
34 #define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
35 #define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
36 #define FSL_DMA_MR_CA 0x00000008 /* Channel abort */
37 #define FSL_DMA_MR_CDSM 0x00000010
38 #define FSL_DMA_MR_XFE 0x00000020 /* Extended features en */
39 #define FSL_DMA_MR_EIE 0x00000040 /* Error interrupt en */
40 #define FSL_DMA_MR_EOLSIE 0x00000080 /* End-of-lists interrupt en */
41 #define FSL_DMA_MR_EOLNIE 0x00000100 /* End-of-links interrupt en */
42 #define FSL_DMA_MR_EOSIE 0x00000200 /* End-of-seg interrupt en */
43 #define FSL_DMA_MR_SRW 0x00000400 /* Single register write */
44 #define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
45 #define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
46 #define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
47 #define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
48 #define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
49 #define FSL_DMA_MR_EMP_EN 0x00200000 /* Ext master pause en */
50 #define FSL_DMA_MR_BWC_MASK 0x0f000000 /* Bandwidth/pause ctl */
51 #define FSL_DMA_MR_BWC_DIS 0x0f000000 /* Bandwidth/pause ctl disable */
52 uint sr; /* DMA status register */
53 #define FSL_DMA_SR_EOLSI 0x00000001 /* End-of-list interrupt */
54 #define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
55 #define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
56 #define FSL_DMA_SR_EOLNI 0x00000008 /* End-of-links interrupt */
57 #define FSL_DMA_SR_PE 0x00000010 /* Programming error */
58 #define FSL_DMA_SR_CH 0x00000020 /* Channel halted */
59 #define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
61 uint clndar; /* DMA current link descriptor address register */
62 uint satr; /* DMA source attributes register */
63 #define FSL_DMA_SATR_ESAD_MASK 0x000001ff /* Extended source addr */
64 #define FSL_DMA_SATR_SREAD_NO_SNOOP 0x00040000 /* Read, don't snoop */
65 #define FSL_DMA_SATR_SREAD_SNOOP 0x00050000 /* Read, snoop */
66 #define FSL_DMA_SATR_SREAD_UNLOCK 0x00070000 /* Read, unlock l2 */
67 #define FSL_DMA_SATR_STRAN_MASK 0x00f00000 /* Source interface */
68 #define FSL_DMA_SATR_SSME 0x01000000 /* Source stride en */
69 #define FSL_DMA_SATR_SPCIORDER 0x02000000 /* PCI transaction order */
70 #define FSL_DMA_SATR_STFLOWLVL_MASK 0x0c000000 /* RIO flow level */
71 #define FSL_DMA_SATR_SBPATRMU 0x20000000 /* Bypass ATMU */
72 uint sar; /* DMA source address register */
73 uint datr; /* DMA destination attributes register */
74 #define FSL_DMA_DATR_EDAD_MASK 0x000001ff /* Extended dest addr */
75 #define FSL_DMA_DATR_DWRITE_NO_SNOOP 0x00040000 /* Write, don't snoop */
76 #define FSL_DMA_DATR_DWRITE_SNOOP 0x00050000 /* Write, snoop */
77 #define FSL_DMA_DATR_DWRITE_ALLOC 0x00060000 /* Write, alloc l2 */
78 #define FSL_DMA_DATR_DWRITE_LOCK 0x00070000 /* Write, lock l2 */
79 #define FSL_DMA_DATR_DTRAN_MASK 0x00f00000 /* Dest interface */
80 #define FSL_DMA_DATR_DSME 0x01000000 /* Dest stride en */
81 #define FSL_DMA_DATR_DPCIORDER 0x02000000 /* PCI transaction order */
82 #define FSL_DMA_DATR_DTFLOWLVL_MASK 0x0c000000 /* RIO flow level */
83 #define FSL_DMA_DATR_DBPATRMU 0x20000000 /* Bypass ATMU */
84 uint dar; /* DMA destination address register */
85 uint bcr; /* DMA byte count register */
87 uint nlndar; /* DMA next link descriptor address register */
89 uint clabdar; /* DMA current List - alternate base descriptor address Register */
91 uint nlsdar; /* DMA next list descriptor address register */
92 uint ssr; /* DMA source stride register */
93 uint dsr; /* DMA destination stride register */
99 int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
100 #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
101 void dma_meminit(uint val, uint size);
105 #endif /* _ASM_DMA_H_ */