2 * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU Lesser General
7 * Public License. You may obtain a copy of the GNU Lesser General
8 * Public License Version 2.1 or later at the following locations:
10 * http://www.opensource.org/licenses/lgpl-license.html
11 * http://www.gnu.org/copyleft/lgpl.html
15 * @defgroup VPU Video Processor Unit Driver
19 * @file plat-mxc/include/mach/mxc_vpu.h
21 * @brief VPU system initialization and file operation definition
26 #ifndef __ASM_ARCH_MXC_VPU_H__
27 #define __ASM_ARCH_MXC_VPU_H__
31 struct mxc_vpu_platform_data {
41 u32 cpu_addr; /* cpu address to free the dma mem */
42 u32 virt_uaddr; /* virtual user space address */
45 #define VPU_IOC_MAGIC 'V'
47 #define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0)
48 #define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1)
49 #define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2)
50 #define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3)
51 #define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4)
52 #define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6)
53 #define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7)
54 #define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8)
55 #define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9)
56 #define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11)
57 #define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12)
58 #define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13)
59 #define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14)
60 #define VPU_IOC_PHYMEM_CHECK _IO(VPU_IOC_MAGIC, 15)
61 #define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 16)
63 #define BIT_CODE_RUN 0x000
64 #define BIT_CODE_DOWN 0x004
65 #define BIT_INT_CLEAR 0x00C
66 #define BIT_INT_STATUS 0x010
67 #define BIT_CUR_PC 0x018
68 #define BIT_INT_REASON 0x174
70 #define MJPEG_PIC_STATUS_REG 0x3004
71 #define MBC_SET_SUBBLK_EN 0x4A0
73 #define BIT_WORK_CTRL_BUF_BASE 0x100
74 #define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4)
75 #define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0)
76 #define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1)
77 #define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2)
78 #define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3)
79 #define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4)
80 #define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5)
82 #ifndef CONFIG_ARCH_MX6
83 #define BIT_RESET_CTRL 0x11C
85 #define BIT_RESET_CTRL 0x128
88 /* i could be 0, 1, 2, 3 */
89 #define BIT_RD_PTR_BASE 0x120
90 #define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8)
91 #define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4)
93 /* i could be 0, 1, 2, 3 */
94 #define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140)
95 #define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4)
97 #define BIT_BUSY_FLAG 0x160
98 #define BIT_RUN_COMMAND 0x164
99 #define BIT_INT_ENABLE 0x170
101 #define BITVAL_PIC_RUN 8
103 #define VPU_SLEEP_REG_VALUE 10
104 #define VPU_WAKE_REG_VALUE 11
106 int vl2cc_init(u32 vl2cc_hw_base);
107 void vl2cc_enable(void);
108 void vl2cc_flush(void);
109 void vl2cc_disable(void);
110 void vl2cc_cleanup(void);
112 int vl2cc_init(u32 vl2cc_hw_base);
113 void vl2cc_enable(void);
114 void vl2cc_flush(void);
115 void vl2cc_disable(void);
116 void vl2cc_cleanup(void);