1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/karo_tx25.h> // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
54 #define PLATFORM_SETUP1 _platform_setup1
55 #define CYGHWR_HAL_ARM_HAS_MMU
57 //#define INTERNAL_BOOT_MODE
59 #if defined(INTERNAL_BOOT_MODE)
60 #define PLATFORM_PREAMBLE setup_flash_header
63 #ifdef CYG_HAL_STARTUP_ROMRAM
64 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
67 #define TX25_NAND_PAGE_SIZE 2048
68 #define TX25_NAND_BLKS_PER_PAGE 64
70 #define DEBUG_LED_BIT 7
72 #ifndef CYGOPT_HAL_ARM_TX25_DEBUG
81 #define CYGHWR_LED_MACRO LED_BLINK #\x
97 // switch user LED (GPIO2[7] PAD A21) on STK5
98 ldr r10, GPIO2_BASE_ADDR_W
102 ldr r9, [r10, #GPIO_DR]
103 orne r9, #(1 << DEBUG_LED_BIT) // LED ON
104 biceq r9, #(1 << DEBUG_LED_BIT) // LED OFF
105 str r9, [r10, #GPIO_DR]
124 .macro early_uart_setup
125 ldr r1, IOMUXC_BASE_ADDR_W
138 ldr r1, UART1_BASE_ADDR_W
139 mov r0, #(1 << 0) @ UART_EN
140 // orr r0, r0, #(1 << 14) @ ADEN
141 str r0, [r1, #0x80] @ UCR1
143 mov r0, #(1 << 14) @ IRTS
144 orr r0, r0, #((1 << 5) | (1 << 2) | (1 << 1)) @ word size 8bit, TXEN, RXEN
145 str r0, [r1, #0x84] @ UCR2
147 ldr r0, [r1, #0x88] @ UCR3
148 orr r0, r0, #(1 << 2) @ RXDMUXSEL
149 str r0, [r1, #0x88] @ UCR3
152 str r0, [r1, #0xa4] @ UBIR
155 str r0, [r1, #0xa8] @ UBMR
159 ldr r9, UART1_BASE_ADDR_W
161 ldr r10, [r9, #0xb4] @ UTS
162 tst r10, #(1 << 4) @ TXFULL
168 .set progress_ind, 'A'
170 uart_putc #progress_ind
171 .set progress_ind, progress_ind + 1
174 .macro early_uart_setup
183 // initialize GPIO2[7] (Pad A21) for LED on STK5
184 ldr r10, GPIO2_BASE_ADDR_W
186 ldr r9, [r10, #GPIO_GDIR]
187 orr r9, #(1 << DEBUG_LED_BIT)
188 str r9, [r10, #GPIO_GDIR]
190 ldr r10, IOMUXC_BASE_ADDR_W
194 ldr r10, GPIO2_BASE_ADDR_W
196 ldr r9, [r10, #GPIO_DR]
197 orr r9, #(1 << DEBUG_LED_BIT) // LED ON
198 str r9, [r10, #GPIO_DR]
202 #ifdef CYGHWR_TX25_BOOTSPLASH
203 ldr r10, IOMUXC_BASE_ADDR_W
206 str r9, [r10, #0x088]
207 str r9, [r10, #0x08c]
210 str r9, [r10, #0x0c8]
211 str r9, [r10, #0x0cc]
212 str r9, [r10, #0x0d0]
213 str r9, [r10, #0x0d4]
214 str r9, [r10, #0x0d8]
215 str r9, [r10, #0x0dc]
216 str r9, [r10, #0x0e0]
217 str r9, [r10, #0x0e4]
218 str r9, [r10, #0x0e8]
219 str r9, [r10, #0x0ec]
220 str r9, [r10, #0x0f0]
221 str r9, [r10, #0x0f4]
222 str r9, [r10, #0x0f8]
223 str r9, [r10, #0x0fc]
224 str r9, [r10, #0x100]
225 str r9, [r10, #0x104]
226 str r9, [r10, #0x108]
227 str r9, [r10, #0x10c]
228 str r9, [r10, #0x110]
229 str r9, [r10, #0x114]
232 str r9, [r10, #0x11c] /* configure PAD_PWM as GPIO1_26 LCD_BACKLIGHT */
233 str r9, [r10, #0x020] /* dto. for PAD_A18 (GPIO2_4) LCD_RESET */
234 str r9, [r10, #0x024] /* dto. for PAD_A19 (GPIO2_5) LCD_POWER */
236 ldr r10, GPIO1_BASE_ADDR_W
238 ldr r9, [r10, #GPIO_DR]
239 orr r9, #(1 << (LCD_BACKLIGHT_GPIO % 32))
240 str r9, [r10, #GPIO_DR]
242 ldr r9, [r10, #GPIO_GDIR]
243 orr r9, #(1 << (LCD_BACKLIGHT_GPIO % 32))
244 str r9, [r10, #GPIO_GDIR]
246 ldr r10, GPIO2_BASE_ADDR_W
248 ldr r9, [r10, #GPIO_DR]
249 bic r9, #(1 << (LCD_POWER_GPIO % 32) | (1 << (LCD_RESET_GPIO % 32)))
250 str r9, [r10, #GPIO_DR]
252 ldr r9, [r10, #GPIO_GDIR]
253 orr r9, #((1 << (LCD_POWER_GPIO % 32)) | (1 << (LCD_RESET_GPIO % 32)))
254 str r9, [r10, #GPIO_GDIR]
259 // This macro represents the initial startup code for the platform
260 // r11 is reserved to contain chip rev info in this file
261 .macro _platform_setup1
262 KARO_TX25_SETUP_START:
263 // invalidate I/D cache/TLB
265 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
266 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
267 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
278 #ifndef INTERNAL_BOOT_MODE
279 // check if sdram has been setup
280 #ifdef RAM_BANK1_SIZE
281 cmp pc, #RAM_BANK1_BASE
283 cmp pc, #(RAM_BANK1_BASE + RAM_BANK1_SIZE)
284 blo HWInitialise_skip_SDRAM_setup
286 cmp pc, #RAM_BANK0_BASE
288 cmp pc, #(RAM_BANK0_BASE + RAM_BANK0_SIZE)
289 blo HWInitialise_skip_SDRAM_setup
290 #endif // RAM_BANK1_SIZE
291 #endif // INTERNAL_BOOT_MODE
301 #ifndef INTERNAL_BOOT_MODE
310 HWInitialise_skip_SDRAM_setup:
312 add r2, r0, #0x0800 // 2K window
314 blo Normal_Boot_Continue
316 bhi Normal_Boot_Continue
320 /* Copy image from NFC buffer to SDRAM first */
321 ldr r1, MXC_REDBOOT_RAM_START
334 mov r0, #NFC_BASE // r0: nfc base. Reloaded after each page copy
335 add r12, r0, #0x1E00 // r12: NFC register base. Doesn't change
336 ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
340 ldr r7, CCM_BASE_ADDR_W
341 ldr r1, [r7, #CLKCTL_RCSR]
342 /* BUS WIDTH setting */
344 orrne r1, r1, #(1 << 14)
345 biceq r1, r1, #(1 << 14)
349 orrne r1, r1, #(1 << 9)
352 bic r1, r1, #(1 << 9)
354 orrne r1, r1, #(1 << 8) /* 2KB page size */
355 biceq r1, r1, #(1 << 8) /* 512B page size */
356 movne r2, #(64 >> 1) /* 64 bytes */
357 moveq r2, #8 /* 16 bytes */
361 bicne r3, r3, #1 /* Enable 8bit ECC mode */
362 movne r2, #109 /* 218 bytes */
363 moveq r2, #(128 >> 1) /* 128 bytes */
365 str r1, [r7, #CLKCTL_RCSR]
366 strh r2, [r12, #ECC_RSLT_SPARE_AREA_REG_OFF]
367 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
369 //unlock internal buffer
371 strh r3, [r12, #NFC_CONFIGURATION_REG_OFF]
374 strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF]
376 strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF]
378 strh r3, [r12, #NF_WR_PROT_REG_OFF]
380 /* r0: NFC base address. RAM buffer base address. [Updated constantly]
381 * r1: starting flash address to be copied. [Updated constantly]
382 * r2: page size. [Doesn't change]
383 * r3: used as argument.
384 * r11: starting SDRAM address for copying. [Updated constantly].
385 * r12: NFC register base address. [Updated constantly].
386 * r13: end of SDRAM address for copying. [Doesn't change].
389 ldr r3, [r7, #CLKCTL_RCSR]
398 /* Update the indicator of copy area */
399 ldr r11, MXC_REDBOOT_RAM_START
400 add r13, r11, #REDBOOT_IMAGE_SIZE
412 do_addr_input //1st addr cycle
414 do_addr_input //2nd addr cycle
416 do_addr_input //3rd addr cycle
418 do_addr_input //4th addr cycle
419 b end_of_nfc_addr_ops
423 do_addr_input //1st addr cycle
425 do_addr_input //2nd addr cycle
427 do_addr_input //3rd addr cycle
429 do_addr_input //4th addr cycle
431 do_addr_input //5th addr cycle
435 b end_of_nfc_addr_ops
439 do_addr_input //1st addr cycle
441 do_addr_input //2nd addr cycle
443 do_addr_input //3rd addr cycle
445 do_addr_input //4th addr cycle
447 do_addr_input //5th addr cycle
456 // Check if x16/2kb page
458 bhi nfc_addr_data_output_done_4k
459 beq nfc_addr_data_output_done_2k
460 beq nfc_addr_data_output_done_512
462 // check for bad block
463 // mov r3, r1, lsl #(32-17) // get rid of block number
464 // cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
465 b nfc_addr_data_output_done
467 nfc_addr_data_output_done_4k:
469 b nfc_addr_data_output_done
471 nfc_addr_data_output_done_2k:
472 // check for bad block
473 //TODO: mov r3, r1, lsl #(32-17) // get rid of block number
474 // cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
475 b nfc_addr_data_output_done
477 nfc_addr_data_output_done_512:
478 // check for bad block
479 // TODO: mov r3, r1, lsl #(32-5-9) // get rid of block number
480 // TODO: cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
482 nfc_addr_data_output_done:
485 add r4, r0, #0x1000 //r3 -> spare area buf 0
490 // really sucks. Bad block!!!!
493 // even suckier since we already read the first page!
494 // Check if x16/2kb page
497 subhi r11, r11, #0x1000 //rewind 1 page for the sdram pointer
498 subhi r1, r1, #0x1000 //rewind 1 page for the flash pointer
500 subeq r11, r11, #0x800 //rewind 1 page for the sdram pointer
501 subeq r1, r1, #0x800 //rewind 1 page for the flash pointer
503 sublo r11, r11, #512 //rewind 1 page for the sdram pointer
504 sublo r1, r1, #512 //rewind 1 page for the flash pointer
506 // Check if x16/2kb page
507 ldr r7, CCM_BASE_ADDR_W
508 ldr r7, [r7, #CLKCTL_RCSR]
510 addne r1, r1, #(128 * 4096)
511 bne Skip_bad_block_done
513 addeq r1, r1, #(32 * 512)
514 addne r1, r1, #(64 * 2048)
521 add r2, r2, #NFC_BASE
527 sub r2, r2, #NFC_BASE
530 bge NAND_Copy_Main_done
531 // Check if x16/2kb page
537 Normal_Boot_Continue:
542 // Set up a stack [for calling C code]
543 ldr sp, =__startup_stack
551 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
552 orr r1, r1, #7 // enable MMU bit
554 mcr MMU_CP, 0, r1, MMU_Control, c0
555 mov pc, r2 /* Change address spaces */
559 .endm // _platform_setup1
562 ldr r0, SDRAM_ADDR_MASK
563 ldr r1, MXC_REDBOOT_RAM_START
570 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
571 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
573 bx lr // do_wait_op_done
576 ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
577 orr r3, r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
578 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
580 strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
582 mov r3, #FDO_PAGE_SPARE_VAL
583 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
586 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
587 #define PLATFORM_SETUP1
592 .endm /* init_spba */
594 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
597 * Set all MPROTx to be non-bufferable, trusted for R/W,
598 * not forced to user-mode.
600 ldr r0, AIPS1_CTRL_BASE_ADDR_W
601 ldr r1, AIPS1_PARAM_W
604 ldr r0, AIPS2_CTRL_BASE_ADDR_W
607 .endm /* init_aips */
609 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
611 ldr r0, MAX_BASE_ADDR_W
612 /* MPR - priority for MX25 is IAHB>DAHB>USBOTG>RTIC>(SDHC2/SDMA) */
614 str r1, [r0, #0x000] /* for S0 */
615 str r1, [r0, #0x100] /* for S1 */
616 str r1, [r0, #0x200] /* for S2 */
617 str r1, [r0, #0x300] /* for S3 */
618 str r1, [r0, #0x400] /* for S4 */
619 /* SGPCR - always park on last master */
621 str r1, [r0, #0x010] /* for S0 */
622 str r1, [r0, #0x110] /* for S1 */
623 str r1, [r0, #0x210] /* for S2 */
624 str r1, [r0, #0x310] /* for S3 */
625 str r1, [r0, #0x410] /* for S4 */
626 /* MGPCR - restore default values */
628 str r1, [r0, #0x800] /* for M0 */
629 str r1, [r0, #0x900] /* for M1 */
630 str r1, [r0, #0xA00] /* for M2 */
631 str r1, [r0, #0xB00] /* for M3 */
632 str r1, [r0, #0xC00] /* for M4 */
637 ldr r0, CCM_BASE_ADDR_W
639 /* default CLKO to 1/6 of the USB PLL */
640 ldr r1, [r0, #CLKCTL_MCR]
641 bic r1, r1, #0x00F00000
642 bic r1, r1, #0x7F000000
643 mov r2, #0x45000000 /* set CLKO divider to 6 */
644 add r2, r2, #0x00600000 /* select usb_clk clock source for CLKO */
646 str r1, [r0, #CLKCTL_MCR]
648 ldr r1, CCM_CCTL_VAL_W
649 str r1, [r0, #CLKCTL_CCTL] /* configure ARM clk */
651 /* enable all the clocks */
653 str r2, [r0, #CLKCTL_CGR0]
655 str r2, [r0, #CLKCTL_CGR1]
657 str r2, [r0, #CLKCTL_CGR2]
658 .endm /* init_clock */
662 /* Configure M3IF registers */
665 * M3IF Control Register (M3IFCTL) for MX25
666 * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
667 * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
668 * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
669 * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
670 * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
671 * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
672 * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
673 * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
678 str r0, [r1] /* M3IF control reg */
679 .endm /* init_m3if */
682 ldr r0, IOMUXC_BASE_ADDR_W
686 ldr r0, ESDCTL_BASE_W
687 mov r1, #RAM_BANK0_BASE
689 #ifdef RAM_BANK1_SIZE
690 mov r1, #RAM_BANK1_BASE
696 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
697 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
698 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
700 .endm // nfc_cmd_input
704 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
705 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
706 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
708 .endm // do_addr_input
710 /* To support 133MHz DDR */
713 ldr r1, IOMUXC_BASE_ADDR_W
715 add r2, r1, #0x4C8 - 0x368
720 .endm /* init_iomuxc */
722 #define ESDCTL_NORMAL (0 << 28)
723 #define ESDCTL_PCHG (1 << 28)
724 #define ESDCTL_AREF (2 << 28)
725 #define ESDCTL_LMOD (3 << 28)
726 #define ESDCTL_SLFRFSH (4 << 28)
728 #define RA_BITS 2 /* row addr bits - 11 */
729 #define CA_BITS 1 /* 0-2: col addr bits - 8 3: rsrvd */
730 #define DSIZ 1 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
731 #define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
732 #define PWDT 1 /* 0: disabled 1: precharge pwdn
733 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
734 #define FP 0 /* 0: not full page 1: full page */
735 #define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
736 #define PRCT 0 /* 0: disabled *: clks / 2 (0..63) */
737 #define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
738 (DSIZ << 16) | (SREFR << 13) | (PWDT << 10) | (FP << 8) | \
739 (BL << 7) | (PRCT << 0))
741 #define tXP 0 /* clks - 1 (0..3) */ // N/A
742 #define tWTR 0 /* clks - 1 (0..1) */ // N/A
743 #define tRP 2 /* clks - 1 (0..3) */ // 2
744 #define tMRD 1 /* clks - 1 (0..3) */ // 1
745 #define tWR 0 /* clks - 2 (0..1) */ // 0
746 #define tRAS 5 /* clks - 1 (0..7) */ // 5
747 #define tRRD 1 /* clks - 1 (0..3) */ // 1
748 #define tCAS 3 /* 0: 3 clks[LPDDR] 1: rsrvd *: clks (2..3) */ // 3
749 #define tRCD 2 /* clks - 1 (0..7) */ // 2
750 #define tRC 8 /* 0: 20 *: clks - 1 (0..15) */ // 8
752 #define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
753 (tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \
754 (tRCD << 4) | (tRC << 0))
757 * r0: control base, r1: ram bank base
761 mov r3, #(1 << 1) /* SDRAM controller reset */
762 str r3, [r0, #ESDCTL_ESDMISC]
764 ldr r3, [r0, #ESDCTL_ESDMISC]
768 ldr r3, ESDCTL_CONFIG
769 cmp r1, #RAM_BANK1_BASE
770 movhs r2, #0xc // bank 1 ESDCFG offset
771 movlo r2, #0x4 // bank 0 ESDCFG offset
773 sub r2, r2, #4 // adjust to ESDCTL offset
775 ldr r3, ESDCTL_CMD_PRECHARGE
777 str r3, [r1, #(1 << 10)] // precharge all command
779 ldr r3, ESDCTL_CMD_AUTOREFR
782 ldrb r3, [r1] // perform auto refresh cycles
785 ldr r3, ESDCTL_CMD_MODEREG
787 strb r3, [r1, #((tCAS << 4) | (FP << 2) | 0x03)] // load mode reg via A0..A11
789 ldr r3, ESDCTL_CMD_NORMAL
794 #define PLATFORM_VECTORS _platform_vectors
795 .macro _platform_vectors
799 .globl _KARO_STRUCT_SIZE
801 .word 0 // reserve space structure length
803 .globl _KARO_CECFG_START
806 .word 0 // reserve space for CE configuration
809 .globl _KARO_CECFG_END
813 //Internal Boot, from MMC/SD cards or NAND flash
814 #ifdef INTERNAL_BOOT_MODE
815 #define DCDGEN(type, addr, data) \
820 #define FHEADER_OFFSET 0x400
822 #ifdef RAM_BANK1_SIZE
823 #define PHYS_ADDR(a) ((a) - RAM_BANK0_BASE - RAM_BANK0_SIZE + RAM_BANK1_BASE)
825 #define PHYS_ADDR(a) (a)
828 .macro setup_flash_header
830 #if defined(FHEADER_OFFSET)
833 app_code_jump_v: .long PHYS_ADDR(reset_vector)
834 app_code_barker: .long 0xB1
835 app_code_csf: .long 0
836 hwcfg_ptr_ptr: .long PHYS_ADDR(hwcfg_ptr)
837 super_root_key: .long 0
838 hwcfg_ptr: .long PHYS_ADDR(dcd_data)
839 #ifdef RAM_BANK1_SIZE
840 app_dest_ptr: .long RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
842 app_dest_ptr: .long RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET
844 dcd_data: .long 0xB17219E9
847 // real dcd data table
849 DCDGEN(4, 0xB8001010, 0x00000000) // disable mDDR
850 DCDGEN(4, 0xB8001000, 0x92100000) // precharge command
851 DCDGEN(1, 0x80000400, 0x00000000) // precharge all dummy write
852 DCDGEN(4, 0xB8001000, 0xA2100000) // auto-refresh command
853 DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
854 DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
855 DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
856 DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
857 DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
858 DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
859 DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
860 DCDGEN(4, 0x80000000, 0x00000000) // dummy write for refresh
861 DCDGEN(4, 0xB8001000, 0xB2100000) // Load Mode Register command - cas=3 bl=8
862 DCDGEN(1, 0x80000033, 0x00) // dummy write -- address has the mode bits
864 // For DDR clock speed max = 133 MHz, HYB18M1G320BF-7.5 memory
865 // based on data sheet HYx18M1G16x_BF_rev100.pdf.
867 // ESDCTL0=0x82216880:
868 // SDE=1 ESDRAM Controller Enable: Enabled
869 // SMODE=000 SDRAM Controller Operating Mode: Normal Read/Write
870 // SP=0 Supervisor Protect: User mode accesses allowed
871 // ROW=010 Row Address Width: 13 Row Addresses
872 // COL=10 Column Address Width: 10 Column Addresses
873 // DSIZ=01 SDRAM Memory Data Width: 16-bit memory width aligned to D[15:0]
874 // SREFR=011 SDRAM Refresh Rate: 4 rows each refresh clock,
875 // 8192 rows/64 mS @ 32 kHz
876 // 7.81 uS row rate at 32 kHz
877 // PWDT=10 Power Down Timer: 64 clocks (HCLK) after completion of last access
878 // with Active Power Down (most aggressive)
879 // FP=0 Full Page: Not Full Page
880 // BL=1 Burst Length: 8
881 // PRCT=000000 Precharge Timer: Disabled
883 DCDGEN(4, 0xB8001000, ESDCTLVAL)
885 // ESDCFG0=0x00295728:
886 // tXP=01 LPDDR exit power down to next valid command delay: 2 clocks
887 // tWTR=0 LPDDR WRITE to READ Command Delay: 1 clock
888 // tRP=10 SDRAM Row Precharge Delay: 3 clocks
889 // tMRD=01 SDRAM Load Mode Register to ACTIVE Command: 2 clocks
890 // tWR=0 SDRAM WRITE to PRECHARGE Command: 2 clocks
891 // tRAS=101 SDRAM ACTIVE to PRECHARGE Command: 6 clocks
892 // tRRD=01 ACTIVE Bank A to ACTIVE Bank B Command: 2 clocks
893 // tCAS=11 SDRAM CAS Latency: 3 clocks
894 // tRCD=010 SDRAM Row to Column Delay: 3 clocks
895 // tRC=1000 SDRAM Row Cycle Delay: 9 clocks
897 DCDGEN(4, 0xB8001004, ESDCFGVAL)
900 DCDGEN(4, 0x53F80008, 0x20034000) // CLKCTL ARM=400 AHB=133
903 //CARD_FLASH_CFG_PARMS_T---length
905 .long REDBOOT_IMAGE_SIZE
909 SDRAM_ADDR_MASK: .word 0xFFFC0000
910 #ifdef RAM_BANK1_SIZE
911 MXC_REDBOOT_RAM_START: .word RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
913 MXC_REDBOOT_RAM_START: .word RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET
915 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
916 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
917 AIPS1_PARAM_W: .word 0x77777777
918 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
919 MAX_PARAM1: .word 0x00043210
920 ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
921 M3IF_BASE_W: .word M3IF_BASE
922 ESDCTL_CMD_NORMAL: .word ESDCTLVAL | ESDCTL_NORMAL
923 ESDCTL_CMD_AUTOREFR: .word ESDCTLVAL | ESDCTL_AREF
924 ESDCTL_CMD_PRECHARGE: .word ESDCTLVAL | ESDCTL_PCHG
925 ESDCTL_CMD_MODEREG: .word ESDCTLVAL | ESDCTL_LMOD
926 ESDCTL_CONFIG: .word ESDCFGVAL
927 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
928 GPIO1_BASE_ADDR_W: .word GPIO1_BASE_ADDR
929 GPIO2_BASE_ADDR_W: .word GPIO2_BASE_ADDR
931 UART1_BASE_ADDR_W: .word UART1_BASE_ADDR
932 UART1_UBIR_W: .word 0x0f
933 UART1_UBMR_W: .word 0x2e
935 CCM_CGR0_W: .word 0x1FFFFFFF
936 CCM_CGR1_W: .word 0xFFFFFFFF
937 CCM_CGR2_W: .word 0x000FDFFF
938 CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
939 CCM_CCTL_VAL_W: .word 0x20034000
940 /*-----------------------------------------------------------------------*/
941 /* end of hal_platform_setup.h */
942 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */