X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farm720t%2Fstart.S;h=a396ebcb715ebc121d8b4e13c7b28fecc2ea2675;hb=69f14dc2fd64307f012381dd333a06001dec75dc;hp=8cd267b352a215bfcad139d75d40802066c599cc;hpb=e03f31697478e9edd523f34b1ed54b6ff2cb7242;p=karo-tx-uboot.git diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 8cd267b352..a396ebcb71 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -1,8 +1,8 @@ /* * armboot - Startup Code for ARM720 CPU-core * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke * * See file CREDITS for list of people who contributed to this * project. @@ -43,14 +43,20 @@ _start: b reset ldr pc, _software_interrupt ldr pc, _prefetch_abort ldr pc, _data_abort -#ifdef CONFIG_LPC2292 - .word 0xB4405F76 /* 2's complement of the checksum of the vectors */ -#else ldr pc, _not_used -#endif ldr pc, _irq ldr pc, _fiq +#ifdef CONFIG_SPL_BUILD +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -58,6 +64,8 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +#endif /* CONFIG_SPL_BUILD */ .balignl 16,0xdeadbeef @@ -77,18 +85,29 @@ _fiq: .word fiq .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. */ -.globl _bss_start -_bss_start: - .word __bss_start +.globl _bss_start_ofs +_bss_start_ofs: + .word __bss_start - _start -.globl _bss_end -_bss_end: - .word _end +.globl _bss_end_ofs +_bss_end_ofs: + .word __bss_end - _start + +.globl _end_ofs +_end_ofs: + .word _end - _start #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ @@ -107,30 +126,6 @@ FIQ_STACK_START: IRQ_STACK_START_IN: .word 0x0badc0de -.globl _datarel_start -_datarel_start: - .word __datarel_start - -.globl _datarelrolocal_start -_datarelrolocal_start: - .word __datarelrolocal_start - -.globl _datarellocal_start -_datarellocal_start: - .word __datarellocal_start - -.globl _datarelro_start -_datarelro_start: - .word __datarelro_start - -.globl _got_start -_got_start: - .word __got_start - -.globl _got_end -_got_end: - .word __got_end - /* * the actual reset code */ @@ -152,109 +147,15 @@ reset: bl cpu_init_crit #endif -#ifdef CONFIG_LPC2292 - bl lowlevel_init -#endif - -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - */ - .globl relocate_code -relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ - mov r7, r2 /* save addr of destination */ - - /* Set up the stack */ -stack_setup: - mov sp, r4 - - adr r0, _start - ldr r2, _TEXT_BASE - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - cmp r0, r6 - beq clear_bss - -copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - blo copy_loop - -#ifndef CONFIG_PRELOADER - /* fix got entries */ - ldr r1, _TEXT_BASE /* Text base */ - mov r0, r7 /* reloc addr */ - ldr r2, _got_start /* addr in Flash */ - ldr r3, _got_end /* addr in Flash */ - sub r3, r3, r1 - add r3, r3, r0 - sub r2, r2, r1 - add r2, r2, r0 - -fixloop: - ldr r4, [r2] - sub r4, r4, r1 - add r4, r4, r0 - str r4, [r2] - add r2, r2, #4 - cmp r2, r3 - blo fixloop -#endif + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: -clear_bss: -#ifndef CONFIG_PRELOADER - ldr r0, _bss_start - ldr r1, _bss_end - ldr r3, _TEXT_BASE /* Text base */ - mov r4, r7 /* reloc addr */ - sub r0, r0, r3 - add r0, r0, r4 - sub r1, r1, r3 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - bne clbss_l - - bl coloured_LED_init - bl red_LED_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _TEXT_BASE - ldr r2, _board_init_r - sub r2, r2, r0 - add r2, r2, r7 /* position from board_init_r in RAM */ - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r7 /* dest_addr */ - /* jump to it ... */ - mov lr, r2 mov pc, lr -_board_init_r: .word board_init_r - /* ************************************************************************* * @@ -266,192 +167,9 @@ _board_init_r: .word board_init_r ************************************************************************* */ -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - -/* Interupt-Controller base addresses */ -INTMR1: .word 0x80000280 @ 32 bit size -INTMR2: .word 0x80001280 @ 16 bit size -INTMR3: .word 0x80002280 @ 8 bit size - -/* SYSCONs */ -SYSCON1: .word 0x80000100 -SYSCON2: .word 0x80001100 -SYSCON3: .word 0x80002200 - -#define CLKCTL 0x6 /* mask */ -#define CLKCTL_18 0x0 /* 18.432 MHz */ -#define CLKCTL_36 0x2 /* 36.864 MHz */ -#define CLKCTL_49 0x4 /* 49.152 MHz */ -#define CLKCTL_73 0x6 /* 73.728 MHz */ - -#elif defined(CONFIG_LPC2292) -PLLCFG_ADR: .word PLLCFG -PLLFEED_ADR: .word PLLFEED -PLLCON_ADR: .word PLLCON -PLLSTAT_ADR: .word PLLSTAT -VPBDIV_ADR: .word VPBDIV -MEMMAP_ADR: .word MEMMAP - -#endif - +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - mov r1, #0x00 - ldr r0, INTMR1 - str r1, [r0] - ldr r0, INTMR2 - str r1, [r0] - ldr r0, INTMR3 - str r1, [r0] - - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15,0,r0,c1,c0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - mcr p15,0,r0,c1,c0 -#elif defined(CONFIG_NETARM) - /* - * prior to software reset : need to set pin PORTC4 to be *HRESET - */ - ldr r0, =NETARM_GEN_MODULE_BASE - ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ - NETARM_GEN_PORT_DIR(0x10)) - str r1, [r0, #+NETARM_GEN_PORTC] - /* - * software reset : see HW Ref. Guide 8.2.4 : Software Service register - * for an explanation of this process - */ - ldr r0, =NETARM_GEN_MODULE_BASE - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - /* - * setup PLL and System Config - */ - ldr r0, =NETARM_GEN_MODULE_BASE - - ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ - NETARM_GEN_SYS_CFG_BUSFULL | \ - NETARM_GEN_SYS_CFG_USER_EN | \ - NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ - NETARM_GEN_SYS_CFG_BUSARB_INT | \ - NETARM_GEN_SYS_CFG_BUSMON_EN ) - - str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] - -#ifndef CONFIG_NETARM_PLL_BYPASS - ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ - NETARM_GEN_PLL_CTL_POLTST_DEF | \ - NETARM_GEN_PLL_CTL_INDIV(1) | \ - NETARM_GEN_PLL_CTL_ICP_DEF | \ - NETARM_GEN_PLL_CTL_OUTDIV(2) ) - str r1, [r0, #+NETARM_GEN_PLL_CONTROL] -#endif - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - mov r1, #0 - ldr r0, =NETARM_GEN_MODULE_BASE - str r1, [r0, #+NETARM_GEN_INTR_ENABLE] - -#elif defined(CONFIG_S3C4510B) - /* - * Mask off all IRQ sources - */ - ldr r1, =REG_INTMASK - ldr r0, =0x3FFFFF - str r0, [r1] - - /* - * Disable Cache - */ - ldr r0, =REG_SYSCFG - ldr r1, =0x83ffffa0 /* cache-disabled */ - str r1, [r0] - -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific initialisation for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - /* Set-up PLL */ - mov r3, #0xAA - mov r4, #0x55 - /* First disconnect and disable the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x00 - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Set new M and P values */ - ldr r0, PLLCFG_ADR - mov r1, #0x23 /* M=4 and P=2 */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Then enable the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x01 /* PLL enable bit */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Wait for the lock */ - ldr r0, PLLSTAT_ADR - mov r1, #0x400 /* lock bit */ -lock_loop: - ldr r2, [r0] - and r2, r1, r2 - cmp r2, #0 - beq lock_loop - /* And finally connect the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x03 /* PLL enable bit and connect bit */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Set-up VPBDIV register */ - ldr r0, VPBDIV_ADR - mov r1, #0x01 /* VPB clock is same as process clock */ - str r1, [r0] -#else -#error No cpu_init_crit() defined for current CPU type -#endif - -#ifdef CONFIG_ARM7_REVD - /* set clock speed */ - /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */ - /* !!! not doing DRAM refresh properly! */ - ldr r0, SYSCON3 - ldr r1, [r0] - bic r1, r1, #CLKCTL - orr r1, r1, #CLKCTL_36 - str r1, [r0] -#endif - -#ifndef CONFIG_LPC2292 mov ip, lr /* * before relocating, we have to setup RAM timing @@ -460,11 +178,12 @@ lock_loop: */ bl lowlevel_init mov lr, ip -#endif mov pc, lr +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#ifndef CONFIG_SPL_BUILD /* ************************************************************************* * @@ -627,49 +346,4 @@ fiq: bl do_fiq #endif - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - .align 5 -.globl reset_cpu -reset_cpu: - mov ip, #0 - mcr p15, 0, ip, c7, c7, 0 @ invalidate cache - mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) - mrc p15, 0, ip, c1, c0, 0 @ get ctrl register - bic ip, ip, #0x000f @ ............wcam - bic ip, ip, #0x2100 @ ..v....s........ - mcr p15, 0, ip, c1, c0, 0 @ ctrl register - mov pc, r0 -#elif defined(CONFIG_NETARM) - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, =NETARM_MEM_MODULE_BASE - ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] - ldr r1, =0xFFFFF000 - and r0, r1, r0 - ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE) - add r0, r1, r0 - ldr r4, =NETARM_GEN_MODULE_BASE - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - mov pc, r0 -#elif defined(CONFIG_S3C4510B) -/* Nothing done here as reseting the CPU is board specific, depending - * on external peripherals such as watchdog timers, etc. */ -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - .align 5 -.globl reset_cpu -reset_cpu: - mov pc, r0 -#else -#error No reset_cpu() defined for current CPU type -#endif +#endif /* CONFIG_SPL_BUILD */