X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=board%2Fdavedenx%2Fqong%2Fqong.c;h=ad1694b79fb7d7ef77af0a1014a9c006b731d2b1;hb=3be2bdf5dc69b3142c1162a59bc67191c9077567;hp=8a81cfc68615617b63c55ef1de496d3a1d9c9c0c;hpb=d7dc464be4ee246ecab6c7934b322b5aaecfe5f6;p=karo-tx-uboot.git diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 8a81cfc686..ad1694b79f 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -2,62 +2,56 @@ * * (c) 2009 Emcraft Systems, Ilya Yanok * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include #include -#include -#include +#include +#include +#include #include #include +#include #include -#include +#include #include "qong_fpga.h" +#include +#include DECLARE_GLOBAL_DATA_PTR; -int dram_init (void) +int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } static void qong_fpga_reset(void) { - mxc_gpio_set(QONG_FPGA_RST_PIN, 0); + gpio_set_value(QONG_FPGA_RST_PIN, 0); udelay(30); - mxc_gpio_set(QONG_FPGA_RST_PIN, 1); + gpio_set_value(QONG_FPGA_RST_PIN, 1); udelay(300); } -int board_early_init_f (void) +int board_early_init_f(void) { #ifdef CONFIG_QONG_FPGA - /* CS1: FPGA/Network Controller/GPIO */ - /* 16-bit, no DTACK */ - __REG(CSCR_U(1)) = 0x00000A01; - __REG(CSCR_L(1)) = 0x20040501; - __REG(CSCR_A(1)) = 0x04020C00; + /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(1, &cs1); /* setup pins for FPGA */ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); @@ -68,21 +62,20 @@ int board_early_init_f (void) /* FPGA reset Pin */ /* rstn = 0 */ - mxc_gpio_set(QONG_FPGA_RST_PIN, 0); - mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(QONG_FPGA_RST_PIN, 0); /* set interrupt pin as input */ - mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN); + gpio_direction_input(QONG_FPGA_IRQ_PIN); /* FPGA JTAG Interface */ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO)); - mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN); + gpio_direction_output(QONG_FPGA_TCK_PIN, 0); + gpio_direction_output(QONG_FPGA_TMS_PIN, 0); + gpio_direction_output(QONG_FPGA_TDI_PIN, 0); + gpio_direction_input(QONG_FPGA_TDO_PIN); #endif /* setup pins for UART1 */ @@ -105,12 +98,6 @@ int board_early_init_f (void) mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC)); #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -128,61 +115,27 @@ int board_early_init_f (void) mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8); + mx31_set_gpr(MUX_PGP_UH2, 1); return 0; } -int board_init (void) +int board_init(void) { /* Chip selects */ /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ - __REG(CSCR_U(0)) = ((0 << 31) | /* SP */ - (0 << 30) | /* WP */ - (0 << 28) | /* BCD */ - (0 << 24) | /* BCS */ - (0 << 22) | /* PSZ */ - (0 << 21) | /* PME */ - (0 << 20) | /* SYNC */ - (0 << 16) | /* DOL */ - (3 << 14) | /* CNC */ - (21 << 8) | /* WSC */ - (0 << 7) | /* EW */ - (0 << 4) | /* WWS */ - (6 << 0) /* EDC */ - ); - - __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */ - (1 << 24) | /* OEN */ - (3 << 20) | /* EBWA */ - (3 << 16) | /* EBWN */ - (1 << 12) | /* CSA */ - (1 << 11) | /* EBC */ - (5 << 8) | /* DSZ */ - (1 << 4) | /* CSN */ - (0 << 3) | /* PSR */ - (0 << 2) | /* CRE */ - (0 << 1) | /* WRAP */ - (1 << 0) /* CSEN */ - ); - - __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */ - (1 << 24) | /* EBRN */ - (2 << 20) | /* RWA */ - (2 << 16) | /* RWN */ - (0 << 15) | /* MUM */ - (0 << 13) | /* LAH */ - (2 << 10) | /* LBN */ - (0 << 8) | /* LBA */ - (0 << 6) | /* DWW */ - (0 << 4) | /* DCT */ - (0 << 3) | /* WWU */ - (0 << 2) | /* AGE */ - (0 << 1) | /* CNC2 */ - (0 << 0) /* FCE */ - ); + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; @@ -196,22 +149,35 @@ int board_init (void) int board_late_init(void) { u32 val; + struct pmic *p; + int ret; + + ret = pmic_init(I2C_PMIC); + if (ret) + return ret; + p = pmic_get("FSL_PMIC"); + if (!p) + return -ENODEV; /* Enable RTC battery */ - val = pmic_reg_read(REG_POWER_CTL0); - pmic_reg_write(REG_POWER_CTL0, val | COINCHEN); - pmic_reg_write(REG_INT_STATUS1, RTCRSTI); + pmic_reg_read(p, REG_POWER_CTL0, &val); + pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN); + pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI); + +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_init(); +#endif return 0; } -int checkboard (void) +int checkboard(void) { printf("Board: DAVE/DENX Qong\n"); return 0; } -int misc_init_r (void) +int misc_init_r(void) { #ifdef CONFIG_QONG_FPGA u32 tmp; @@ -236,12 +202,19 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) static void board_nand_setup(void) { - /* CS3: NAND 8-bit */ - __REG(CSCR_U(3)) = 0x00004f00; - __REG(CSCR_L(3)) = 0x20013b31; - __REG(CSCR_A(3)) = 0x00020800; - __REG(IOMUXC_GPR) |= 1 << 13; + static const struct mxc_weimcs cs3 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(3, &cs3); + + mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO)); @@ -251,27 +224,26 @@ static void board_nand_setup(void) qong_fpga_reset(); /* Enable NAND flash */ - mxc_gpio_set(15, 1); - mxc_gpio_set(14, 1); - mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN); - mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN); - mxc_gpio_set(15, 0); + gpio_set_value(15, 1); + gpio_set_value(14, 1); + gpio_direction_output(15, 0); + gpio_direction_input(16); + gpio_direction_input(14); } int qong_nand_rdy(void *chip) { udelay(1); - return mxc_gpio_get(16); + return gpio_get_value(16); } void qong_nand_select_chip(struct mtd_info *mtd, int chip) { if (chip >= 0) - mxc_gpio_set(15, 0); + gpio_set_value(15, 0); else - mxc_gpio_set(15, 1); + gpio_set_value(15, 1); }