X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=board%2Fg2000%2Fg2000.c;h=713b6995a614c9002b30f3bca94f5d52297777ff;hb=a0f21ff18a9dd4dffd4d3533613903ab1e70e14b;hp=39b5c701e02c34f3ed12f0ac94961fa33570aa72;hpb=f6e5739a68131998a5ae8aa0cf56a0316f810200;p=karo-tx-uboot.git diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 39b5c701e0..713b6995a6 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -33,32 +33,32 @@ #define MEM_SDTR1_INIT_VAL 0x00854005 #define SDRAM0_CFG_ENABLE 0x80000000 -#define CFG_SDRAM_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ int board_early_init_f (void) { #if 0 /* test-only */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000010); - mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */ - mtdcr (uictr, 0x00000010); /* set int trigger levels */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000010); + mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */ + mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #else - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ #endif #if 1 /* test-only */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ #endif return 0; @@ -73,12 +73,12 @@ int misc_init_f (void) int misc_init_r (void) { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) /* * Set NAND-FLASH GPIO signals to default */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE); #endif return (0); @@ -91,7 +91,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); @@ -114,24 +114,23 @@ int checkboard (void) long int init_sdram_static_settings(void) { -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) /* disable memcontroller so updates work */ - mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL ); - mtsdram0( mem_rtr , MEM_RTR_INIT_VAL ); - mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL ); - mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL ); - mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL ); - mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL ); + mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL); + mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL); + mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL); + mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL); + mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL); + mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); - mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); + mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE); - return (CFG_SDRAM_SIZE); /* CFG_SDRAM_SIZE is in G2000.h */ + return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long int ret; @@ -148,71 +147,21 @@ long int initdram (int board_type) return ret; } - -#if 1 /* test-only */ -void sdram_init(void) -{ - init_sdram_static_settings(); -} -#endif - - -#if 0 /* test-only */ -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} -#endif - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - #if 0 /* test-only !!! */ -int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong ap, cr; printf("\nEBC registers for PPC405GP:\n"); - mfebc(pb0ap, ap); mfebc(pb0cr, cr); + mfebc(PB0AP, ap); mfebc(PB0CR, cr); printf("0: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb1ap, ap); mfebc(pb1cr, cr); + mfebc(PB1AP, ap); mfebc(PB1CR, cr); printf("1: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb2ap, ap); mfebc(pb2cr, cr); + mfebc(PB2AP, ap); mfebc(PB2CR, cr); printf("2: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb3ap, ap); mfebc(pb3cr, cr); + mfebc(PB3AP, ap); mfebc(PB3CR, cr); printf("3: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb4ap, ap); mfebc(pb4cr, cr); + mfebc(PB4AP, ap); mfebc(PB4CR, cr); printf("4: AP=%08lx CP=%08lx\n", ap, cr); printf("\n"); @@ -220,12 +169,12 @@ int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( dumpebc, 1, 1, do_dumpebc, - "dumpebc - Dump all EBC registers\n", - NULL + "Dump all EBC registers", + "" ); -int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i; @@ -242,12 +191,12 @@ int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( dumpdcr, 1, 1, do_dumpdcr, - "dumpdcr - Dump all DCR registers\n", - NULL + "Dump all DCR registers", + "" ); -int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:"); printf("\n%04x %08x ", 947, mfspr(947)); @@ -306,7 +255,7 @@ int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( dumpspr, 1, 1, do_dumpspr, - "dumpspr - Dump all SPR registers\n", - NULL + "Dump all SPR registers", + "" ); #endif