X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=cpu%2Fbf533%2Ftraps.c;h=7e156d51106bfd98f05b4b2f1e3f60d2bd5b7f61;hb=9ce7e53abd039decea1af67aec81bbd5df7a2593;hp=248e34f3f5b0636b6380075f9e3ec9353d841d41;hpb=a20e7106928a284a6d14c066c54b72e552075b06;p=karo-tx-uboot.git

diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c
index 248e34f3f5..7e156d5110 100644
--- a/cpu/bf533/traps.c
+++ b/cpu/bf533/traps.c
@@ -1,7 +1,7 @@
 /*
  * U-boot - traps.c Routines related to interrupts and exceptions
  *
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
  *
  * This file is based on
  * No original Copyright holder listed,
@@ -29,22 +29,20 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
  */
 
 #include <common.h>
 #include <linux/types.h>
 #include <asm/errno.h>
-#include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/traps.h>
-#include <asm/page.h>
-#include <asm/machdep.h>
 #include "cpu.h"
-#include <asm/arch/anomaly.h>
 #include <asm/cplb.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
 
 void init_IRQ(void)
 {
@@ -69,7 +67,7 @@ static unsigned int cplb_sizes[4] =
 void trap_c(struct pt_regs *regs)
 {
 	unsigned int addr;
-	unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
+	unsigned long trapnr = (regs->seqstat) & EXCAUSE;
 	unsigned int i, j, size, *I0, *I1;
 	unsigned short data = 0;
 
@@ -77,7 +75,7 @@ void trap_c(struct pt_regs *regs)
 	/* 0x26 - Data CPLB Miss */
 	case VEC_CPLB_M:
 
-#ifdef ANOMALY_05000261
+#if ANOMALY_05000261
 		/*
 		 * Work around an anomaly: if we see a new DCPLB fault,
 		 * return without doing anything. Then,
@@ -119,16 +117,16 @@ void trap_c(struct pt_regs *regs)
 
 		/* Turn the cache off */
 		if (data) {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL &=
 			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-			sync();
+			SSYNC();
 		}
 
 		if (data) {
@@ -174,16 +172,16 @@ void trap_c(struct pt_regs *regs)
 		/* Turn the cache back on */
 		if (data) {
 			j = *(unsigned int *)DMEM_CONTROL;
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL =
 			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-			sync();
+			SSYNC();
 		}
 
 		break;