X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2FDU440.h;h=08271132dc2e933a5704c4cefed57393683d83f2;hb=31043e20ae748635f142483e8b7b645948687055;hp=508a0cae3d830c2fda8e5fa7f8fb447a328a9563;hpb=f61f1e150c84f5b9347fca79a4bc5f2286c545d2;p=karo-tx-uboot.git diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 508a0cae3d..08271132dc 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -5,20 +5,7 @@ * based on the Sequoia board configuration by * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -37,6 +24,10 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 +#endif + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ #define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */ @@ -51,7 +42,7 @@ #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */ #define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */ #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ @@ -60,11 +51,9 @@ #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 -#define CONFIG_SYS_PCI_IOBASE 0xe8000000 - - -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ +#define CONFIG_SYS_PCI_IOBASE 0xe8000000 +#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH +#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */ #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 @@ -77,18 +66,20 @@ #define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ -#define CONFIG_SYS_INIT_RAM_END (4 << 10) -#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -#undef CONFIG_UART1_CONSOLE #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -166,19 +157,20 @@ /* * I2C */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_I2C_CMD_TREE 1 -#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_PPC4XX +#define CONFIG_SYS_I2C_PPC4XX_CH0 +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 +#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_PPC4XX_CH1 +#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 100000 +#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F #define CONFIG_SYS_SPD_BUS_NUM 0 #define IIC1_MCP3021_ADDR 0x4d #define IIC1_USB2507_ADDR 0x2c -#ifdef CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}} -#endif +#define CONFIG_SYS_I2C_NOPROBES { {1, IIC1_USB2507_ADDR} } + #define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 @@ -253,6 +245,7 @@ int du440_phy_addr(int devnum); #endif +#define CONFIG_PPC4xx_EMAC #define CONFIG_IBM_EMAC4_V4 1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */ @@ -263,7 +256,6 @@ int du440_phy_addr(int devnum); #define CONFIG_HAS_ETH0 #define CONFIG_SYS_RX_ETH_BUFFER 128 -#define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY1_ADDR du440_phy_addr(1) @@ -289,14 +281,13 @@ int du440_phy_addr(int devnum); #include -#define CONFIG_CMD_AUTOSCRIPT -#define CONFIG_CMD_BSP +#define CONFIG_CMD_ASKENV #define CONFIG_CMD_BMP +#define CONFIG_CMD_BSP #define CONFIG_CMD_DATE -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP -#define CONFIG_CMD_DTT #define CONFIG_CMD_DIAG +#define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT @@ -308,9 +299,10 @@ int du440_phy_addr(int devnum); #define CONFIG_CMD_NFS #define CONFIG_CMD_PCI #define CONFIG_CMD_PING -#define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_USB #define CONFIG_SUPPORT_VFAT @@ -353,6 +345,7 @@ int du440_phy_addr(int devnum); * PCI stuff */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ @@ -410,25 +403,16 @@ int du440_phy_addr(int devnum); * NAND FLASH */ #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \ CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS} -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -#define CONFIG_AUTOSCRIPT 1 +#define CONFIG_SOURCE 1 #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP