X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8536DS.h;h=d4e3ef5c2c0e2399782531688664eaa0b89fc927;hb=606a76f8ef479e42ae4d06f8f3ce87e9a1c72acf;hp=9d45648605bb4762ca20e0d96efe0085ee8d5163;hpb=07355700523203c5f72018712cf0d93683f255c8;p=karo-tx-uboot.git diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9d45648605..d4e3ef5c2c 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,10 +27,48 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_MK_36BIT +#include "../board/freescale/common/ics307_clk.h" + +#ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT 1 #endif +#ifdef CONFIG_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#endif /* CONFIG_NAND_SPL */ +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH 1 +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -39,6 +77,7 @@ #define CONFIG_MPC8536DS 1 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ +#define CONFIG_SPI_FLASH 1 /* Has SPI Flash */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -54,22 +93,9 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash associated with the CDS board. - * This allows booting from a promjet. - */ -#define CONFIG_ASSUME_AMD_FLASH - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -extern unsigned long get_board_ddr_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ -#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq - from ICS307 instead of switches */ /* * These can be toggled for performance analysis, otherwise use default. @@ -91,22 +117,23 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) + * Config the L2 Cache as L2 SRAM */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull #else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif /* DDR Setup */ #define CONFIG_VERY_BIG_RAM @@ -114,7 +141,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#undef CONFIG_DDR_DLL #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -190,10 +216,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM \ +#define CONFIG_FLASH_BR_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ @@ -211,7 +237,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \ + defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#else +#undef CONFIG_SYS_RAMBOOT +#endif #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -220,6 +252,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT @@ -265,29 +298,39 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define PIXIS_VWATCH 0x24 /* Watchdog Register */ #define PIXIS_LED 0x25 /* LED Register */ +#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ + /* old pixis referenced names */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 +#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000, \ @@ -298,14 +341,24 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START \ + (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM \ +#define CONFIG_SYS_NAND_BR_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2< 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 + +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0xF0000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif +#else + #define CONFIG_ENV_IS_IN_FLASH 1 + #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 + #define CONFIG_ENV_ADDR 0xfff80000 + #else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #endif + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -603,6 +692,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -618,6 +708,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC +#endif + +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION @@ -628,6 +733,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -643,18 +749,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -680,8 +779,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_IPADDR 192.168.1.254 #define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /opt/nfsroot -#define CONFIG_BOOTFILE uImage +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_SERVERIP 192.168.1.1 @@ -700,18 +799,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8536ds/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ "fdtfile=8536ds/mpc8536ds.dtb\0" \ "bdev=sda3\0" \ - "usb_phy_type=ulpi\0" + "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \