X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2Fdavinci_sonata.h;h=b85c988b5d84f3744808cca16aa193c1c5029761;hb=3a926a304b9f7a74dbe67ae7dc4cb6c7a174c6c0;hp=0dc89ef41e2c2b329105c255a323ced809380843;hpb=1ecb758341bac03994ed045821f9c0f7d1686d07;p=karo-tx-uboot.git diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 0dc89ef41e..b85c988b5d 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -1,20 +1,7 @@ /* * Copyright (C) 2007 Sergey Kubushyn * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -51,14 +38,13 @@ #define SONATA_BOARD #define CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_SYS_USE_NOR -#define CONFIG_DISPLAY_CPUINFO +#define MACH_TYPE_SONATA 1254 +#define CONFIG_MACH_TYPE MACH_TYPE_SONATA /*===================*/ /* SoC Configuration */ /*===================*/ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SOC_DM644X /*====================================================*/ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ @@ -75,7 +61,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ #define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define CONFIG_STACKSIZE (256*1024) /* regular stack */ #define PHYS_SDRAM_1 0x80000000 /* DDR Start */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ #define DDR_4BANKS /* 4-bank DDR2 (128MB) */ @@ -89,26 +74,22 @@ #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /*===================*/ /* I2C Configuration */ /*===================*/ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /*==================================*/ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC -#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI /*=====================*/ /* Flash & Environment */ /*=====================*/ @@ -126,7 +107,6 @@ #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -#define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) #ifdef CONFIG_NOR_UART_BOOT #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ @@ -140,6 +120,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2) +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ #define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ #define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ @@ -149,11 +130,9 @@ /*==============================*/ /* U-Boot general configuration */ /*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R #undef CONFIG_BOOTDELAY #define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ @@ -162,7 +141,6 @@ #define CONFIG_VERSION_VARIABLE #define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_LONGHELP #define CONFIG_CRC32_VERIFY @@ -178,7 +156,6 @@ /*=================*/ /* U-Boot commands */ /*=================*/ -#include #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG @@ -187,23 +164,24 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES #define CONFIG_CMD_EEPROM -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR #ifdef CONFIG_SYS_USE_NAND -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS #define CONFIG_CMD_NAND #elif defined(CONFIG_SYS_USE_NOR) #define CONFIG_CMD_JFFS2 #else #error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!" #endif -/*=======================*/ -/* KGDB support (if any) */ -/*=======================*/ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ + +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS #endif + +#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */