X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2Fdevkit8000.h;h=fbcbdb3afffe991ad72a4da68f17e0826c3757d6;hb=3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7;hp=fa7a6c7d8e12060406dcaf8536622ff959ac8966;hpb=d963e84c92a63b4e6c4f2f80482a5ecbe9b24fe0;p=karo-tx-uboot.git diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index fa7a6c7d8e..baa2635c13 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -9,36 +9,27 @@ * * Configuration settings for the DevKit8000 board. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ +#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 +#define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON -#define CONFIG_SYS_TEXT_BASE 0x80008000 +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 #define CONFIG_SDRC /* The chip has SDRC controller */ @@ -53,7 +44,6 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ @@ -61,19 +51,15 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* Size of malloc() pool */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - /* initial data */ /* Hardware drivers */ - -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* DM9000 */ -#define CONFIG_NET_MULTI 1 #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x2c000000 @@ -98,16 +84,15 @@ 115200} /* MMC */ +#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 /* I2C */ #define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 #define CONFIG_DRIVER_OMAP34XX_I2C 1 /* TWL4030 */ @@ -180,7 +165,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ + "console=ttyO2,115200n8\0" \ + "mmcdev=0\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ "defaultdisplay=dvi\0" \ @@ -195,6 +181,7 @@ "run commonargs; " \ "setenv bootargs ${bootargs} " \ "root=/dev/mmcblk0p2 " \ + "rootwait " \ "${kernelopts}\0" \ "nandargs=" \ "run commonargs; " \ @@ -213,10 +200,10 @@ "${kernelopts} " \ "dnsip1=${dnsip} " \ "dnsip2=${dnsip2}\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ @@ -229,7 +216,7 @@ "dhcp ${loadaddr}; " \ "run netargs; " \ "bootm ${loadaddr}\0" \ - "autoboot=if mmc init 0; then " \ + "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ @@ -247,7 +234,6 @@ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ @@ -273,22 +259,11 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ #define CONFIG_SYS_HZ 1000 -/* The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /* NAND and environment organization */ #define PISMO1_NAND_SIZE GPMC_SIZE_128M @@ -297,17 +272,87 @@ #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_ENV_OFFSET boot_flash_off - -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* SRAM config */ +#define CONFIG_SYS_SRAM_START 0x40200000 +#define CONFIG_SYS_SRAM_SIZE 0x10000 + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SIMPLE + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ + +/* SPL OS boot options */ +#define CONFIG_SPL_OS_BOOT + +#define CONFIG_CMD_SPL +#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ +#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ + 0x400000) +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 + +#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args" + +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ + +#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) #endif /* __CONFIG_H */