X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2Fsc3.h;h=a96ffbcec3251c74bb34f97486e9aeb59d35d738;hb=230187ce266889ad465b39ded6717805379e7ffe;hp=61eb26ed84395e61b0baeab65716355ab3c2f448;hpb=a77034a8dfc7942ca08483138dccdebeacc36826;p=karo-tx-uboot.git diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 61eb26ed84..a96ffbcec3 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -6,23 +6,7 @@ * (C) Copyright 2003 * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -62,6 +46,8 @@ #define CONFIG_4xx 1 #define CONFIG_405GP 1 +#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 + #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ @@ -76,15 +62,11 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_SERIAL_MULTI -#undef CONFIG_SERIAL_SOFTWARE_FIFO -/* - * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input - * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature - */ -#if CONFIG_SERIAL_SOFTWARE_FIFO - #define CONFIG_POWER_DOWN -#endif +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() /* * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz @@ -163,7 +145,6 @@ #undef CONFIG_LOADS_ECHO /* no echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_NET_MULTI /* #define CONFIG_EEPRO100_SROM_WRITE */ /* #define CONFIG_SHOW_MAC */ #define CONFIG_EEPRO100 @@ -249,16 +230,16 @@ * IIC stuff *----------------------------------------------------------------------- */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_PPC4XX +#define CONFIG_SYS_I2C_PPC4XX_CH0 #define I2C_INIT #define I2C_ACTIVE 0 #define I2C_TRISTATE 0 -#define CONFIG_SYS_I2C_SPEED 100000 /* use the standard 100kHz speed */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* mask valid bits */ +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 +#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* mask valid bits */ #define CONFIG_RTC_DS1337 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 @@ -272,6 +253,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ @@ -379,8 +361,9 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFFE00000 -#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 /* placed last 256k */ -#define CONFIG_SYS_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ +#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */ /* @@ -463,7 +446,7 @@ /* Where the internal SRAM starts */ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* Where the internal SRAM ends (only offset) */ -#define CONFIG_SYS_INIT_RAM_END 0x0F00 +#define CONFIG_SYS_INIT_RAM_SIZE 0x0F00 /* @@ -476,24 +459,14 @@ | | | 64 Bytes | | | - CONFIG_SYS_INIT_RAM_END ------> ------------ higher address + CONFIG_SYS_INIT_RAM_SIZE ------> ------------ higher address (offset only) */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Initial value of the stack pointern in internal SRAM */ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - /* ################################################################################### */ /* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects */ /* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ @@ -527,7 +500,7 @@ #define CONFIG_SYS_EBC_CFG 0xb84ef000 -#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */ +#undef CONFIG_SDRAM_BANK0 /* use private SDRAM initialization */ #undef CONFIG_SPD_EEPROM /* @@ -542,9 +515,9 @@ #define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000 /* - Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu. + Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu. Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die - das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen + das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen auf ISA- und PCI-Zyklen) */ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000