X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2Ft3corp.h;h=9ab99244cfdbb673165703ca73628fe93366fa5b;hb=8b485ba12b0defa0c4ed3559789250238f8331a8;hp=0ecc5b10deac2f8cfe5bb3782e34040f26cb14c7;hpb=2271d3ddccfbd4a7640121669ff9b013b1fea361;p=karo-tx-uboot.git diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 0ecc5b10de..9ab99244cf 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -2,20 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -31,6 +18,10 @@ #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 +#endif + #define CONFIG_HOSTNAME t3corp /* @@ -74,8 +65,8 @@ #define CONFIG_SYS_FLASH_SIZE (64 << 20) #define CONFIG_SYS_FPGA1_BASE 0xe0000000 -#define CONFIG_SYS_FPGA2_BASE 0xe0100000 -#define CONFIG_SYS_FPGA3_BASE 0xe0200000 +#define CONFIG_SYS_FPGA2_BASE 0xe2000000 +#define CONFIG_SYS_FPGA3_BASE 0xe4000000 #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 @@ -84,28 +75,24 @@ (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ +#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ - -#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ - /* * Initial RAM & stack pointer (placed in OCM) */ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ -#define CONFIG_SYS_INIT_RAM_END (4 << 10) -#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Serial Port */ -#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /* * Environment @@ -120,10 +107,16 @@ */ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ +#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + (CONFIG_SYS_FPGA1_BASE + 0x01000000) } +#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \ + 0xbddf } /* set async read mode */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/ @@ -144,10 +137,13 @@ /* * DDR2 SDRAM */ +#define CONFIG_SYS_MBYTES_SDRAM 256 +#define CONFIG_DDR_ECC #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A +#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */ /* DDR1/2 SDRAM Device Control Register Data Values */ /* Memory Queue */ @@ -162,9 +158,6 @@ #define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 -#define CONFIG_DDR_ECC -#define CONFIG_SYS_MBYTES_SDRAM 256 - #define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK /* DDR1/2 SDRAM Device Control Register Data Values */ @@ -313,7 +306,7 @@ /* * I2C */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 #define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) @@ -354,12 +347,14 @@ "ramdisk_addr=fc200000\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ + "unlock=yes\0" \ "" /* * Commands additional to the ones defined in amcc-common.h */ #define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_ECCTEST #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM @@ -368,6 +363,7 @@ */ /* General PCI */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_PCI_CONFIG_HOST_BRIDGE @@ -417,16 +413,16 @@ #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_RE_ENABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_32MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) @@ -434,16 +430,16 @@ #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_RE_ENABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) @@ -451,16 +447,16 @@ #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_RE_ENABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT)