HDMI isfr clock source from video 27M clock.
There are one clock gate control of video27m_root in CCM,
ccm_video27m_root_cg = ((lpcg_mipi_core_cfg_clk_enable_clock_root
| lpcg_mipi_core_pll_refclk_enable_clock_root) | lpcg_vpu_rclk_enable_clock_root);
The video 27M clock depend on vpu clock or mipi core clock.
In mx6 chip, vpu can been disabled by fuse,
so for vpu disabled case, mipi core clock should enabled and make sure
27M clock on.
Add mipi core clock management in hdmi drivers to support vpu disabled
case.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit
32c8b60e0509300b504795ec96488242bbb11d3b)
static void __iomem *hdmi_base;
static struct clk *isfr_clk;
static struct clk *iahb_clk;
static void __iomem *hdmi_base;
static struct clk *isfr_clk;
static struct clk *iahb_clk;
+static struct clk *mipi_core_clk;
static spinlock_t irq_spinlock;
static spinlock_t edid_spinlock;
static unsigned int sample_rate;
static spinlock_t irq_spinlock;
static spinlock_t edid_spinlock;
static unsigned int sample_rate;
hdmi_abort_state = 0;
spin_unlock_irqrestore(&hdmi_audio_lock, flags);
hdmi_abort_state = 0;
spin_unlock_irqrestore(&hdmi_audio_lock, flags);
+ mipi_core_clk = clk_get(&hdmi_data->pdev->dev, "mipi_core");
+ if (IS_ERR(mipi_core_clk)) {
+ ret = PTR_ERR(mipi_core_clk);
+ dev_err(&hdmi_data->pdev->dev,
+ "Unable to get mipi core clk: %d\n", ret);
+ goto eclkg;
+ }
+
+ ret = clk_prepare_enable(mipi_core_clk);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Cannot enable mipi core clock: %d\n", ret);
+ goto eclke;
+ }
+
isfr_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_isfr");
if (IS_ERR(isfr_clk)) {
ret = PTR_ERR(isfr_clk);
dev_err(&hdmi_data->pdev->dev,
"Unable to get HDMI isfr clk: %d\n", ret);
isfr_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_isfr");
if (IS_ERR(isfr_clk)) {
ret = PTR_ERR(isfr_clk);
dev_err(&hdmi_data->pdev->dev,
"Unable to get HDMI isfr clk: %d\n", ret);
}
ret = clk_prepare_enable(isfr_clk);
if (ret < 0) {
dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
}
ret = clk_prepare_enable(isfr_clk);
if (ret < 0) {
dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
}
pr_debug("%s isfr_clk:%d\n", __func__,
}
pr_debug("%s isfr_clk:%d\n", __func__,
/* Disable HDMI clocks until video/audio sub-drivers are initialized */
clk_disable_unprepare(isfr_clk);
clk_disable_unprepare(iahb_clk);
/* Disable HDMI clocks until video/audio sub-drivers are initialized */
clk_disable_unprepare(isfr_clk);
clk_disable_unprepare(iahb_clk);
+ clk_disable_unprepare(mipi_core_clk);
/* Replace platform data coming in with a local struct */
platform_set_drvdata(pdev, hdmi_data);
/* Replace platform data coming in with a local struct */
platform_set_drvdata(pdev, hdmi_data);
clk_put(iahb_clk);
eclkg2:
clk_disable_unprepare(isfr_clk);
clk_put(iahb_clk);
eclkg2:
clk_disable_unprepare(isfr_clk);
+eclkg1:
+ clk_disable_unprepare(mipi_core_clk);
+eclke:
+ clk_put(mipi_core_clk);
struct fb_info *fbi;
struct clk *hdmi_isfr_clk;
struct clk *hdmi_iahb_clk;
struct fb_info *fbi;
struct clk *hdmi_isfr_clk;
struct clk *hdmi_iahb_clk;
+ struct clk *mipi_core_clk;
struct delayed_work hotplug_work;
struct delayed_work hdcp_hdp_work;
struct delayed_work hotplug_work;
struct delayed_work hdcp_hdp_work;
mxc_hdmi_phy_disable(hdmi);
clk_disable(hdmi->hdmi_iahb_clk);
clk_disable(hdmi->hdmi_isfr_clk);
mxc_hdmi_phy_disable(hdmi);
clk_disable(hdmi->hdmi_iahb_clk);
clk_disable(hdmi->hdmi_isfr_clk);
+ clk_disable(hdmi->mipi_core_clk);
"event=FB_EVENT_RESUME\n");
if (hdmi->blank == FB_BLANK_UNBLANK) {
"event=FB_EVENT_RESUME\n");
if (hdmi->blank == FB_BLANK_UNBLANK) {
+ clk_enable(hdmi->mipi_core_clk);
clk_enable(hdmi->hdmi_iahb_clk);
clk_enable(hdmi->hdmi_isfr_clk);
mxc_hdmi_phy_init(hdmi);
clk_enable(hdmi->hdmi_iahb_clk);
clk_enable(hdmi->hdmi_isfr_clk);
mxc_hdmi_phy_init(hdmi);
+ hdmi->mipi_core_clk = clk_get(&hdmi->pdev->dev, "mipi_core");
+ if (IS_ERR(hdmi->mipi_core_clk)) {
+ ret = PTR_ERR(hdmi->mipi_core_clk);
+ dev_err(&hdmi->pdev->dev,
+ "Unable to get mipi core clk: %d\n", ret);
+ goto egetclk;
+ }
+
+ ret = clk_prepare_enable(hdmi->mipi_core_clk);
+ if (ret < 0) {
+ dev_err(&hdmi->pdev->dev,
+ "Cannot enable mipi core clock: %d\n", ret);
+ goto erate;
+ }
+
hdmi->hdmi_isfr_clk = clk_get(&hdmi->pdev->dev, "hdmi_isfr");
if (IS_ERR(hdmi->hdmi_isfr_clk)) {
ret = PTR_ERR(hdmi->hdmi_isfr_clk);
hdmi->hdmi_isfr_clk = clk_get(&hdmi->pdev->dev, "hdmi_isfr");
if (IS_ERR(hdmi->hdmi_isfr_clk)) {
ret = PTR_ERR(hdmi->hdmi_isfr_clk);
erate1:
clk_put(hdmi->hdmi_isfr_clk);
egetclk1:
erate1:
clk_put(hdmi->hdmi_isfr_clk);
egetclk1:
+ clk_disable_unprepare(hdmi->mipi_core_clk);
+erate:
+ clk_put(hdmi->mipi_core_clk);
+egetclk:
dev_dbg(&hdmi->pdev->dev, "%s error exit\n", __func__);
return ret;
dev_dbg(&hdmi->pdev->dev, "%s error exit\n", __func__);
return ret;
clk_put(hdmi->hdmi_isfr_clk);
clk_disable_unprepare(hdmi->hdmi_iahb_clk);
clk_put(hdmi->hdmi_iahb_clk);
clk_put(hdmi->hdmi_isfr_clk);
clk_disable_unprepare(hdmi->hdmi_iahb_clk);
clk_put(hdmi->hdmi_iahb_clk);
+ clk_disable_unprepare(hdmi->mipi_core_clk);
+ clk_put(hdmi->mipi_core_clk);
platform_device_unregister(hdmi->pdev);
platform_device_unregister(hdmi->pdev);