From 40e7bcdee72830fa51d9e98428f1a61f9126527e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:29:08 +0200 Subject: [PATCH] arm: socfpga: cache: Enable D-Cache The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- board/altera/socfpga/socfpga_cyclone5.c | 1 + include/configs/socfpga_cyclone5.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 41498421c1..6b982778be 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -35,6 +35,7 @@ int board_early_init_f(void) int board_init(void) { icache_enable(); + dcache_enable(); /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 76979b10b8..de60bb2f06 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -18,7 +18,6 @@ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 -#define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ #define CONFIG_MISC_INIT_R @@ -26,6 +25,7 @@ #define CONFIG_SOCFPGA #define CONFIG_CLOCKS +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 /* base address for .text section */ -- 2.39.2