Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt

   1 * ARM SMMUv3 Architecture Implementation
   2
   3 The SMMUv3 architecture is a significant deparature from previous
   4 revisions, replacing the MMIO register interface with in-memory command
   5 and event queues and adding support for the ATS and PRI components of
   6 the PCIe specification.
   7
   8 ** SMMUv3 required properties:
   9
  10 - compatible        : Should include:
  11
  12                       * "arm,smmu-v3" for any SMMUv3 compliant
  13                         implementation. This entry should be last in the
  14                         compatible list.
  15
  16 - reg               : Base address and size of the SMMU.
  17
  18 - interrupts        : Non-secure interrupt list describing the wired
  19                       interrupt sources corresponding to entries in
  20                       interrupt-names. If no wired interrupts are
  21                       present then this property may be omitted.
  22
  23 - interrupt-names   : When the interrupts property is present, should
  24                       include the following:
  25                       * "eventq"    - Event Queue not empty
  26                       * "priq"      - PRI Queue not empty
  27                       * "cmdq-sync" - CMD_SYNC complete
  28                       * "gerror"    - Global Error activated
  29
  30 ** SMMUv3 optional properties:
  31
  32 - dma-coherent      : Present if DMA operations made by the SMMU (page
  33                       table walks, stream table accesses etc) are cache
  34                       coherent with the CPU.
  35
  36                       NOTE: this only applies to the SMMU itself, not
  37                       masters connected upstream of the SMMU.
  38
  39 - msi-parent        : See the generic MSI binding described in
  40                         devicetree/bindings/interrupt-controller/msi.txt
  41                       for a description of the msi-parent property.
  42
  43 - hisilicon,broken-prefetch-cmd
  44                     : Avoid sending CMD_PREFETCH_* commands to the SMMU.
  45
  46 ** Example
  47
  48         smmu@2b400000 {
  49                 compatible = "arm,smmu-v3";
  50                 reg = <0x0 0x2b400000 0x0 0x20000>;
  51                 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
  52                              <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
  53                              <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
  54                              <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
  55                 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
  56                 dma-coherent;
  57                 #iommu-cells = <0>;
  58                 msi-parent = <&its 0xff0000>;
  59         };