2 * AXS101/AXS103 Software Development Platform
4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/of_platform.h>
19 #include <asm/asm-offsets.h>
22 #include <asm/mach_desc.h>
24 #define AXS_MB_CGU 0xE0010000
25 #define AXS_MB_CREG 0xE0011000
27 #define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214)
28 #define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220)
29 #define CREG_MB_VER (AXS_MB_CREG + 0x230)
30 #define CREG_MB_CONFIG (AXS_MB_CREG + 0x234)
32 #define AXC001_CREG 0xF0001000
33 #define AXC001_GPIO_INTC 0xF0003000
35 static void __init axs10x_enable_gpio_intc_wire(void)
38 * Peripherals on CPU Card and Mother Board are wired to cpu intc via
39 * intermediate DW APB GPIO blocks (mainly for debouncing)
41 * ---------------------
42 * | snps,arc700-intc |
43 * ---------------------
45 * ------------------- -------------------
46 * | snps,dw-apb-gpio | | snps,dw-apb-gpio |
47 * ------------------- -------------------
49 * | [ Debug UART on cpu card ]
51 * ------------------------
52 * | snps,dw-apb-intc (MB)|
53 * ------------------------
55 * [eth] [uart] [... other perip on Main Board]
57 * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
58 * with stacked INTCs. In particular problem happens if its master INTC
59 * not yet instantiated. See discussion here -
60 * https://lkml.org/lkml/2015/3/4/755
62 * So setup the first gpio block as a passive pass thru and hide it from
63 * DT hardware topology - connect MB intc directly to cpu intc
64 * The GPIO "wire" needs to be init nevertheless (here)
66 * One side adv is that peripheral interrupt handling avoids one nested
69 #define GPIO_INTEN (AXC001_GPIO_INTC + 0x30)
70 #define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34)
71 #define GPIO_INTTYPE_LEVEL (AXC001_GPIO_INTC + 0x38)
72 #define GPIO_INT_POLARITY (AXC001_GPIO_INTC + 0x3c)
73 #define MB_TO_GPIO_IRQ 12
75 iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
76 iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
77 iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
78 iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
81 static inline void __init
82 write_cgu_reg(uint32_t value, void __iomem *reg, void __iomem *lock_reg)
84 unsigned int loops = 128 * 1024, ctr;
86 iowrite32(value, reg);
89 while (((ioread32(lock_reg) & 1) == 1) && ctr--) /* wait for unlock */
93 while (((ioread32(lock_reg) & 1) == 0) && ctr--) /* wait for re-lock */
97 static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
101 #ifdef CONFIG_CPU_BIG_ENDIAN
102 unsigned int pad:11, y:12, m:4, d:5;
104 unsigned int d:5, m:4, y:12, pad:11;
110 board.val = ioread32((void __iomem *)creg);
111 pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
115 static void __init axs10x_early_init(void)
120 /* Determine motherboard version */
121 if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
122 mb_rev = 3; /* HT-3 (rev3.0) */
124 mb_rev = 2; /* HT-2 (rev2.0) */
126 axs10x_enable_gpio_intc_wire();
128 scnprintf(mb, 32, "MainBoard v%d", mb_rev);
129 axs10x_print_board_ver(CREG_MB_VER, mb);
134 #define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20)
135 #define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60)
136 #define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34)
137 #define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74)
139 #define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
140 #define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120)
143 * Set up System Memory Map for ARC cpu / peripherals controllers
145 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
146 * of which maps to a corresponding 256MB aperture in Target slave memory map.
148 * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
149 * (0x0000_0000) of DDR Port 0 (slave #1)
151 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
152 * which has master/slaves on both ends.
153 * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
154 * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
155 * MB AXI Tunnel Master, which also has a mem map setup
157 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
158 * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
161 unsigned int slave_sel:4, slave_off:4, pad:24;
164 /* CPU Card target slaves */
165 #define AXC001_SLV_NONE 0
166 #define AXC001_SLV_DDR_PORT0 1
167 #define AXC001_SLV_SRAM 2
168 #define AXC001_SLV_AXI_TUNNEL 3
169 #define AXC001_SLV_AXI2APB 6
170 #define AXC001_SLV_DDR_PORT1 7
172 /* MB AXI Target slaves */
173 #define AXS_MB_SLV_NONE 0
174 #define AXS_MB_SLV_AXI_TUNNEL_CPU 1
175 #define AXS_MB_SLV_AXI_TUNNEL_HAPS 2
176 #define AXS_MB_SLV_SRAM 3
177 #define AXS_MB_SLV_CONTROL 4
180 #define AXS_MB_MST_TUNNEL_CPU 0
181 #define AXS_MB_MST_USB_OHCI 10
184 * memmap for ARC core on CPU Card
186 static const struct aperture axc001_memmap[16] = {
187 {AXC001_SLV_AXI_TUNNEL, 0x0},
188 {AXC001_SLV_AXI_TUNNEL, 0x1},
189 {AXC001_SLV_SRAM, 0x0}, /* 0x2000_0000: Local SRAM */
190 {AXC001_SLV_NONE, 0x0},
191 {AXC001_SLV_NONE, 0x0},
192 {AXC001_SLV_NONE, 0x0},
193 {AXC001_SLV_NONE, 0x0},
194 {AXC001_SLV_NONE, 0x0},
195 {AXC001_SLV_DDR_PORT0, 0x0}, /* 0x8000_0000: DDR 0..256M */
196 {AXC001_SLV_DDR_PORT0, 0x1}, /* 0x9000_0000: DDR 256..512M */
197 {AXC001_SLV_DDR_PORT0, 0x2},
198 {AXC001_SLV_DDR_PORT0, 0x3},
199 {AXC001_SLV_NONE, 0x0},
200 {AXC001_SLV_AXI_TUNNEL, 0xD},
201 {AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */
202 {AXC001_SLV_AXI2APB, 0x0}, /* CPU Card local CREG, CGU... */
206 * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
207 * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
209 static const struct aperture axc001_axi_tunnel_memmap[16] = {
210 {AXC001_SLV_AXI_TUNNEL, 0x0},
211 {AXC001_SLV_AXI_TUNNEL, 0x1},
212 {AXC001_SLV_SRAM, 0x0},
213 {AXC001_SLV_NONE, 0x0},
214 {AXC001_SLV_NONE, 0x0},
215 {AXC001_SLV_NONE, 0x0},
216 {AXC001_SLV_NONE, 0x0},
217 {AXC001_SLV_NONE, 0x0},
218 {AXC001_SLV_DDR_PORT1, 0x0},
219 {AXC001_SLV_DDR_PORT1, 0x1},
220 {AXC001_SLV_DDR_PORT1, 0x2},
221 {AXC001_SLV_DDR_PORT1, 0x3},
222 {AXC001_SLV_NONE, 0x0},
223 {AXC001_SLV_AXI_TUNNEL, 0xD},
224 {AXC001_SLV_AXI_TUNNEL, 0xE},
225 {AXC001_SLV_AXI2APB, 0x0},
229 * memmap for MB AXI Masters
230 * Same mem map for all perip controllers as well as MB AXI Tunnel Master
232 static const struct aperture axs_mb_memmap[16] = {
233 {AXS_MB_SLV_SRAM, 0x0},
234 {AXS_MB_SLV_SRAM, 0x0},
235 {AXS_MB_SLV_NONE, 0x0},
236 {AXS_MB_SLV_NONE, 0x0},
237 {AXS_MB_SLV_NONE, 0x0},
238 {AXS_MB_SLV_NONE, 0x0},
239 {AXS_MB_SLV_NONE, 0x0},
240 {AXS_MB_SLV_NONE, 0x0},
241 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8}, /* DDR on CPU Card */
242 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9}, /* DDR on CPU Card */
243 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA},
244 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB},
245 {AXS_MB_SLV_NONE, 0x0},
246 {AXS_MB_SLV_AXI_TUNNEL_HAPS, 0xD},
247 {AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */
248 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF},
251 static noinline void __init
252 axs101_set_memmap(void __iomem *base, const struct aperture map[16])
254 unsigned int slave_select, slave_offset;
257 slave_select = slave_offset = 0;
258 for (i = 0; i < 8; i++) {
259 slave_select |= map[i].slave_sel << (i << 2);
260 slave_offset |= map[i].slave_off << (i << 2);
263 iowrite32(slave_select, base + 0x0); /* SLV0 */
264 iowrite32(slave_offset, base + 0x8); /* OFFSET0 */
266 slave_select = slave_offset = 0;
267 for (i = 0; i < 8; i++) {
268 slave_select |= map[i+8].slave_sel << (i << 2);
269 slave_offset |= map[i+8].slave_off << (i << 2);
272 iowrite32(slave_select, base + 0x4); /* SLV1 */
273 iowrite32(slave_offset, base + 0xC); /* OFFSET1 */
276 static void __init axs101_early_init(void)
280 /* ARC 770D memory view */
281 axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
282 iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
284 /* AXI tunnel memory map (incoming traffic from MB into CPU Card */
285 axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
286 axc001_axi_tunnel_memmap);
287 iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
289 /* MB peripherals memory map */
290 for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
291 axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
294 iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */
296 /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
297 iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
299 /* Set up the MB interrupt system: mux interrupts to GPIO7) */
300 iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
302 /* reset ethernet and ULPI interfaces */
303 iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
305 /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
306 iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
311 #endif /* CONFIG_AXS101 */
315 #define AXC003_CGU 0xF0000000
316 #define AXC003_CREG 0xF0001000
317 #define AXC003_MST_AXI_TUNNEL 0
318 #define AXC003_MST_HS38 1
320 #define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440)
321 #define CREG_CPU_GPIO_UART_MUX (AXC003_CREG + 0x480)
322 #define CREG_CPU_TUN_IO_CTRL (AXC003_CREG + 0x494)
327 #ifdef CONFIG_CPU_BIG_ENDIAN
328 unsigned int pad:17, noupd:1, bypass:1, edge:1, high:6, low:6;
330 unsigned int low:6, high:6, edge:1, bypass:1, noupd:1, pad:17;
336 static unsigned int __init axs103_get_freq(void)
338 union pll_reg idiv, fbdiv, odiv;
339 unsigned int f = 33333333;
341 idiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 0);
342 fbdiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 4);
343 odiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 8);
345 if (idiv.bypass != 1)
346 f = f / (idiv.low + idiv.high);
348 if (fbdiv.bypass != 1)
349 f = f * (fbdiv.low + fbdiv.high);
351 if (odiv.bypass != 1)
352 f = f / (odiv.low + odiv.high);
354 f = (f + 500000) / 1000000; /* Rounding */
358 static inline unsigned int __init encode_div(unsigned int id, int upd)
365 div.bypass = id == 1 ? 1 : 0;
366 div.edge = (id%2 == 0) ? 0 : 1; /* 0 = rising */
367 div.low = (id%2 == 0) ? id >> 1 : (id >> 1)+1;
373 noinline static void __init
374 axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
376 write_cgu_reg(encode_div(id, 0),
377 (void __iomem *)AXC003_CGU + 0x80 + 0,
378 (void __iomem *)AXC003_CGU + 0x110);
380 write_cgu_reg(encode_div(fd, 0),
381 (void __iomem *)AXC003_CGU + 0x80 + 4,
382 (void __iomem *)AXC003_CGU + 0x110);
384 write_cgu_reg(encode_div(od, 1),
385 (void __iomem *)AXC003_CGU + 0x80 + 8,
386 (void __iomem *)AXC003_CGU + 0x110);
389 static void __init axs103_early_init(void)
392 * AXS103 configurations for SMP/QUAD configurations share device tree
393 * which defaults to 90 MHz. However recent failures of Quad config
394 * revealed P&R timing violations so clamp it down to safe 50 MHz
395 * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
397 * This hack is really hacky as of now. Fix it properly by getting the
398 * number of cores as return value of platform's early SMP callback
400 #ifdef CONFIG_ARC_MCIP
401 unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
403 arc_set_core_freq(50 * 1000000);
404 else if (num_cores == 2)
405 arc_set_core_freq(75 * 1000000);
408 switch (arc_get_core_freq()/1000000) {
410 axs103_set_freq(1, 1, 1);
413 axs103_set_freq(1, 30, 20);
416 axs103_set_freq(2, 45, 10);
419 axs103_set_freq(2, 54, 10);
422 axs103_set_freq(1, 30, 10);
425 axs103_set_freq(2, 45, 6);
429 * In this case, core_frequency derived from
430 * DT "clock-frequency" might not match with board value.
431 * Hence update it to match the board value.
433 arc_set_core_freq(axs103_get_freq() * 1000000);
437 pr_info("Freq is %dMHz\n", axs103_get_freq());
439 /* Memory maps already config in pre-bootloader */
441 /* set GPIO mux to UART */
442 iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
444 iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
445 (void __iomem *) CREG_CPU_TUN_IO_CTRL);
447 /* Set up the AXS_MB interrupt system.*/
448 iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
449 + (AXC003_MST_HS38 << 2)));
451 /* connect ICTL - Main Board with GPIO line */
452 iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
454 axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
462 static const char *axs101_compat[] __initconst = {
467 MACHINE_START(AXS101, "axs101")
468 .dt_compat = axs101_compat,
469 .init_early = axs101_early_init,
472 #endif /* CONFIG_AXS101 */
476 static const char *axs103_compat[] __initconst = {
481 MACHINE_START(AXS103, "axs103")
482 .dt_compat = axs103_compat,
483 .init_early = axs103_early_init,
487 * For the VDK OS-kit, to get the offset to pid and command fields
489 char coware_swa_pid_offset[TASK_PID];
490 char coware_swa_comm_offset[TASK_COMM];
492 #endif /* CONFIG_AXS103 */