arch/arm/boot/dts/armada-385-db-ap.dts

   1 /*
   2  * Device Tree file for Marvell Armada 385 Access Point Development board
   3  * (DB-88F6820-AP)
   4  *
   5  *  Copyright (C) 2014 Marvell
   6  *
   7  * Nadav Haklai <nadavh@marvell.com>
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPL or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This file is licensed under the terms of the GNU General Public
  15  *     License version 2.  This program is licensed "as is" without
  16  *     any warranty of any kind, whether express or implied.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 /dts-v1/;
  43 #include "armada-385.dtsi"
  44
  45 #include <dt-bindings/gpio/gpio.h>
  46
  47 / {
  48         model = "Marvell Armada 385 Access Point Development Board";
  49         compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
  50
  51         chosen {
  52                 stdout-path = "serial1:115200n8";
  53         };
  54
  55         memory {
  56                 device_type = "memory";
  57                 reg = <0x00000000 0x80000000>; /* 2GB */
  58         };
  59
  60         soc {
  61                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  62                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  63                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
  64                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
  65
  66                 internal-regs {
  67                         spi1: spi@10680 {
  68                                 pinctrl-names = "default";
  69                                 pinctrl-0 = <&spi1_pins>;
  70                                 status = "okay";
  71
  72                                 spi-flash@0 {
  73                                         #address-cells = <1>;
  74                                         #size-cells = <1>;
  75                                         compatible = "st,m25p128", "jedec,spi-nor";
  76                                         reg = <0>; /* Chip select 0 */
  77                                         spi-max-frequency = <54000000>;
  78                                 };
  79                         };
  80
  81                         i2c0: i2c@11000 {
  82                                 pinctrl-names = "default";
  83                                 pinctrl-0 = <&i2c0_pins>;
  84                                 status = "okay";
  85
  86                                 /*
  87                                  * This bus is wired to two EEPROM
  88                                  * sockets, one of which holding the
  89                                  * board ID used by the bootloader.
  90                                  * Erasing this EEPROM's content will
  91                                  * brick the board.
  92                                  * Use this bus with caution.
  93                                  */
  94                         };
  95
  96                         mdio@72004 {
  97                                 pinctrl-names = "default";
  98                                 pinctrl-0 = <&mdio_pins>;
  99
 100                                 phy0: ethernet-phy@1 {
 101                                         reg = <1>;
 102                                 };
 103
 104                                 phy1: ethernet-phy@4 {
 105                                         reg = <4>;
 106                                 };
 107
 108                                 phy2: ethernet-phy@6 {
 109                                         reg = <6>;
 110                                 };
 111                         };
 112
 113                         /* UART0 is exposed through the JP8 connector */
 114                         uart0: serial@12000 {
 115                                 pinctrl-names = "default";
 116                                 pinctrl-0 = <&uart0_pins>;
 117                                 status = "okay";
 118                         };
 119
 120                         /*
 121                          * UART1 is exposed through a FTDI chip
 122                          * wired to the mini-USB connector
 123                          */
 124                         uart1: serial@12100 {
 125                                 pinctrl-names = "default";
 126                                 pinctrl-0 = <&uart1_pins>;
 127                                 status = "okay";
 128                         };
 129
 130                         pinctrl@18000 {
 131                                 xhci0_vbus_pins: xhci0-vbus-pins {
 132                                         marvell,pins = "mpp44";
 133                                         marvell,function = "gpio";
 134                                 };
 135                         };
 136
 137                         ethernet@30000 {
 138                                 status = "okay";
 139                                 phy = <&phy2>;
 140                                 phy-mode = "sgmii";
 141                         };
 142
 143                         ethernet@34000 {
 144                                 status = "okay";
 145                                 phy = <&phy1>;
 146                                 phy-mode = "sgmii";
 147                         };
 148
 149                         ethernet@70000 {
 150                                 pinctrl-names = "default";
 151
 152                                 /*
 153                                  * The Reference Clock 0 is used to
 154                                  * provide a clock to the PHY
 155                                  */
 156                                 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
 157                                 status = "okay";
 158                                 phy = <&phy0>;
 159                                 phy-mode = "rgmii-id";
 160                         };
 161
 162                         nfc: flash@d0000 {
 163                                 status = "okay";
 164                                 #address-cells = <1>;
 165                                 #size-cells = <1>;
 166
 167                                 num-cs = <1>;
 168                                 nand-ecc-strength = <4>;
 169                                 nand-ecc-step-size = <512>;
 170                                 marvell,nand-keep-config;
 171                                 marvell,nand-enable-arbiter;
 172                                 nand-on-flash-bbt;
 173                         };
 174
 175                         usb3@f0000 {
 176                                 status = "okay";
 177                                 usb-phy = <&usb3_phy>;
 178                         };
 179                 };
 180
 181                 pcie-controller {
 182                         status = "okay";
 183
 184                         /*
 185                          * The three PCIe units are accessible through
 186                          * standard mini-PCIe slots on the board.
 187                          */
 188                         pcie@1,0 {
 189                                 /* Port 0, Lane 0 */
 190                                 status = "okay";
 191                         };
 192
 193                         pcie@2,0 {
 194                                 /* Port 1, Lane 0 */
 195                                 status = "okay";
 196                         };
 197
 198                         pcie@3,0 {
 199                                 /* Port 2, Lane 0 */
 200                                 status = "okay";
 201                         };
 202                 };
 203         };
 204
 205         usb3_phy: usb3_phy {
 206                 compatible = "usb-nop-xceiv";
 207                 vcc-supply = <&reg_xhci0_vbus>;
 208         };
 209
 210         reg_xhci0_vbus: xhci0-vbus {
 211                 compatible = "regulator-fixed";
 212                 pinctrl-names = "default";
 213                 pinctrl-0 = <&xhci0_vbus_pins>;
 214                 regulator-name = "xhci0-vbus";
 215                 regulator-min-microvolt = <5000000>;
 216                 regulator-max-microvolt = <5000000>;
 217                 enable-active-high;
 218                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 219         };
 220 };