arch/arm/boot/dts/atlas7.dtsi

   1 /*
   2  * DTS file for CSR SiRFatlas7 SoC
   3  *
   4  * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,atlas7";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&gic>;
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18                 serial2 = &uart2;
  19                 serial3 = &uart3;
  20                 serial4 = &uart4;
  21                 serial5 = &uart5;
  22                 serial6 = &uart6;
  23                 serial9 = &usp2;
  24                 spi1 = &spi1;
  25                 spi2 = &usp1;
  26                 spi3 = &usp2;
  27                 spi4 = &usp3;
  28         };
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <0>;
  37                 };
  38                 cpu@1 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a7";
  41                         reg = <1>;
  42                 };
  43         };
  44
  45         clocks {
  46                 xinw {
  47                         compatible = "fixed-clock";
  48                         #clock-cells = <0>;
  49                         clock-frequency = <32768>;
  50                         clock-output-names = "xinw";
  51                 };
  52                 xin {
  53                         compatible = "fixed-clock";
  54                         #clock-cells = <0>;
  55                         clock-frequency = <26000000>;
  56                         clock-output-names = "xin";
  57                 };
  58         };
  59
  60         arm-pmu {
  61                 compatible = "arm,cortex-a7-pmu";
  62                 interrupts = <0 29 4>, <0 82 4>;
  63         };
  64
  65         noc {
  66                 compatible = "simple-bus";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges = <0x10000000 0x10000000 0xc0000000>;
  70
  71                 gic: interrupt-controller@10301000 {
  72                         compatible = "arm,cortex-a9-gic";
  73                         interrupt-controller;
  74                         #interrupt-cells = <3>;
  75                         reg = <0x10301000 0x1000>,
  76                              <0x10302000 0x0100>;
  77                 };
  78
  79                 pmu_regulator: pmu_regulator@10E30020 {
  80                         compatible = "sirf,atlas7-pmu-ldo";
  81                         reg = <0x10E30020 0x4>;
  82                         ldo: ldo {
  83                                 regulator-name = "ldo";
  84                         };
  85                 };
  86
  87                 atlas7_codec: atlas7_codec@10E30000 {
  88                         #sound-dai-cells = <0>;
  89                         compatible = "sirf,atlas7-codec";
  90                         reg = <0x10E30000 0x400>;
  91                         clocks = <&car 62>;
  92                         ldo-supply = <&ldo>;
  93                 };
  94
  95                 atlas7_iacc: atlas7_iacc@10D01000 {
  96                         #sound-dai-cells = <0>;
  97                         compatible = "sirf,atlas7-iacc";
  98                         reg = <0x10D01000 0x100>;
  99                         dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
 100                                 <&dmac3 3>, <&dmac3 9>;
 101                         dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
 102                         clocks = <&car 62>;
 103                 };
 104
 105                 ipc@13240000 {
 106                         compatible = "sirf,atlas7-ipc";
 107                         ranges = <0x13240000 0x13240000 0x00010000>;
 108                         #address-cells = <1>;
 109                         #size-cells = <1>;
 110
 111                         hwspinlock {
 112                                 compatible = "sirf,hwspinlock";
 113                                 reg = <0x13240000 0x00010000>;
 114
 115                                 num-spinlocks = <30>;
 116                         };
 117
 118                         ns_m3_rproc@0 {
 119                                 compatible = "sirf,ns2m30-rproc";
 120                                 reg = <0x13240000 0x00010000>;
 121                                 interrupts = <0 123 0>;
 122                         };
 123
 124                         ns_m3_rproc@1 {
 125                                 compatible = "sirf,ns2m31-rproc";
 126                                 reg = <0x13240000 0x00010000>;
 127                                 interrupts = <0 126 0>;
 128                         };
 129
 130                         ns_kal_rproc@0 {
 131                                 compatible = "sirf,ns2kal0-rproc";
 132                                 reg = <0x13240000 0x00010000>;
 133                                 interrupts = <0 124 0>;
 134                         };
 135
 136                         ns_kal_rproc@1 {
 137                                 compatible = "sirf,ns2kal1-rproc";
 138                                 reg = <0x13240000 0x00010000>;
 139                                 interrupts = <0 127 0>;
 140                         };
 141                 };
 142
 143                 pinctrl: ioc@18880000 {
 144                         compatible = "sirf,atlas7-ioc";
 145                         reg = <0x18880000 0x1000>,
 146                                 <0x10E40000 0x1000>;
 147
 148                         audio_ac97_pmx: audio_ac97@0 {
 149                                 audio_ac97 {
 150                                         groups = "audio_ac97_grp";
 151                                         function = "audio_ac97";
 152                                 };
 153                         };
 154
 155                         audio_func_dbg_pmx: audio_func_dbg@0 {
 156                                 audio_func_dbg {
 157                                         groups = "audio_func_dbg_grp";
 158                                         function = "audio_func_dbg";
 159                                 };
 160                         };
 161
 162                         audio_i2s_pmx: audio_i2s@0 {
 163                                 audio_i2s {
 164                                         groups = "audio_i2s_grp";
 165                                         function = "audio_i2s";
 166                                 };
 167                         };
 168
 169                         audio_i2s_2ch_pmx: audio_i2s_2ch@0 {
 170                                 audio_i2s_2ch {
 171                                         groups = "audio_i2s_2ch_grp";
 172                                         function = "audio_i2s_2ch";
 173                                 };
 174                         };
 175
 176                         audio_i2s_extclk_pmx: audio_i2s_extclk@0 {
 177                                 audio_i2s_extclk {
 178                                         groups = "audio_i2s_extclk_grp";
 179                                         function = "audio_i2s_extclk";
 180                                 };
 181                         };
 182
 183                         audio_uart0_pmx: audio_uart0@0 {
 184                                 audio_uart0 {
 185                                         groups = "audio_uart0_grp";
 186                                         function = "audio_uart0";
 187                                 };
 188                         };
 189
 190                         audio_uart1_pmx: audio_uart1@0 {
 191                                 audio_uart1 {
 192                                         groups = "audio_uart1_grp";
 193                                         function = "audio_uart1";
 194                                 };
 195                         };
 196
 197                         audio_uart2_pmx0: audio_uart2@0 {
 198                                 audio_uart2_0 {
 199                                         groups = "audio_uart2_grp0";
 200                                         function = "audio_uart2_m0";
 201                                 };
 202                         };
 203
 204                         audio_uart2_pmx1: audio_uart2@1 {
 205                                 audio_uart2_1 {
 206                                         groups = "audio_uart2_grp1";
 207                                         function = "audio_uart2_m1";
 208                                 };
 209                         };
 210
 211                         c_can_trnsvr_pmx: c_can_trnsvr@0 {
 212                                 c_can_trnsvr {
 213                                         groups = "c_can_trnsvr_grp";
 214                                         function = "c_can_trnsvr";
 215                                 };
 216                         };
 217
 218                         c0_can_pmx0: c0_can@0 {
 219                                 c0_can_0 {
 220                                         groups = "c0_can_grp0";
 221                                         function = "c0_can_m0";
 222                                 };
 223                         };
 224
 225                         c0_can_pmx1: c0_can@1 {
 226                                 c0_can_1 {
 227                                         groups = "c0_can_grp1";
 228                                         function = "c0_can_m1";
 229                                 };
 230                         };
 231
 232                         c1_can_pmx0: c1_can@0 {
 233                                 c1_can_0 {
 234                                         groups = "c1_can_grp0";
 235                                         function = "c1_can_m0";
 236                                 };
 237                         };
 238
 239                         c1_can_pmx1: c1_can@1 {
 240                                 c1_can_1 {
 241                                         groups = "c1_can_grp1";
 242                                         function = "c1_can_m1";
 243                                 };
 244                         };
 245
 246                         c1_can_pmx2: c1_can@2 {
 247                                 c1_can_2 {
 248                                         groups = "c1_can_grp2";
 249                                         function = "c1_can_m2";
 250                                 };
 251                         };
 252
 253                         ca_audio_lpc_pmx: ca_audio_lpc@0 {
 254                                 ca_audio_lpc {
 255                                         groups = "ca_audio_lpc_grp";
 256                                         function = "ca_audio_lpc";
 257                                 };
 258                         };
 259
 260                         ca_bt_lpc_pmx: ca_bt_lpc@0 {
 261                                 ca_bt_lpc {
 262                                         groups = "ca_bt_lpc_grp";
 263                                         function = "ca_bt_lpc";
 264                                 };
 265                         };
 266
 267                         ca_coex_pmx: ca_coex@0 {
 268                                 ca_coex {
 269                                         groups = "ca_coex_grp";
 270                                         function = "ca_coex";
 271                                 };
 272                         };
 273
 274                         ca_curator_lpc_pmx: ca_curator_lpc@0 {
 275                                 ca_curator_lpc {
 276                                         groups = "ca_curator_lpc_grp";
 277                                         function = "ca_curator_lpc";
 278                                 };
 279                         };
 280
 281                         ca_pcm_debug_pmx: ca_pcm_debug@0 {
 282                                 ca_pcm_debug {
 283                                         groups = "ca_pcm_debug_grp";
 284                                         function = "ca_pcm_debug";
 285                                 };
 286                         };
 287
 288                         ca_pio_pmx: ca_pio@0 {
 289                                 ca_pio {
 290                                         groups = "ca_pio_grp";
 291                                         function = "ca_pio";
 292                                 };
 293                         };
 294
 295                         ca_sdio_debug_pmx: ca_sdio_debug@0 {
 296                                 ca_sdio_debug {
 297                                         groups = "ca_sdio_debug_grp";
 298                                         function = "ca_sdio_debug";
 299                                 };
 300                         };
 301
 302                         ca_spi_pmx: ca_spi@0 {
 303                                 ca_spi {
 304                                         groups = "ca_spi_grp";
 305                                         function = "ca_spi";
 306                                 };
 307                         };
 308
 309                         ca_trb_pmx: ca_trb@0 {
 310                                 ca_trb {
 311                                         groups = "ca_trb_grp";
 312                                         function = "ca_trb";
 313                                 };
 314                         };
 315
 316                         ca_uart_debug_pmx: ca_uart_debug@0 {
 317                                 ca_uart_debug {
 318                                         groups = "ca_uart_debug_grp";
 319                                         function = "ca_uart_debug";
 320                                 };
 321                         };
 322
 323                         clkc_pmx0: clkc@0 {
 324                                 clkc_0 {
 325                                         groups = "clkc_grp0";
 326                                         function = "clkc_m0";
 327                                 };
 328                         };
 329
 330                         clkc_pmx1: clkc@1 {
 331                                 clkc_1 {
 332                                         groups = "clkc_grp1";
 333                                         function = "clkc_m1";
 334                                 };
 335                         };
 336
 337                         gn_gnss_i2c_pmx: gn_gnss_i2c@0 {
 338                                 gn_gnss_i2c {
 339                                         groups = "gn_gnss_i2c_grp";
 340                                         function = "gn_gnss_i2c";
 341                                 };
 342                         };
 343
 344                         gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 {
 345                                 gn_gnss_uart_nopause {
 346                                         groups = "gn_gnss_uart_nopause_grp";
 347                                         function = "gn_gnss_uart_nopause";
 348                                 };
 349                         };
 350
 351                         gn_gnss_uart_pmx: gn_gnss_uart@0 {
 352                                 gn_gnss_uart {
 353                                         groups = "gn_gnss_uart_grp";
 354                                         function = "gn_gnss_uart";
 355                                 };
 356                         };
 357
 358                         gn_trg_spi_pmx0: gn_trg_spi@0 {
 359                                 gn_trg_spi_0 {
 360                                         groups = "gn_trg_spi_grp0";
 361                                         function = "gn_trg_spi_m0";
 362                                 };
 363                         };
 364
 365                         gn_trg_spi_pmx1: gn_trg_spi@1 {
 366                                 gn_trg_spi_1 {
 367                                         groups = "gn_trg_spi_grp1";
 368                                         function = "gn_trg_spi_m1";
 369                                 };
 370                         };
 371
 372                         cvbs_dbg_pmx: cvbs_dbg@0 {
 373                                 cvbs_dbg {
 374                                         groups = "cvbs_dbg_grp";
 375                                         function = "cvbs_dbg";
 376                                 };
 377                         };
 378
 379                         cvbs_dbg_test_pmx0: cvbs_dbg_test@0 {
 380                                 cvbs_dbg_test_0 {
 381                                         groups = "cvbs_dbg_test_grp0";
 382                                         function = "cvbs_dbg_test_m0";
 383                                 };
 384                         };
 385
 386                         cvbs_dbg_test_pmx1: cvbs_dbg_test@1 {
 387                                 cvbs_dbg_test_1 {
 388                                         groups = "cvbs_dbg_test_grp1";
 389                                         function = "cvbs_dbg_test_m1";
 390                                 };
 391                         };
 392
 393                         cvbs_dbg_test_pmx2: cvbs_dbg_test@2 {
 394                                 cvbs_dbg_test_2 {
 395                                         groups = "cvbs_dbg_test_grp2";
 396                                         function = "cvbs_dbg_test_m2";
 397                                 };
 398                         };
 399
 400                         cvbs_dbg_test_pmx3: cvbs_dbg_test@3 {
 401                                 cvbs_dbg_test_3 {
 402                                         groups = "cvbs_dbg_test_grp3";
 403                                         function = "cvbs_dbg_test_m3";
 404                                 };
 405                         };
 406
 407                         cvbs_dbg_test_pmx4: cvbs_dbg_test@4 {
 408                                 cvbs_dbg_test_4 {
 409                                         groups = "cvbs_dbg_test_grp4";
 410                                         function = "cvbs_dbg_test_m4";
 411                                 };
 412                         };
 413
 414                         cvbs_dbg_test_pmx5: cvbs_dbg_test@5 {
 415                                 cvbs_dbg_test_5 {
 416                                         groups = "cvbs_dbg_test_grp5";
 417                                         function = "cvbs_dbg_test_m5";
 418                                 };
 419                         };
 420
 421                         cvbs_dbg_test_pmx6: cvbs_dbg_test@6 {
 422                                 cvbs_dbg_test_6 {
 423                                         groups = "cvbs_dbg_test_grp6";
 424                                         function = "cvbs_dbg_test_m6";
 425                                 };
 426                         };
 427
 428                         cvbs_dbg_test_pmx7: cvbs_dbg_test@7 {
 429                                 cvbs_dbg_test_7 {
 430                                         groups = "cvbs_dbg_test_grp7";
 431                                         function = "cvbs_dbg_test_m7";
 432                                 };
 433                         };
 434
 435                         cvbs_dbg_test_pmx8: cvbs_dbg_test@8 {
 436                                 cvbs_dbg_test_8 {
 437                                         groups = "cvbs_dbg_test_grp8";
 438                                         function = "cvbs_dbg_test_m8";
 439                                 };
 440                         };
 441
 442                         cvbs_dbg_test_pmx9: cvbs_dbg_test@9 {
 443                                 cvbs_dbg_test_9 {
 444                                         groups = "cvbs_dbg_test_grp9";
 445                                         function = "cvbs_dbg_test_m9";
 446                                 };
 447                         };
 448
 449                         cvbs_dbg_test_pmx10: cvbs_dbg_test@10 {
 450                                 cvbs_dbg_test_10 {
 451                                         groups = "cvbs_dbg_test_grp10";
 452                                         function = "cvbs_dbg_test_m10";
 453                                 };
 454                         };
 455
 456                         cvbs_dbg_test_pmx11: cvbs_dbg_test@11 {
 457                                 cvbs_dbg_test_11 {
 458                                         groups = "cvbs_dbg_test_grp11";
 459                                         function = "cvbs_dbg_test_m11";
 460                                 };
 461                         };
 462
 463                         cvbs_dbg_test_pmx12: cvbs_dbg_test@12 {
 464                                 cvbs_dbg_test_12 {
 465                                         groups = "cvbs_dbg_test_grp12";
 466                                         function = "cvbs_dbg_test_m12";
 467                                 };
 468                         };
 469
 470                         cvbs_dbg_test_pmx13: cvbs_dbg_test@13 {
 471                                 cvbs_dbg_test_13 {
 472                                         groups = "cvbs_dbg_test_grp13";
 473                                         function = "cvbs_dbg_test_m13";
 474                                 };
 475                         };
 476
 477                         cvbs_dbg_test_pmx14: cvbs_dbg_test@14 {
 478                                 cvbs_dbg_test_14 {
 479                                         groups = "cvbs_dbg_test_grp14";
 480                                         function = "cvbs_dbg_test_m14";
 481                                 };
 482                         };
 483
 484                         cvbs_dbg_test_pmx15: cvbs_dbg_test@15 {
 485                                 cvbs_dbg_test_15 {
 486                                         groups = "cvbs_dbg_test_grp15";
 487                                         function = "cvbs_dbg_test_m15";
 488                                 };
 489                         };
 490
 491                         gn_gnss_power_pmx: gn_gnss_power@0 {
 492                                 gn_gnss_power {
 493                                         groups = "gn_gnss_power_grp";
 494                                         function = "gn_gnss_power";
 495                                 };
 496                         };
 497
 498                         gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 {
 499                                 gn_gnss_sw_status {
 500                                         groups = "gn_gnss_sw_status_grp";
 501                                         function = "gn_gnss_sw_status";
 502                                 };
 503                         };
 504
 505                         gn_gnss_eclk_pmx: gn_gnss_eclk@0 {
 506                                 gn_gnss_eclk {
 507                                         groups = "gn_gnss_eclk_grp";
 508                                         function = "gn_gnss_eclk";
 509                                 };
 510                         };
 511
 512                         gn_gnss_irq1_pmx0: gn_gnss_irq1@0 {
 513                                 gn_gnss_irq1_0 {
 514                                         groups = "gn_gnss_irq1_grp0";
 515                                         function = "gn_gnss_irq1_m0";
 516                                 };
 517                         };
 518
 519                         gn_gnss_irq2_pmx0: gn_gnss_irq2@0 {
 520                                 gn_gnss_irq2_0 {
 521                                         groups = "gn_gnss_irq2_grp0";
 522                                         function = "gn_gnss_irq2_m0";
 523                                 };
 524                         };
 525
 526                         gn_gnss_tm_pmx: gn_gnss_tm@0 {
 527                                 gn_gnss_tm {
 528                                         groups = "gn_gnss_tm_grp";
 529                                         function = "gn_gnss_tm";
 530                                 };
 531                         };
 532
 533                         gn_gnss_tsync_pmx: gn_gnss_tsync@0 {
 534                                 gn_gnss_tsync {
 535                                         groups = "gn_gnss_tsync_grp";
 536                                         function = "gn_gnss_tsync";
 537                                 };
 538                         };
 539
 540                         gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 {
 541                                 gn_io_gnsssys_sw_cfg {
 542                                         groups = "gn_io_gnsssys_sw_cfg_grp";
 543                                         function = "gn_io_gnsssys_sw_cfg";
 544                                 };
 545                         };
 546
 547                         gn_trg_pmx0: gn_trg@0 {
 548                                 gn_trg_0 {
 549                                         groups = "gn_trg_grp0";
 550                                         function = "gn_trg_m0";
 551                                 };
 552                         };
 553
 554                         gn_trg_pmx1: gn_trg@1 {
 555                                 gn_trg_1 {
 556                                         groups = "gn_trg_grp1";
 557                                         function = "gn_trg_m1";
 558                                 };
 559                         };
 560
 561                         gn_trg_shutdown_pmx0: gn_trg_shutdown@0 {
 562                                 gn_trg_shutdown_0 {
 563                                         groups = "gn_trg_shutdown_grp0";
 564                                         function = "gn_trg_shutdown_m0";
 565                                 };
 566                         };
 567
 568                         gn_trg_shutdown_pmx1: gn_trg_shutdown@1 {
 569                                 gn_trg_shutdown_1 {
 570                                         groups = "gn_trg_shutdown_grp1";
 571                                         function = "gn_trg_shutdown_m1";
 572                                 };
 573                         };
 574
 575                         gn_trg_shutdown_pmx2: gn_trg_shutdown@2 {
 576                                 gn_trg_shutdown_2 {
 577                                         groups = "gn_trg_shutdown_grp2";
 578                                         function = "gn_trg_shutdown_m2";
 579                                 };
 580                         };
 581
 582                         gn_trg_shutdown_pmx3: gn_trg_shutdown@3 {
 583                                 gn_trg_shutdown_3 {
 584                                         groups = "gn_trg_shutdown_grp3";
 585                                         function = "gn_trg_shutdown_m3";
 586                                 };
 587                         };
 588
 589                         i2c0_pmx: i2c0@0 {
 590                                 i2c0 {
 591                                         groups = "i2c0_grp";
 592                                         function = "i2c0";
 593                                 };
 594                         };
 595
 596                         i2c1_pmx: i2c1@0 {
 597                                 i2c1 {
 598                                         groups = "i2c1_grp";
 599                                         function = "i2c1";
 600                                 };
 601                         };
 602
 603                         jtag_pmx0: jtag@0 {
 604                                 jtag_0 {
 605                                         groups = "jtag_grp0";
 606                                         function = "jtag_m0";
 607                                 };
 608                         };
 609
 610                         ks_kas_spi_pmx0: ks_kas_spi@0 {
 611                                 ks_kas_spi_0 {
 612                                         groups = "ks_kas_spi_grp0";
 613                                         function = "ks_kas_spi_m0";
 614                                 };
 615                         };
 616
 617                         ld_ldd_pmx: ld_ldd@0 {
 618                                 ld_ldd {
 619                                         groups = "ld_ldd_grp";
 620                                         function = "ld_ldd";
 621                                 };
 622                         };
 623
 624                         ld_ldd_16bit_pmx: ld_ldd_16bit@0 {
 625                                 ld_ldd_16bit {
 626                                         groups = "ld_ldd_16bit_grp";
 627                                         function = "ld_ldd_16bit";
 628                                 };
 629                         };
 630
 631                         ld_ldd_fck_pmx: ld_ldd_fck@0 {
 632                                 ld_ldd_fck {
 633                                         groups = "ld_ldd_fck_grp";
 634                                         function = "ld_ldd_fck";
 635                                 };
 636                         };
 637
 638                         ld_ldd_lck_pmx: ld_ldd_lck@0 {
 639                                 ld_ldd_lck {
 640                                         groups = "ld_ldd_lck_grp";
 641                                         function = "ld_ldd_lck";
 642                                 };
 643                         };
 644
 645                         lr_lcdrom_pmx: lr_lcdrom@0 {
 646                                 lr_lcdrom {
 647                                         groups = "lr_lcdrom_grp";
 648                                         function = "lr_lcdrom";
 649                                 };
 650                         };
 651
 652                         lvds_analog_pmx: lvds_analog@0 {
 653                                 lvds_analog {
 654                                         groups = "lvds_analog_grp";
 655                                         function = "lvds_analog";
 656                                 };
 657                         };
 658
 659                         nd_df_pmx: nd_df@0 {
 660                                 nd_df {
 661                                         groups = "nd_df_grp";
 662                                         function = "nd_df";
 663                                 };
 664                         };
 665
 666                         nd_df_nowp_pmx: nd_df_nowp@0 {
 667                                 nd_df_nowp {
 668                                         groups = "nd_df_nowp_grp";
 669                                         function = "nd_df_nowp";
 670                                 };
 671                         };
 672
 673                         ps_pmx: ps@0 {
 674                                 ps {
 675                                         groups = "ps_grp";
 676                                         function = "ps";
 677                                 };
 678                         };
 679
 680                         pwc_core_on_pmx: pwc_core_on@0 {
 681                                 pwc_core_on {
 682                                         groups = "pwc_core_on_grp";
 683                                         function = "pwc_core_on";
 684                                 };
 685                         };
 686
 687                         pwc_ext_on_pmx: pwc_ext_on@0 {
 688                                 pwc_ext_on {
 689                                         groups = "pwc_ext_on_grp";
 690                                         function = "pwc_ext_on";
 691                                 };
 692                         };
 693
 694                         pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 {
 695                                 pwc_gpio3_clk {
 696                                         groups = "pwc_gpio3_clk_grp";
 697                                         function = "pwc_gpio3_clk";
 698                                 };
 699                         };
 700
 701                         pwc_io_on_pmx: pwc_io_on@0 {
 702                                 pwc_io_on {
 703                                         groups = "pwc_io_on_grp";
 704                                         function = "pwc_io_on";
 705                                 };
 706                         };
 707
 708                         pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 {
 709                                 pwc_lowbatt_b_0 {
 710                                         groups = "pwc_lowbatt_b_grp0";
 711                                         function = "pwc_lowbatt_b_m0";
 712                                 };
 713                         };
 714
 715                         pwc_mem_on_pmx: pwc_mem_on@0 {
 716                                 pwc_mem_on {
 717                                         groups = "pwc_mem_on_grp";
 718                                         function = "pwc_mem_on";
 719                                 };
 720                         };
 721
 722                         pwc_on_key_b_pmx0: pwc_on_key_b@0 {
 723                                 pwc_on_key_b_0 {
 724                                         groups = "pwc_on_key_b_grp0";
 725                                         function = "pwc_on_key_b_m0";
 726                                 };
 727                         };
 728
 729                         pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 {
 730                                 pwc_wakeup_src0 {
 731                                         groups = "pwc_wakeup_src0_grp";
 732                                         function = "pwc_wakeup_src0";
 733                                 };
 734                         };
 735
 736                         pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 {
 737                                 pwc_wakeup_src1 {
 738                                         groups = "pwc_wakeup_src1_grp";
 739                                         function = "pwc_wakeup_src1";
 740                                 };
 741                         };
 742
 743                         pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 {
 744                                 pwc_wakeup_src2 {
 745                                         groups = "pwc_wakeup_src2_grp";
 746                                         function = "pwc_wakeup_src2";
 747                                 };
 748                         };
 749
 750                         pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 {
 751                                 pwc_wakeup_src3 {
 752                                         groups = "pwc_wakeup_src3_grp";
 753                                         function = "pwc_wakeup_src3";
 754                                 };
 755                         };
 756
 757                         pw_cko0_pmx0: pw_cko0@0 {
 758                                 pw_cko0_0 {
 759                                         groups = "pw_cko0_grp0";
 760                                         function = "pw_cko0_m0";
 761                                 };
 762                         };
 763
 764                         pw_cko0_pmx1: pw_cko0@1 {
 765                                 pw_cko0_1 {
 766                                         groups = "pw_cko0_grp1";
 767                                         function = "pw_cko0_m1";
 768                                 };
 769                         };
 770
 771                         pw_cko0_pmx2: pw_cko0@2 {
 772                                 pw_cko0_2 {
 773                                         groups = "pw_cko0_grp2";
 774                                         function = "pw_cko0_m2";
 775                                 };
 776                         };
 777
 778                         pw_cko1_pmx0: pw_cko1@0 {
 779                                 pw_cko1_0 {
 780                                         groups = "pw_cko1_grp0";
 781                                         function = "pw_cko1_m0";
 782                                 };
 783                         };
 784
 785                         pw_cko1_pmx1: pw_cko1@1 {
 786                                 pw_cko1_1 {
 787                                         groups = "pw_cko1_grp1";
 788                                         function = "pw_cko1_m1";
 789                                 };
 790                         };
 791
 792                         pw_i2s01_clk_pmx0: pw_i2s01_clk@0 {
 793                                 pw_i2s01_clk_0 {
 794                                         groups = "pw_i2s01_clk_grp0";
 795                                         function = "pw_i2s01_clk_m0";
 796                                 };
 797                         };
 798
 799                         pw_i2s01_clk_pmx1: pw_i2s01_clk@1 {
 800                                 pw_i2s01_clk_1 {
 801                                         groups = "pw_i2s01_clk_grp1";
 802                                         function = "pw_i2s01_clk_m1";
 803                                 };
 804                         };
 805
 806                         pw_pwm0_pmx: pw_pwm0@0 {
 807                                 pw_pwm0 {
 808                                         groups = "pw_pwm0_grp";
 809                                         function = "pw_pwm0";
 810                                 };
 811                         };
 812
 813                         pw_pwm1_pmx: pw_pwm1@0 {
 814                                 pw_pwm1 {
 815                                         groups = "pw_pwm1_grp";
 816                                         function = "pw_pwm1";
 817                                 };
 818                         };
 819
 820                         pw_pwm2_pmx0: pw_pwm2@0 {
 821                                 pw_pwm2_0 {
 822                                         groups = "pw_pwm2_grp0";
 823                                         function = "pw_pwm2_m0";
 824                                 };
 825                         };
 826
 827                         pw_pwm2_pmx1: pw_pwm2@1 {
 828                                 pw_pwm2_1 {
 829                                         groups = "pw_pwm2_grp1";
 830                                         function = "pw_pwm2_m1";
 831                                 };
 832                         };
 833
 834                         pw_pwm3_pmx0: pw_pwm3@0 {
 835                                 pw_pwm3_0 {
 836                                         groups = "pw_pwm3_grp0";
 837                                         function = "pw_pwm3_m0";
 838                                 };
 839                         };
 840
 841                         pw_pwm3_pmx1: pw_pwm3@1 {
 842                                 pw_pwm3_1 {
 843                                         groups = "pw_pwm3_grp1";
 844                                         function = "pw_pwm3_m1";
 845                                 };
 846                         };
 847
 848                         pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 {
 849                                 pw_pwm_cpu_vol_0 {
 850                                         groups = "pw_pwm_cpu_vol_grp0";
 851                                         function = "pw_pwm_cpu_vol_m0";
 852                                 };
 853                         };
 854
 855                         pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 {
 856                                 pw_pwm_cpu_vol_1 {
 857                                         groups = "pw_pwm_cpu_vol_grp1";
 858                                         function = "pw_pwm_cpu_vol_m1";
 859                                 };
 860                         };
 861
 862                         pw_backlight_pmx0: pw_backlight@0 {
 863                                 pw_backlight_0 {
 864                                         groups = "pw_backlight_grp0";
 865                                         function = "pw_backlight_m0";
 866                                 };
 867                         };
 868
 869                         pw_backlight_pmx1: pw_backlight@1 {
 870                                 pw_backlight_1 {
 871                                         groups = "pw_backlight_grp1";
 872                                         function = "pw_backlight_m1";
 873                                 };
 874                         };
 875
 876                         rg_eth_mac_pmx: rg_eth_mac@0 {
 877                                 rg_eth_mac {
 878                                         groups = "rg_eth_mac_grp";
 879                                         function = "rg_eth_mac";
 880                                 };
 881                         };
 882
 883                         rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 {
 884                                 rg_gmac_phy_intr_n {
 885                                         groups = "rg_gmac_phy_intr_n_grp";
 886                                         function = "rg_gmac_phy_intr_n";
 887                                 };
 888                         };
 889
 890                         rg_rgmii_mac_pmx: rg_rgmii_mac@0 {
 891                                 rg_rgmii_mac {
 892                                         groups = "rg_rgmii_mac_grp";
 893                                         function = "rg_rgmii_mac";
 894                                 };
 895                         };
 896
 897                         rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 {
 898                                 rg_rgmii_phy_ref_clk_0 {
 899                                         groups =
 900                                                 "rg_rgmii_phy_ref_clk_grp0";
 901                                         function =
 902                                                 "rg_rgmii_phy_ref_clk_m0";
 903                                 };
 904                         };
 905
 906                         rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 {
 907                                 rg_rgmii_phy_ref_clk_1 {
 908                                         groups =
 909                                                 "rg_rgmii_phy_ref_clk_grp1";
 910                                         function =
 911                                                 "rg_rgmii_phy_ref_clk_m1";
 912                                 };
 913                         };
 914
 915                         sd0_pmx: sd0@0 {
 916                                 sd0 {
 917                                         groups = "sd0_grp";
 918                                         function = "sd0";
 919                                 };
 920                         };
 921
 922                         sd0_4bit_pmx: sd0_4bit@0 {
 923                                 sd0_4bit {
 924                                         groups = "sd0_4bit_grp";
 925                                         function = "sd0_4bit";
 926                                 };
 927                         };
 928
 929                         sd1_pmx: sd1@0 {
 930                                 sd1 {
 931                                         groups = "sd1_grp";
 932                                         function = "sd1";
 933                                 };
 934                         };
 935
 936                         sd1_4bit_pmx0: sd1_4bit@0 {
 937                                 sd1_4bit_0 {
 938                                         groups = "sd1_4bit_grp0";
 939                                         function = "sd1_4bit_m0";
 940                                 };
 941                         };
 942
 943                         sd1_4bit_pmx1: sd1_4bit@1 {
 944                                 sd1_4bit_1 {
 945                                         groups = "sd1_4bit_grp1";
 946                                         function = "sd1_4bit_m1";
 947                                 };
 948                         };
 949
 950                         sd2_pmx0: sd2@0 {
 951                                 sd2_0 {
 952                                         groups = "sd2_grp0";
 953                                         function = "sd2_m0";
 954                                 };
 955                         };
 956
 957                         sd2_no_cdb_pmx0: sd2_no_cdb@0 {
 958                                 sd2_no_cdb_0 {
 959                                         groups = "sd2_no_cdb_grp0";
 960                                         function = "sd2_no_cdb_m0";
 961                                 };
 962                         };
 963
 964                         sd3_pmx: sd3@0 {
 965                                 sd3 {
 966                                         groups = "sd3_grp";
 967                                         function = "sd3";
 968                                 };
 969                         };
 970
 971                         sd5_pmx: sd5@0 {
 972                                 sd5 {
 973                                         groups = "sd5_grp";
 974                                         function = "sd5";
 975                                 };
 976                         };
 977
 978                         sd6_pmx0: sd6@0 {
 979                                 sd6_0 {
 980                                         groups = "sd6_grp0";
 981                                         function = "sd6_m0";
 982                                 };
 983                         };
 984
 985                         sd6_pmx1: sd6@1 {
 986                                 sd6_1 {
 987                                         groups = "sd6_grp1";
 988                                         function = "sd6_m1";
 989                                 };
 990                         };
 991
 992                         sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 {
 993                                 sp0_ext_ldo_on {
 994                                         groups = "sp0_ext_ldo_on_grp";
 995                                         function = "sp0_ext_ldo_on";
 996                                 };
 997                         };
 998
 999                         sp0_qspi_pmx: sp0_qspi@0 {
1000                                 sp0_qspi {
1001                                         groups = "sp0_qspi_grp";
1002                                         function = "sp0_qspi";
1003                                 };
1004                         };
1005
1006                         sp1_spi_pmx: sp1_spi@0 {
1007                                 sp1_spi {
1008                                         groups = "sp1_spi_grp";
1009                                         function = "sp1_spi";
1010                                 };
1011                         };
1012
1013                         tpiu_trace_pmx: tpiu_trace@0 {
1014                                 tpiu_trace {
1015                                         groups = "tpiu_trace_grp";
1016                                         function = "tpiu_trace";
1017                                 };
1018                         };
1019
1020                         uart0_pmx: uart0@0 {
1021                                 uart0 {
1022                                         groups = "uart0_grp";
1023                                         function = "uart0";
1024                                 };
1025                         };
1026
1027                         uart0_nopause_pmx: uart0_nopause@0 {
1028                                 uart0_nopause {
1029                                         groups = "uart0_nopause_grp";
1030                                         function = "uart0_nopause";
1031                                 };
1032                         };
1033
1034                         uart1_pmx: uart1@0 {
1035                                 uart1 {
1036                                         groups = "uart1_grp";
1037                                         function = "uart1";
1038                                 };
1039                         };
1040
1041                         uart2_pmx: uart2@0 {
1042                                 uart2 {
1043                                         groups = "uart2_grp";
1044                                         function = "uart2";
1045                                 };
1046                         };
1047
1048                         uart3_pmx0: uart3@0 {
1049                                 uart3_0 {
1050                                         groups = "uart3_grp0";
1051                                         function = "uart3_m0";
1052                                 };
1053                         };
1054
1055                         uart3_pmx1: uart3@1 {
1056                                 uart3_1 {
1057                                         groups = "uart3_grp1";
1058                                         function = "uart3_m1";
1059                                 };
1060                         };
1061
1062                         uart3_pmx2: uart3@2 {
1063                                 uart3_2 {
1064                                         groups = "uart3_grp2";
1065                                         function = "uart3_m2";
1066                                 };
1067                         };
1068
1069                         uart3_pmx3: uart3@3 {
1070                                 uart3_3 {
1071                                         groups = "uart3_grp3";
1072                                         function = "uart3_m3";
1073                                 };
1074                         };
1075
1076                         uart3_nopause_pmx0: uart3_nopause@0 {
1077                                 uart3_nopause_0 {
1078                                         groups = "uart3_nopause_grp0";
1079                                         function = "uart3_nopause_m0";
1080                                 };
1081                         };
1082
1083                         uart3_nopause_pmx1: uart3_nopause@1 {
1084                                 uart3_nopause_1 {
1085                                         groups = "uart3_nopause_grp1";
1086                                         function = "uart3_nopause_m1";
1087                                 };
1088                         };
1089
1090                         uart4_pmx0: uart4@0 {
1091                                 uart4_0 {
1092                                         groups = "uart4_grp0";
1093                                         function = "uart4_m0";
1094                                 };
1095                         };
1096
1097                         uart4_pmx1: uart4@1 {
1098                                 uart4_1 {
1099                                         groups = "uart4_grp1";
1100                                         function = "uart4_m1";
1101                                 };
1102                         };
1103
1104                         uart4_pmx2: uart4@2 {
1105                                 uart4_2 {
1106                                         groups = "uart4_grp2";
1107                                         function = "uart4_m2";
1108                                 };
1109                         };
1110
1111                         uart4_nopause_pmx: uart4_nopause@0 {
1112                                 uart4_nopause {
1113                                         groups = "uart4_nopause_grp";
1114                                         function = "uart4_nopause";
1115                                 };
1116                         };
1117
1118                         usb0_drvvbus_pmx: usb0_drvvbus@0 {
1119                                 usb0_drvvbus {
1120                                         groups = "usb0_drvvbus_grp";
1121                                         function = "usb0_drvvbus";
1122                                 };
1123                         };
1124
1125                         usb1_drvvbus_pmx: usb1_drvvbus@0 {
1126                                 usb1_drvvbus {
1127                                         groups = "usb1_drvvbus_grp";
1128                                         function = "usb1_drvvbus";
1129                                 };
1130                         };
1131
1132                         visbus_dout_pmx: visbus_dout@0 {
1133                                 visbus_dout {
1134                                         groups = "visbus_dout_grp";
1135                                         function = "visbus_dout";
1136                                 };
1137                         };
1138
1139                         vi_vip1_pmx: vi_vip1@0 {
1140                                 vi_vip1 {
1141                                         groups = "vi_vip1_grp";
1142                                         function = "vi_vip1";
1143                                 };
1144                         };
1145
1146                         vi_vip1_ext_pmx: vi_vip1_ext@0 {
1147                                 vi_vip1_ext {
1148                                         groups = "vi_vip1_ext_grp";
1149                                         function = "vi_vip1_ext";
1150                                 };
1151                         };
1152
1153                         vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 {
1154                                 vi_vip1_low8bit {
1155                                         groups = "vi_vip1_low8bit_grp";
1156                                         function = "vi_vip1_low8bit";
1157                                 };
1158                         };
1159
1160                         vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 {
1161                                 vi_vip1_high8bit {
1162                                         groups = "vi_vip1_high8bit_grp";
1163                                         function = "vi_vip1_high8bit";
1164                                 };
1165                         };
1166                 };
1167
1168                 pmipc {
1169                         compatible = "arteris, flexnoc", "simple-bus";
1170                         #address-cells = <1>;
1171                         #size-cells = <1>;
1172                         ranges = <0x13240000 0x13240000 0x00010000>;
1173                         pmipc@0x13240000 {
1174                                 compatible = "sirf,atlas7-pmipc";
1175                                 reg = <0x13240000 0x00010000>;
1176                         };
1177                 };
1178
1179                 dramfw {
1180                         compatible = "arteris, flexnoc", "simple-bus";
1181                         #address-cells = <1>;
1182                         #size-cells = <1>;
1183                         ranges = <0x10830000 0x10830000 0x18000>;
1184                         dramfw@10820000 {
1185                                 compatible = "sirf,nocfw-dramfw";
1186                                 reg = <0x10830000 0x18000>;
1187                         };
1188                 };
1189
1190                 spramfw {
1191                         compatible = "arteris, flexnoc", "simple-bus";
1192                         #address-cells = <1>;
1193                         #size-cells = <1>;
1194                         ranges = <0x10250000 0x10250000 0x3000>;
1195                         spramfw@10820000 {
1196                                 compatible = "sirf,nocfw-spramfw";
1197                                 reg = <0x10250000 0x3000>;
1198                         };
1199                 };
1200
1201                 cpum {
1202                         compatible = "arteris, flexnoc", "simple-bus";
1203                         #address-cells = <1>;
1204                         #size-cells = <1>;
1205                         ranges = <0x10200000 0x10200000 0x3000>;
1206                         cpum@10200000 {
1207                                 compatible = "sirf,nocfw-cpum";
1208                                 reg = <0x10200000 0x3000>;
1209                         };
1210                 };
1211
1212                 cgum {
1213                         compatible = "arteris, flexnoc", "simple-bus";
1214                         #address-cells = <1>;
1215                         #size-cells = <1>;
1216                         ranges = <0x18641000 0x18641000 0x3000>,
1217                                          <0x18620000 0x18620000 0x1000>,
1218                                         <0x18630000 0x18630000 0x10000>;
1219
1220                         cgum@18641000 {
1221                                 compatible = "sirf,nocfw-cgum";
1222                                 reg = <0x18641000 0x3000>;
1223                         };
1224
1225                         car: clock-controller@18620000 {
1226                                 compatible = "sirf,atlas7-car";
1227                                 reg = <0x18620000 0x1000>;
1228                                 #clock-cells = <1>;
1229                                 #reset-cells = <1>;
1230                         };
1231                         pwm: pwm@18630000 {
1232                                 compatible = "sirf,prima2-pwm";
1233                                 #pwm-cells = <2>;
1234                                 reg = <0x18630000 0x10000>;
1235                                 clocks = <&car 138>, <&car 139>, <&car 237>,
1236                                         <&car 240>,  <&car 140>, <&car 246>;
1237                                 clock-names = "pwmc", "sigsrc0", "sigsrc1",
1238                                         "sigsrc2", "sigsrc3", "sigsrc4";
1239                         };
1240                 };
1241
1242                 gnssm {
1243                         compatible = "arteris, flexnoc", "simple-bus";
1244                         #address-cells = <1>;
1245                         #size-cells = <1>;
1246                         ranges = <0x18000000 0x18000000 0x0000ffff>,
1247                                 <0x18010000 0x18010000 0x1000>,
1248                                 <0x18020000 0x18020000 0x1000>,
1249                                 <0x18030000 0x18030000 0x1000>,
1250                                 <0x18040000 0x18040000 0x1000>,
1251                                 <0x18050000 0x18050000 0x1000>,
1252                                 <0x18060000 0x18060000 0x1000>,
1253                                 <0x180b0000 0x180b0000 0x4000>,
1254                                 <0x18100000 0x18100000 0x3000>,
1255                                 <0x18250000 0x18250000 0x10000>,
1256                                 <0x18200000 0x18200000 0x1000>;
1257
1258                         dmac0: dma-controller@18000000 {
1259                                 cell-index = <0>;
1260                                 compatible = "sirf,atlas7-dmac";
1261                                 reg = <0x18000000 0x1000>;
1262                                 interrupts = <0 12 0>;
1263                                 clocks = <&car 89>;
1264                                 dma-channels = <16>;
1265                                 #dma-cells = <1>;
1266                         };
1267
1268                         gnssmfw@0x18100000 {
1269                                 compatible = "sirf,nocfw-gnssm";
1270                                 reg = <0x18100000 0x3000>;
1271                         };
1272
1273                         uart0: uart@18010000 {
1274                                 cell-index = <0>;
1275                                 compatible = "sirf,atlas7-uart";
1276                                 reg = <0x18010000 0x1000>;
1277                                 interrupts = <0 17 0>;
1278                                 clocks = <&car 90>;
1279                                 fifosize = <128>;
1280                                 dmas = <&dmac0 3>, <&dmac0 2>;
1281                                 dma-names = "rx", "tx";
1282                         };
1283
1284                         uart1: uart@18020000 {
1285                                 cell-index = <1>;
1286                                 compatible = "sirf,atlas7-uart";
1287                                 reg = <0x18020000 0x1000>;
1288                                 interrupts = <0 18 0>;
1289                                 clocks = <&car 88>;
1290                                 fifosize = <32>;
1291                         };
1292
1293                         uart2: uart@18030000 {
1294                                 cell-index = <2>;
1295                                 compatible = "sirf,atlas7-uart";
1296                                 reg = <0x18030000 0x1000>;
1297                                 interrupts = <0 19 0>;
1298                                 clocks = <&car 91>;
1299                                 fifosize = <128>;
1300                                 dmas = <&dmac0 6>, <&dmac0 7>;
1301                                 dma-names = "rx", "tx";
1302                                 status = "disabled";
1303                         };
1304                         uart3: uart@18040000 {
1305                                 cell-index = <3>;
1306                                 compatible = "sirf,atlas7-uart";
1307                                 reg = <0x18040000 0x1000>;
1308                                 interrupts = <0 66 0>;
1309                                 clocks = <&car 92>;
1310                                 fifosize = <128>;
1311                                 dmas = <&dmac0 4>, <&dmac0 5>;
1312                                 dma-names = "rx", "tx";
1313                                 status = "disabled";
1314                         };
1315                         uart4: uart@18050000 {
1316                                 cell-index = <4>;
1317                                 compatible = "sirf,atlas7-uart";
1318                                 reg = <0x18050000 0x1000>;
1319                                 interrupts = <0 69 0>;
1320                                 clocks = <&car 93>;
1321                                 fifosize = <128>;
1322                                 dmas = <&dmac0 0>, <&dmac0 1>;
1323                                 dma-names = "rx", "tx";
1324                                 status = "disabled";
1325                         };
1326                         uart5: uart@18060000 {
1327                                 cell-index = <5>;
1328                                 compatible = "sirf,atlas7-uart";
1329                                 reg = <0x18060000 0x1000>;
1330                                 interrupts = <0 71 0>;
1331                                 clocks = <&car 94>;
1332                                 fifosize = <128>;
1333                                 dmas = <&dmac0 8>, <&dmac0 9>;
1334                                 dma-names = "rx", "tx";
1335                                 status = "disabled";
1336                         };
1337                         gmac: eth@180b0000 {
1338                                 compatible = "snps, dwc-eth-qos";
1339                                 reg = <0x180b0000 0x4000>;
1340                                 interrupts = <0 59 0>, <0 70 0>;
1341                                 interrupt-names = "macirq", "macpmt";
1342                                 clocks = <&car 39>, <&car 45>,
1343                                        <&car 86>, <&car 87>;
1344                                 clock-names = "gnssm_rgmii", "gnssm_gmac",
1345                                         "rgmii", "gmac";
1346                                 local-mac-address = [00 00 00 00 00 00];
1347                                 phy-mode = "rgmii";
1348                         };
1349                         dspub@18250000 {
1350                                 compatible = "dx,cc44p";
1351                                 reg = <0x18250000 0x10000>;
1352                                 interrupts = <0 27 0>;
1353                         };
1354
1355                         spi1: spi@18200000 {
1356                                 compatible = "sirf,prima2-spi";
1357                                 reg = <0x18200000 0x1000>;
1358                                 interrupts = <0 16 0>;
1359                                 clocks = <&car 95>;
1360                                 #address-cells = <1>;
1361                                 #size-cells = <0>;
1362                                 dmas = <&dmac0 12>, <&dmac0 13>;
1363                                 dma-names = "rx", "tx";
1364                                 status = "disabled";
1365                         };
1366                 };
1367
1368
1369                 gpum {
1370                         compatible = "arteris, flexnoc", "simple-bus";
1371                         #address-cells = <1>;
1372                         #size-cells = <1>;
1373                         ranges = <0x13000000 0x13000000 0x3000>,
1374                                 <0x13010000 0x13010000 0x1400>,
1375                                 <0x13010800 0x13010800 0x100>,
1376                                 <0x13011000 0x13011000 0x100>;
1377                         gpum@0x13000000 {
1378                                 compatible = "sirf,nocfw-gpum";
1379                                 reg = <0x13000000 0x3000>;
1380                         };
1381                         dmacsdrr: dma-controller@13010800 {
1382                                 cell-index = <5>;
1383                                 compatible = "sirf,atlas7-dmac-v2";
1384                                 reg = <0x13010800 0x100>;
1385                                 interrupts = <0 8 0>;
1386                                 clocks = <&car 127>;
1387                                 #dma-cells = <1>;
1388                                 #dma-channels = <1>;
1389                         };
1390                         dmacsdrw: dma-controller@13011000 {
1391                                 cell-index = <6>;
1392                                 compatible = "sirf,atlas7-dmac-v2";
1393                                 reg = <0x13011000 0x100>;
1394                                 interrupts = <0 9 0>;
1395                                 clocks = <&car 127>;
1396                                 #dma-cells = <1>;
1397                                 #dma-channels = <1>;
1398                         };
1399                         sdr@0x13010000 {
1400                                 compatible = "sirf,atlas7-sdr";
1401                                 reg = <0x13010000 0x1400>;
1402                                 interrupts = <0 7 0>,
1403                                            <0 8 0>,
1404                                            <0 9 0>;
1405                                 clocks = <&car 127>;
1406                                 dmas = <&dmacsdrr 0>, <&dmacsdrw 0>;
1407                                 dma-names = "tx", "rx";
1408                         };
1409                 };
1410
1411                 mediam {
1412                         compatible = "arteris, flexnoc", "simple-bus";
1413                         #address-cells = <1>;
1414                         #size-cells = <1>;
1415                         ranges = <0x15000000 0x15000000 0x00600000>,
1416                                 <0x16000000 0x16000000 0x00200000>,
1417                                 <0x17000000 0x17000000 0x10000>,
1418                                 <0x17020000 0x17020000 0x1000>,
1419                                 <0x17030000 0x17030000 0x1000>,
1420                                 <0x17040000 0x17040000 0x1000>,
1421                                 <0x17050000 0x17050000 0x10000>,
1422                                 <0x17060000 0x17060000 0x200>,
1423                                 <0x17060200 0x17060200 0x100>,
1424                                 <0x17070000 0x17070000 0x200>,
1425                                 <0x17070200 0x17070200 0x100>,
1426                                 <0x170A0000 0x170A0000 0x3000>;
1427
1428                         multimedia@15000000 {
1429                                 compatible = "sirf,atlas7-video-codec";
1430                                 reg = <0x15000000 0x10000>;
1431                                 interrupts = <0 5 0>;
1432                                 clocks = <&car 102>;
1433                         };
1434
1435                         mediam@170A0000 {
1436                                 compatible = "sirf,nocfw-mediam";
1437                                 reg = <0x170A0000 0x3000>;
1438                         };
1439
1440                         gpio_0: gpio_mediam@17040000 {
1441                                 #gpio-cells = <2>;
1442                                 #interrupt-cells = <2>;
1443                                 compatible = "sirf,atlas7-gpio";
1444                                 reg = <0x17040000 0x1000>;
1445                                 interrupts = <0 13 0>, <0 14 0>;
1446                                 clocks = <&car 107>;
1447                                 clock-names = "gpio0_io";
1448                                 gpio-controller;
1449                                 interrupt-controller;
1450
1451                                 gpio-banks = <2>;
1452                                 gpio-ranges = <&pinctrl 0 0 0>,
1453                                                 <&pinctrl 32 0 0>;
1454                                 gpio-ranges-group-names = "lvds_gpio_grp",
1455                                                         "uart_nand_gpio_grp";
1456                         };
1457
1458                         nand@17050000 {
1459                                 compatible = "sirf,atlas7-nand";
1460                                 reg = <0x17050000 0x10000>;
1461                                 pinctrl-names = "default";
1462                                 pinctrl-0 = <&nd_df_pmx>;
1463                                 interrupts = <0 41 0>;
1464                                 clocks = <&car 108>, <&car 112>;
1465                                 clock-names = "nand_io", "nand_nand";
1466                         };
1467
1468                         sd0: sdhci@16000000 {
1469                                 cell-index = <0>;
1470                                 compatible = "sirf,atlas7-sdhc";
1471                                 reg = <0x16000000 0x100000>;
1472                                 interrupts = <0 38 0>;
1473                                 clocks = <&car 109>, <&car 111>;
1474                                 clock-names = "core", "iface";
1475                                 wp-inverted;
1476                                 non-removable;
1477                                 status = "disabled";
1478                                 bus-width = <8>;
1479                         };
1480
1481                         sd1: sdhci@16100000 {
1482                                 cell-index = <1>;
1483                                 compatible = "sirf,atlas7-sdhc";
1484                                 reg = <0x16100000 0x100000>;
1485                                 interrupts = <0 38 0>;
1486                                 clocks = <&car 109>, <&car 111>;
1487                                 clock-names = "core", "iface";
1488                                 non-removable;
1489                                 status = "disabled";
1490                                 bus-width = <8>;
1491                         };
1492
1493                         jpeg@17000000 {
1494                                 compatible = "sirf,atlas7-jpeg";
1495                                 reg = <0x17000000 0x10000>;
1496                                 interrupts = <0 72 0>,
1497                                         <0 73 0>;
1498                                 clocks = <&car 103>;
1499                         };
1500
1501                         usb0: usb@17060000 {
1502                                 cell-index = <0>;
1503                                 compatible = "sirf,atlas7-usb";
1504                                 reg = <0x17060000 0x200>;
1505                                 interrupts = <0 10 0>;
1506                                 clocks = <&car 113>;
1507                                 sirf,usbphy = <&usbphy0>;
1508                                 phy_type = "utmi";
1509                                 dr_mode = "otg";
1510                                 maximum-speed = "high-speed";
1511                                 status = "okay";
1512                         };
1513
1514                         usb1: usb@17070000 {
1515                                 cell-index = <1>;
1516                                 compatible = "sirf,atlas7-usb";
1517                                 reg = <0x17070000 0x200>;
1518                                 interrupts = <0 11 0>;
1519                                 clocks = <&car 114>;
1520                                 sirf,usbphy = <&usbphy1>;
1521                                 phy_type = "utmi";
1522                                 dr_mode = "host";
1523                                 maximum-speed = "high-speed";
1524                                 status = "okay";
1525                         };
1526
1527                         usbphy0: usbphy@0 {
1528                                 compatible = "sirf,atlas7-usbphy";
1529                                 reg = <0x17060200 0x100>;
1530                                 clocks = <&car 115>;
1531                                 status = "okay";
1532                         };
1533
1534                         usbphy1: usbphy@1 {
1535                                 compatible = "sirf,atlas7-usbphy";
1536                                 reg = <0x17070200 0x100>;
1537                                 clocks = <&car 116>;
1538                                 status = "okay";
1539                         };
1540
1541                         i2c0: i2c@17020000 {
1542                                 cell-index = <0>;
1543                                 compatible = "sirf,prima2-i2c";
1544                                 reg = <0x17020000 0x1000>;
1545                                 interrupts = <0 24 0>;
1546                                 clocks = <&car 105>;
1547                                 #address-cells = <1>;
1548                                 #size-cells = <0>;
1549                         };
1550
1551                 };
1552
1553                 vdifm {
1554                         compatible = "arteris, flexnoc", "simple-bus";
1555                         #address-cells = <1>;
1556                         #size-cells = <1>;
1557                         ranges = <0x13290000 0x13290000 0x3000>,
1558                                 <0x13300000 0x13300000 0x1000>,
1559                                 <0x14200000 0x14200000 0x600000>;
1560
1561                         vdifm@13290000 {
1562                                 compatible = "sirf,nocfw-vdifm";
1563                                 reg = <0x13290000 0x3000>;
1564                         };
1565
1566                         gpio_1: gpio_vdifm@13300000 {
1567                                 #gpio-cells = <2>;
1568                                 #interrupt-cells = <2>;
1569                                 compatible = "sirf,atlas7-gpio";
1570                                 reg = <0x13300000 0x1000>;
1571                                 interrupts = <0 43 0>, <0 44 0>,
1572                                                 <0 45 0>, <0 46 0>;
1573                                 clocks = <&car 84>;
1574                                 clock-names = "gpio1_io";
1575                                 gpio-controller;
1576                                 interrupt-controller;
1577
1578                                 gpio-banks = <4>;
1579                                 gpio-ranges = <&pinctrl 0 0 0>,
1580                                                 <&pinctrl 32 0 0>,
1581                                                 <&pinctrl 64 0 0>,
1582                                                 <&pinctrl 96 0 0>;
1583                                 gpio-ranges-group-names = "gnss_gpio_grp",
1584                                                         "lcd_vip_gpio_grp",
1585                                                         "sdio_i2s_gpio_grp",
1586                                                         "sp_rgmii_gpio_grp";
1587                         };
1588
1589                         sd2: sdhci@14200000 {
1590                                 cell-index = <2>;
1591                                 compatible = "sirf,atlas7-sdhc";
1592                                 reg = <0x14200000 0x100000>;
1593                                 interrupts = <0 23 0>;
1594                                 clocks = <&car 70>, <&car 75>;
1595                                 clock-names = "core", "iface";
1596                                 status = "disabled";
1597                                 bus-width = <4>;
1598                                 sd-uhs-sdr50;
1599                                 vqmmc-supply = <&vqmmc>;
1600                                 vqmmc: vqmmc@2 {
1601                                         regulator-min-microvolt = <1650000>;
1602                                         regulator-max-microvolt = <1950000>;
1603                                         regulator-name = "vqmmc-ldo";
1604                                         regulator-type = "voltage";
1605                                         regulator-boot-on;
1606                                         regulator-allow-bypass;
1607                                 };
1608                         };
1609
1610                         sd3: sdhci@14300000 {
1611                                 cell-index = <3>;
1612                                 compatible = "sirf,atlas7-sdhc";
1613                                 reg = <0x14300000 0x100000>;
1614                                 interrupts = <0 23 0>;
1615                                 clocks = <&car 76>, <&car 81>;
1616                                 clock-names = "core", "iface";
1617                                 status = "disabled";
1618                                 bus-width = <4>;
1619                         };
1620
1621                         sd5: sdhci@14500000 {
1622                                 cell-index = <5>;
1623                                 compatible = "sirf,atlas7-sdhc";
1624                                 reg = <0x14500000 0x100000>;
1625                                 interrupts = <0 39 0>;
1626                                 clocks = <&car 71>, <&car 76>;
1627                                 clock-names = "core", "iface";
1628                                 status = "disabled";
1629                                 bus-width = <4>;
1630                                 loop-dma;
1631                         };
1632
1633                         sd6: sdhci@14600000 {
1634                                 cell-index = <6>;
1635                                 compatible = "sirf,atlas7-sdhc";
1636                                 reg = <0x14600000 0x100000>;
1637                                 interrupts = <0 98 0>;
1638                                 clocks = <&car 72>, <&car 77>;
1639                                 clock-names = "core", "iface";
1640                                 status = "disabled";
1641                                 bus-width = <4>;
1642                         };
1643
1644                         sd7: sdhci@14700000 {
1645                                 cell-index = <7>;
1646                                 compatible = "sirf,atlas7-sdhc";
1647                                 reg = <0x14700000 0x100000>;
1648                                 interrupts = <0 98 0>;
1649                                 clocks = <&car 72>, <&car 77>;
1650                                 clock-names = "core", "iface";
1651                                 status = "disabled";
1652                                 bus-width = <4>;
1653                         };
1654                 };
1655
1656                 audiom {
1657                         compatible = "arteris, flexnoc", "simple-bus";
1658                         #address-cells = <1>;
1659                         #size-cells = <1>;
1660                         ranges = <0x10d50000 0x10d50000 0x0000ffff>,
1661                                         <0x10d60000 0x10d60000 0x0000ffff>,
1662                                         <0x10d80000 0x10d80000 0x0000ffff>,
1663                                         <0x10d90000 0x10d90000 0x0000ffff>,
1664                                         <0x10ED0000 0x10ED0000 0x3000>,
1665                                         <0x10dc8000 0x10dc8000 0x1000>,
1666                                         <0x10dc0000 0x10dc0000 0x1000>,
1667                                         <0x10db0000 0x10db0000 0x4000>,
1668                                         <0x10d40000 0x10d40000 0x1000>,
1669                                         <0x10d30000 0x10d30000 0x1000>;
1670
1671                         timer@10dc0000 {
1672                                 compatible = "sirf,atlas7-tick";
1673                                 reg = <0x10dc0000 0x1000>;
1674                                 interrupts = <0 0 0>,
1675                                            <0 1 0>,
1676                                            <0 2 0>,
1677                                            <0 49 0>,
1678                                            <0 50 0>,
1679                                            <0 51 0>;
1680                                 clocks = <&car 47>;
1681                         };
1682
1683                         timerb@10dc8000 {
1684                                         compatible = "sirf,atlas7-tick";
1685                                         reg = <0x10dc8000 0x1000>;
1686                                         interrupts = <0 74 0>,
1687                                                            <0 75 0>,
1688                                                            <0 76 0>,
1689                                                            <0 77 0>,
1690                                                            <0 78 0>,
1691                                                            <0 79 0>;
1692                                         clocks = <&car 47>;
1693                         };
1694
1695                         vip0@10db0000 {
1696                                 compatible = "sirf,atlas7-vip0";
1697                                 reg = <0x10db0000 0x2000>;
1698                                 interrupts = <0 85 0>;
1699                                 sirf,vip_cma_size = <0xC00000>;
1700                         };
1701
1702                         cvd@10db2000 {
1703                                 compatible = "sirf,cvd";
1704                                 reg = <0x10db2000 0x2000>;
1705                                 clocks = <&car 46>;
1706                         };
1707
1708                         dmac2: dma-controller@10d50000 {
1709                                 cell-index = <2>;
1710                                 compatible = "sirf,atlas7-dmac";
1711                                 reg = <0x10d50000 0xffff>;
1712                                 interrupts = <0 55 0>;
1713                                 clocks = <&car 60>;
1714                                 dma-channels = <16>;
1715                                 #dma-cells = <1>;
1716                         };
1717
1718                         dmac3: dma-controller@10d60000 {
1719                                 cell-index = <3>;
1720                                 compatible = "sirf,atlas7-dmac";
1721                                 reg = <0x10d60000 0xffff>;
1722                                 interrupts = <0 56 0>;
1723                                 clocks = <&car 61>;
1724                                 dma-channels = <16>;
1725                                 #dma-cells = <1>;
1726                         };
1727
1728                         adc: adc@10d80000 {
1729                                 compatible = "sirf,atlas7-adc";
1730                                 reg = <0x10d80000 0xffff>;
1731                                 interrupts = <0 34 0>;
1732                                 clocks = <&car 49>;
1733                                 #io-channel-cells = <1>;
1734                         };
1735
1736                         pulsec@10d90000 {
1737                                 compatible = "sirf,prima2-pulsec";
1738                                 reg = <0x10d90000 0xffff>;
1739                                 interrupts = <0 42 0>;
1740                                 clocks = <&car 54>;
1741                         };
1742
1743                         audiom@10ED0000 {
1744                                 compatible = "sirf,nocfw-audiom";
1745                                 reg = <0x10ED0000 0x3000>;
1746                                 interrupts = <0 102 0>;
1747                         };
1748
1749                         usp1: usp@10d30000 {
1750                                 cell-index = <1>;
1751                                 reg = <0x10d30000 0x1000>;
1752                                 fifosize = <512>;
1753                                 clocks = <&car 58>;
1754                                 dmas = <&dmac2 6>, <&dmac2 7>;
1755                                 dma-names = "rx", "tx";
1756                         };
1757
1758                         usp2: usp@10d40000 {
1759                                 cell-index = <2>;
1760                                 reg = <0x10d40000 0x1000>;
1761                                 interrupts = <0 22 0>;
1762                                 clocks = <&car 59>;
1763                                 dmas = <&dmac2 12>, <&dmac2 13>;
1764                                 dma-names = "rx", "tx";
1765                                 #address-cells = <1>;
1766                                 #size-cells = <0>;
1767                                 status = "disabled";
1768                         };
1769                 };
1770
1771                 ddrm {
1772                         compatible = "arteris, flexnoc", "simple-bus";
1773                         #address-cells = <1>;
1774                         #size-cells = <1>;
1775                         ranges = <0x10820000 0x10820000 0x3000>,
1776                                         <0x10800000 0x10800000 0x2000>;
1777                         ddrm@10820000 {
1778                                 compatible = "sirf,nocfw-ddrm";
1779                                 reg = <0x10820000 0x3000>;
1780                                 interrupts = <0 105 0>;
1781                         };
1782
1783                         memory-controller@0x10800000 {
1784                                 compatible = "sirf,atlas7-memc";
1785                                 reg = <0x10800000 0x2000>;
1786                         };
1787
1788                 };
1789
1790                 btm {
1791                         compatible = "arteris, flexnoc", "simple-bus";
1792                         #address-cells = <1>;
1793                         #size-cells = <1>;
1794                         ranges = <0x11002000 0x11002000 0x0000ffff>,
1795                                <0x11010000 0x11010000 0x3000>,
1796                                <0x11000000 0x11000000 0x1000>,
1797                                <0x11001000 0x11001000 0x1000>;
1798
1799                         dmac4: dma-controller@11002000 {
1800                                 cell-index = <4>;
1801                                 compatible = "sirf,atlas7-dmac";
1802                                 reg = <0x11002000 0x1000>;
1803                                 interrupts = <0 99 0>;
1804                                 clocks = <&car 130>;
1805                                 dma-channels = <16>;
1806                                 #dma-cells = <1>;
1807                         };
1808                         uart6: uart@11000000 {
1809                                 cell-index = <6>;
1810                                 compatible = "sirf,atlas7-bt-uart",
1811                                                 "sirf,atlas7-uart";
1812                                 reg = <0x11000000 0x1000>;
1813                                 interrupts = <0 100 0>;
1814                                 clocks = <&car 131>, <&car 133>, <&car 134>;
1815                                 clock-names = "uart", "general", "noc";
1816                                 fifosize = <128>;
1817                                 dmas = <&dmac4 12>, <&dmac4 13>;
1818                                 dma-names = "rx", "tx";
1819                                 status = "disabled";
1820                         };
1821
1822                         usp3: usp@11001000 {
1823                                 compatible = "sirf,atlas7-bt-usp",
1824                                            "sirf,prima2-usp-pcm";
1825                                 cell-index = <3>;
1826                                 reg = <0x11001000 0x1000>;
1827                                 fifosize = <512>;
1828                                 clocks = <&car 132>, <&car 129>, <&car 133>,
1829                                         <&car 134>, <&car 135>;
1830                                 clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
1831                                         "noc_btm_io", "thbtm_io";
1832                                 dmas = <&dmac4 0>, <&dmac4 1>;
1833                                 dma-names = "rx", "tx";
1834                         };
1835
1836                         btm@11010000 {
1837                                 compatible = "sirf,nocfw-btm";
1838                                 reg = <0x11010000 0x3000>;
1839                         };
1840                 };
1841
1842                 rtcm {
1843                         compatible = "arteris, flexnoc", "simple-bus";
1844                         #address-cells = <1>;
1845                         #size-cells = <1>;
1846                         ranges = <0x18810000 0x18810000 0x3000>,
1847                                 <0x18840000 0x18840000 0x1000>,
1848                                 <0x18890000 0x18890000 0x1000>,
1849                                 <0x188B0000 0x188B0000 0x10000>,
1850                                 <0x188D0000 0x188D0000 0x1000>;
1851                         rtcm@18810000 {
1852                                 compatible = "sirf,nocfw-rtcm";
1853                                 reg = <0x18810000 0x3000>;
1854                                 interrupts = <0 109 0>;
1855                         };
1856
1857                         gpio_2: gpio_rtcm@18890000 {
1858                                 #gpio-cells = <2>;
1859                                 #interrupt-cells = <2>;
1860                                 compatible = "sirf,atlas7-gpio";
1861                                 reg = <0x18890000 0x1000>;
1862                                 interrupts = <0 47 0>;
1863                                 gpio-controller;
1864                                 interrupt-controller;
1865
1866                                 gpio-banks = <1>;
1867                                 gpio-ranges = <&pinctrl 0 0 0>;
1868                                 gpio-ranges-group-names = "rtc_gpio_grp";
1869                         };
1870
1871                         rtc-iobg@18840000 {
1872                                 compatible = "sirf,prima2-rtciobg",
1873                                         "sirf-prima2-rtciobg-bus",
1874                                         "simple-bus";
1875                                 #address-cells = <1>;
1876                                 #size-cells = <1>;
1877                                 reg = <0x18840000 0x1000>;
1878
1879                                 sysrtc@2000 {
1880                                         compatible = "sirf,prima2-sysrtc";
1881                                         reg = <0x2000 0x100>;
1882                                         interrupts = <0 52 0>;
1883                                 };
1884                                 pwrc@3000 {
1885                                         compatible = "sirf,atlas7-pwrc";
1886                                         reg = <0x3000 0x100>;
1887                                 };
1888                         };
1889
1890                         qspi: flash@188B0000 {
1891                                 cell-index = <0>;
1892                                 compatible = "sirf,atlas7-qspi-nor";
1893                                 reg = <0x188B0000 0x10000>;
1894                                 interrupts = <0 15 0>;
1895                                 #address-cells = <1>;
1896                                 #size-cells = <0>;
1897                         };
1898
1899                         retain@0x188D0000 {
1900                                 compatible = "sirf,atlas7-retain";
1901                                 reg = <0x188D0000 0x1000>;
1902                         };
1903
1904                 };
1905                 disp-iobg {
1906                         /* lcdc0 */
1907                         compatible = "simple-bus";
1908                         #address-cells = <1>;
1909                         #size-cells = <1>;
1910                         ranges = <0x13100000 0x13100000 0x20000>,
1911                                 <0x10e10000 0x10e10000 0x10000>,
1912                                 <0x17010000 0x17010000 0x10000>;
1913
1914                         lcd@13100000 {
1915                                 compatible = "sirf,atlas7-lcdc";
1916                                 reg = <0x13100000 0x10000>;
1917                                 interrupts = <0 30 0>;
1918                                 clocks = <&car 79>;
1919                         };
1920                         vpp@13110000 {
1921                                 compatible = "sirf,atlas7-vpp";
1922                                 reg = <0x13110000 0x10000>;
1923                                 interrupts = <0 31 0>;
1924                                 clocks = <&car 78>;
1925                                 resets = <&car 29>;
1926                         };
1927                         lvds@10e10000 {
1928                                 compatible = "sirf,atlas7-lvdsc";
1929                                 reg = <0x10e10000 0x10000>;
1930                                 interrupts = <0 64 0>;
1931                                 clocks = <&car 54>;
1932                                 resets = <&car 29>;
1933                         };
1934                         g2d@17010000 {
1935                                 compatible = "sirf, atlas7-g2d";
1936                                 reg = <0x17010000 0x10000>;
1937                                 interrupts = <0 61 0>;
1938                                 clocks = <&car 104>;
1939                         };
1940
1941                 };
1942
1943                 graphics-iobg {
1944                         compatible = "simple-bus";
1945                         #address-cells = <1>;
1946                         #size-cells = <1>;
1947                         ranges = <0x12000000 0x12000000 0x1000000>;
1948
1949                         graphics@12000000 {
1950                                 compatible = "powervr,sgx531";
1951                                 reg = <0x12000000 0x1000000>;
1952                                 interrupts = <0 6 0>;
1953                                 clocks = <&car 126>;
1954                         };
1955                 };
1956         };
1957 };