arch/arm/boot/dts/bcm-nsp.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/interrupt-controller/irq.h>
  35
  36 #include "skeleton.dtsi"
  37
  38 / {
  39         compatible = "brcm,nsp";
  40         model = "Broadcom Northstar Plus SoC";
  41         interrupt-parent = <&gic>;
  42
  43         mpcore {
  44                 compatible = "simple-bus";
  45                 ranges = <0x00000000 0x19020000 0x00003000>;
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48
  49                 cpus {
  50                         #address-cells = <1>;
  51                         #size-cells = <0>;
  52
  53                         cpu@0 {
  54                                 device_type = "cpu";
  55                                 compatible = "arm,cortex-a9";
  56                                 next-level-cache = <&L2>;
  57                                 reg = <0x0>;
  58                         };
  59                 };
  60
  61                 L2: l2-cache {
  62                         compatible = "arm,pl310-cache";
  63                         reg = <0x2000 0x1000>;
  64                         cache-unified;
  65                         cache-level = <2>;
  66                 };
  67
  68                 gic: interrupt-controller@19021000 {
  69                         compatible = "arm,cortex-a9-gic";
  70                         #interrupt-cells = <3>;
  71                         #address-cells = <0>;
  72                         interrupt-controller;
  73                         reg = <0x1000 0x1000>,
  74                               <0x0100 0x100>;
  75                 };
  76
  77                 timer@19020200 {
  78                         compatible = "arm,cortex-a9-global-timer";
  79                         reg = <0x0200 0x100>;
  80                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  81                         clocks = <&periph_clk>;
  82                 };
  83         };
  84
  85         clocks {
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88                 ranges;
  89
  90                 periph_clk: periph_clk {
  91                         compatible = "fixed-clock";
  92                         #clock-cells = <0>;
  93                         clock-frequency = <500000000>;
  94                 };
  95         };
  96
  97         axi {
  98                 compatible = "simple-bus";
  99                 ranges = <0x00000000 0x18000000 0x00001000>;
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102
 103                 uart0: serial@18000300 {
 104                         compatible = "ns16550a";
 105                         reg = <0x0300 0x100>;
 106                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 107                         clock-frequency = <62499840>;
 108                         status = "disabled";
 109                 };
 110
 111                 uart1: serial@18000400 {
 112                         compatible = "ns16550a";
 113                         reg = <0x0400 0x100>;
 114                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 115                         clock-frequency = <62499840>;
 116                         status = "disabled";
 117                 };
 118         };
 119 };