arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "TI DRA742";
  15         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  16
  17         memory {
  18                 device_type = "memory";
  19                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  20         };
  21
  22         evm_3v3_sd: fixedregulator-sd {
  23                 compatible = "regulator-fixed";
  24                 regulator-name = "evm_3v3_sd";
  25                 regulator-min-microvolt = <3300000>;
  26                 regulator-max-microvolt = <3300000>;
  27                 enable-active-high;
  28                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  29         };
  30
  31         mmc2_3v3: fixedregulator-mmc2 {
  32                 compatible = "regulator-fixed";
  33                 regulator-name = "mmc2_3v3";
  34                 regulator-min-microvolt = <3300000>;
  35                 regulator-max-microvolt = <3300000>;
  36         };
  37
  38         extcon_usb1: extcon_usb1 {
  39                 compatible = "linux,extcon-usb-gpio";
  40                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  41         };
  42
  43         extcon_usb2: extcon_usb2 {
  44                 compatible = "linux,extcon-usb-gpio";
  45                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  46         };
  47
  48         vtt_fixed: fixedregulator-vtt {
  49                 compatible = "regulator-fixed";
  50                 regulator-name = "vtt_fixed";
  51                 regulator-min-microvolt = <1350000>;
  52                 regulator-max-microvolt = <1350000>;
  53                 regulator-always-on;
  54                 regulator-boot-on;
  55                 enable-active-high;
  56                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  57         };
  58 };
  59
  60 &dra7_pmx_core {
  61         pinctrl-names = "default";
  62         pinctrl-0 = <&vtt_pin>;
  63
  64         vtt_pin: pinmux_vtt_pin {
  65                 pinctrl-single,pins = <
  66                         0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
  67                 >;
  68         };
  69
  70         i2c1_pins: pinmux_i2c1_pins {
  71                 pinctrl-single,pins = <
  72                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
  73                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
  74                 >;
  75         };
  76
  77         i2c2_pins: pinmux_i2c2_pins {
  78                 pinctrl-single,pins = <
  79                         0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
  80                         0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
  81                 >;
  82         };
  83
  84         i2c3_pins: pinmux_i2c3_pins {
  85                 pinctrl-single,pins = <
  86                         0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
  87                         0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
  88                 >;
  89         };
  90
  91         mcspi1_pins: pinmux_mcspi1_pins {
  92                 pinctrl-single,pins = <
  93                         0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
  94                         0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
  95                         0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
  96                         0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
  97                         0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
  98                         0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
  99                 >;
 100         };
 101
 102         mcspi2_pins: pinmux_mcspi2_pins {
 103                 pinctrl-single,pins = <
 104                         0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
 105                         0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 106                         0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 107                         0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
 108                 >;
 109         };
 110
 111         uart1_pins: pinmux_uart1_pins {
 112                 pinctrl-single,pins = <
 113                         0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
 114                         0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
 115                         0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
 116                         0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
 117                 >;
 118         };
 119
 120         uart2_pins: pinmux_uart2_pins {
 121                 pinctrl-single,pins = <
 122                         0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
 123                         0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
 124                         0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
 125                         0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
 126                 >;
 127         };
 128
 129         uart3_pins: pinmux_uart3_pins {
 130                 pinctrl-single,pins = <
 131                         0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
 132                         0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 133                 >;
 134         };
 135
 136         qspi1_pins: pinmux_qspi1_pins {
 137                 pinctrl-single,pins = <
 138                         0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
 139                         0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
 140                         0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
 141                         0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
 142                         0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
 143                         0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
 144                         0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
 145                         0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
 146                         0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
 147                         0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
 148                 >;
 149         };
 150
 151         usb1_pins: pinmux_usb1_pins {
 152                 pinctrl-single,pins = <
 153                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 154                 >;
 155         };
 156
 157         usb2_pins: pinmux_usb2_pins {
 158                 pinctrl-single,pins = <
 159                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 160                 >;
 161         };
 162
 163         nand_flash_x16: nand_flash_x16 {
 164                 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 165                  * So NAND flash requires following switch settings:
 166                  * SW5.9 (GPMC_WPN) = LOW
 167                  * SW5.1 (NAND_BOOTn) = HIGH */
 168                 pinctrl-single,pins = <
 169                         0x0     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad0     */
 170                         0x4     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad1     */
 171                         0x8     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad2     */
 172                         0xc     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad3     */
 173                         0x10    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad4     */
 174                         0x14    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad5     */
 175                         0x18    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad6     */
 176                         0x1c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad7     */
 177                         0x20    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad8     */
 178                         0x24    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad9     */
 179                         0x28    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad10    */
 180                         0x2c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad11    */
 181                         0x30    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad12    */
 182                         0x34    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad13    */
 183                         0x38    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad14    */
 184                         0x3c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad15    */
 185                         0xd8    (PIN_INPUT_PULLUP  | MUX_MODE0) /* gpmc_wait0   */
 186                         0xcc    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_wen     */
 187                         0xb4    (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0    */
 188                         0xc4    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_advn_ale */
 189                         0xc8    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_oen_ren  */
 190                         0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
 191                 >;
 192         };
 193
 194         cpsw_default: cpsw_default {
 195                 pinctrl-single,pins = <
 196                         /* Slave 1 */
 197                         0x250 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txc.rgmii0_txc */
 198                         0x254 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txctl.rgmii0_txctl */
 199                         0x258 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_td3.rgmii0_txd3 */
 200                         0x25c (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd2.rgmii0_txd2 */
 201                         0x260 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd1.rgmii0_txd1 */
 202                         0x264 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd0.rgmii0_txd0 */
 203                         0x268 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxc.rgmii0_rxc */
 204                         0x26c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxctl.rgmii0_rxctl */
 205                         0x270 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd3.rgmii0_rxd3 */
 206                         0x274 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd2.rgmii0_rxd2 */
 207                         0x278 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd1.rgmii0_rxd1 */
 208                         0x27c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd0.rgmii0_rxd0 */
 209
 210                         /* Slave 2 */
 211                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 212                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 213                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 214                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 215                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 216                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 217                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 218                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 219                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 220                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 221                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 222                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 223                 >;
 224
 225         };
 226
 227         cpsw_sleep: cpsw_sleep {
 228                 pinctrl-single,pins = <
 229                         /* Slave 1 */
 230                         0x250 (MUX_MODE15)
 231                         0x254 (MUX_MODE15)
 232                         0x258 (MUX_MODE15)
 233                         0x25c (MUX_MODE15)
 234                         0x260 (MUX_MODE15)
 235                         0x264 (MUX_MODE15)
 236                         0x268 (MUX_MODE15)
 237                         0x26c (MUX_MODE15)
 238                         0x270 (MUX_MODE15)
 239                         0x274 (MUX_MODE15)
 240                         0x278 (MUX_MODE15)
 241                         0x27c (MUX_MODE15)
 242
 243                         /* Slave 2 */
 244                         0x198 (MUX_MODE15)
 245                         0x19c (MUX_MODE15)
 246                         0x1a0 (MUX_MODE15)
 247                         0x1a4 (MUX_MODE15)
 248                         0x1a8 (MUX_MODE15)
 249                         0x1ac (MUX_MODE15)
 250                         0x1b0 (MUX_MODE15)
 251                         0x1b4 (MUX_MODE15)
 252                         0x1b8 (MUX_MODE15)
 253                         0x1bc (MUX_MODE15)
 254                         0x1c0 (MUX_MODE15)
 255                         0x1c4 (MUX_MODE15)
 256                 >;
 257         };
 258
 259         davinci_mdio_default: davinci_mdio_default {
 260                 pinctrl-single,pins = <
 261                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 262                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 263                 >;
 264         };
 265
 266         davinci_mdio_sleep: davinci_mdio_sleep {
 267                 pinctrl-single,pins = <
 268                         0x23c (MUX_MODE15)
 269                         0x240 (MUX_MODE15)
 270                 >;
 271         };
 272
 273         dcan1_pins_default: dcan1_pins_default {
 274                 pinctrl-single,pins = <
 275                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 276                         0x418   (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
 277                 >;
 278         };
 279
 280         dcan1_pins_sleep: dcan1_pins_sleep {
 281                 pinctrl-single,pins = <
 282                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 283                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 284                 >;
 285         };
 286 };
 287
 288 &i2c1 {
 289         status = "okay";
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&i2c1_pins>;
 292         clock-frequency = <400000>;
 293
 294         tps659038: tps659038@58 {
 295                 compatible = "ti,tps659038";
 296                 reg = <0x58>;
 297
 298                 tps659038_pmic {
 299                         compatible = "ti,tps659038-pmic";
 300
 301                         regulators {
 302                                 smps123_reg: smps123 {
 303                                         /* VDD_MPU */
 304                                         regulator-name = "smps123";
 305                                         regulator-min-microvolt = < 850000>;
 306                                         regulator-max-microvolt = <1250000>;
 307                                         regulator-always-on;
 308                                         regulator-boot-on;
 309                                 };
 310
 311                                 smps45_reg: smps45 {
 312                                         /* VDD_DSPEVE */
 313                                         regulator-name = "smps45";
 314                                         regulator-min-microvolt = < 850000>;
 315                                         regulator-max-microvolt = <1150000>;
 316                                         regulator-always-on;
 317                                         regulator-boot-on;
 318                                 };
 319
 320                                 smps6_reg: smps6 {
 321                                         /* VDD_GPU - over VDD_SMPS6 */
 322                                         regulator-name = "smps6";
 323                                         regulator-min-microvolt = <850000>;
 324                                         regulator-max-microvolt = <1250000>;
 325                                         regulator-always-on;
 326                                         regulator-boot-on;
 327                                 };
 328
 329                                 smps7_reg: smps7 {
 330                                         /* CORE_VDD */
 331                                         regulator-name = "smps7";
 332                                         regulator-min-microvolt = <850000>;
 333                                         regulator-max-microvolt = <1060000>;
 334                                         regulator-always-on;
 335                                         regulator-boot-on;
 336                                 };
 337
 338                                 smps8_reg: smps8 {
 339                                         /* VDD_IVAHD */
 340                                         regulator-name = "smps8";
 341                                         regulator-min-microvolt = < 850000>;
 342                                         regulator-max-microvolt = <1250000>;
 343                                         regulator-always-on;
 344                                         regulator-boot-on;
 345                                 };
 346
 347                                 smps9_reg: smps9 {
 348                                         /* VDDS1V8 */
 349                                         regulator-name = "smps9";
 350                                         regulator-min-microvolt = <1800000>;
 351                                         regulator-max-microvolt = <1800000>;
 352                                         regulator-always-on;
 353                                         regulator-boot-on;
 354                                 };
 355
 356                                 ldo1_reg: ldo1 {
 357                                         /* LDO1_OUT --> SDIO  */
 358                                         regulator-name = "ldo1";
 359                                         regulator-min-microvolt = <1800000>;
 360                                         regulator-max-microvolt = <3300000>;
 361                                         regulator-always-on;
 362                                         regulator-boot-on;
 363                                 };
 364
 365                                 ldo2_reg: ldo2 {
 366                                         /* VDD_RTCIO */
 367                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 368                                         regulator-name = "ldo2";
 369                                         regulator-min-microvolt = <3300000>;
 370                                         regulator-max-microvolt = <3300000>;
 371                                         regulator-always-on;
 372                                         regulator-boot-on;
 373                                 };
 374
 375                                 ldo3_reg: ldo3 {
 376                                         /* VDDA_1V8_PHY */
 377                                         regulator-name = "ldo3";
 378                                         regulator-min-microvolt = <1800000>;
 379                                         regulator-max-microvolt = <1800000>;
 380                                         regulator-always-on;
 381                                         regulator-boot-on;
 382                                 };
 383
 384                                 ldo9_reg: ldo9 {
 385                                         /* VDD_RTC */
 386                                         regulator-name = "ldo9";
 387                                         regulator-min-microvolt = <1050000>;
 388                                         regulator-max-microvolt = <1050000>;
 389                                         regulator-always-on;
 390                                         regulator-boot-on;
 391                                 };
 392
 393                                 ldoln_reg: ldoln {
 394                                         /* VDDA_1V8_PLL */
 395                                         regulator-name = "ldoln";
 396                                         regulator-min-microvolt = <1800000>;
 397                                         regulator-max-microvolt = <1800000>;
 398                                         regulator-always-on;
 399                                         regulator-boot-on;
 400                                 };
 401
 402                                 ldousb_reg: ldousb {
 403                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 404                                         regulator-name = "ldousb";
 405                                         regulator-min-microvolt = <3300000>;
 406                                         regulator-max-microvolt = <3300000>;
 407                                         regulator-boot-on;
 408                                 };
 409                         };
 410                 };
 411         };
 412
 413         pcf_gpio_21: gpio@21 {
 414                 compatible = "ti,pcf8575";
 415                 reg = <0x21>;
 416                 lines-initial-states = <0x1408>;
 417                 gpio-controller;
 418                 #gpio-cells = <2>;
 419                 interrupt-parent = <&gpio6>;
 420                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 421                 interrupt-controller;
 422                 #interrupt-cells = <2>;
 423         };
 424
 425 };
 426
 427 &i2c2 {
 428         status = "okay";
 429         pinctrl-names = "default";
 430         pinctrl-0 = <&i2c2_pins>;
 431         clock-frequency = <400000>;
 432 };
 433
 434 &i2c3 {
 435         status = "okay";
 436         pinctrl-names = "default";
 437         pinctrl-0 = <&i2c3_pins>;
 438         clock-frequency = <400000>;
 439 };
 440
 441 &mcspi1 {
 442         status = "okay";
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&mcspi1_pins>;
 445 };
 446
 447 &mcspi2 {
 448         status = "okay";
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&mcspi2_pins>;
 451 };
 452
 453 &uart1 {
 454         status = "okay";
 455         pinctrl-names = "default";
 456         pinctrl-0 = <&uart1_pins>;
 457         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 458                               <&dra7_pmx_core 0x3e0>;
 459 };
 460
 461 &uart2 {
 462         status = "okay";
 463         pinctrl-names = "default";
 464         pinctrl-0 = <&uart2_pins>;
 465 };
 466
 467 &uart3 {
 468         status = "okay";
 469         pinctrl-names = "default";
 470         pinctrl-0 = <&uart3_pins>;
 471 };
 472
 473 &mmc1 {
 474         status = "okay";
 475         vmmc-supply = <&evm_3v3_sd>;
 476         vmmc_aux-supply = <&ldo1_reg>;
 477         bus-width = <4>;
 478         /*
 479          * SDCD signal is not being used here - using the fact that GPIO mode
 480          * is always hardwired.
 481          */
 482         cd-gpios = <&gpio6 27 0>;
 483 };
 484
 485 &mmc2 {
 486         status = "okay";
 487         vmmc-supply = <&mmc2_3v3>;
 488         bus-width = <8>;
 489 };
 490
 491 &cpu0 {
 492         cpu0-supply = <&smps123_reg>;
 493 };
 494
 495 &qspi {
 496         status = "okay";
 497         pinctrl-names = "default";
 498         pinctrl-0 = <&qspi1_pins>;
 499
 500         spi-max-frequency = <48000000>;
 501         m25p80@0 {
 502                 compatible = "s25fl256s1";
 503                 spi-max-frequency = <48000000>;
 504                 reg = <0>;
 505                 spi-tx-bus-width = <1>;
 506                 spi-rx-bus-width = <4>;
 507                 spi-cpol;
 508                 spi-cpha;
 509                 #address-cells = <1>;
 510                 #size-cells = <1>;
 511
 512                 /* MTD partition table.
 513                  * The ROM checks the first four physical blocks
 514                  * for a valid file to boot and the flash here is
 515                  * 64KiB block size.
 516                  */
 517                 partition@0 {
 518                         label = "QSPI.SPL";
 519                         reg = <0x00000000 0x000010000>;
 520                 };
 521                 partition@1 {
 522                         label = "QSPI.SPL.backup1";
 523                         reg = <0x00010000 0x00010000>;
 524                 };
 525                 partition@2 {
 526                         label = "QSPI.SPL.backup2";
 527                         reg = <0x00020000 0x00010000>;
 528                 };
 529                 partition@3 {
 530                         label = "QSPI.SPL.backup3";
 531                         reg = <0x00030000 0x00010000>;
 532                 };
 533                 partition@4 {
 534                         label = "QSPI.u-boot";
 535                         reg = <0x00040000 0x00100000>;
 536                 };
 537                 partition@5 {
 538                         label = "QSPI.u-boot-spl-os";
 539                         reg = <0x00140000 0x00080000>;
 540                 };
 541                 partition@6 {
 542                         label = "QSPI.u-boot-env";
 543                         reg = <0x001c0000 0x00010000>;
 544                 };
 545                 partition@7 {
 546                         label = "QSPI.u-boot-env.backup1";
 547                         reg = <0x001d0000 0x0010000>;
 548                 };
 549                 partition@8 {
 550                         label = "QSPI.kernel";
 551                         reg = <0x001e0000 0x0800000>;
 552                 };
 553                 partition@9 {
 554                         label = "QSPI.file-system";
 555                         reg = <0x009e0000 0x01620000>;
 556                 };
 557         };
 558 };
 559
 560 &omap_dwc3_1 {
 561         extcon = <&extcon_usb1>;
 562 };
 563
 564 &omap_dwc3_2 {
 565         extcon = <&extcon_usb2>;
 566 };
 567
 568 &usb1 {
 569         dr_mode = "peripheral";
 570         pinctrl-names = "default";
 571         pinctrl-0 = <&usb1_pins>;
 572 };
 573
 574 &usb2 {
 575         dr_mode = "host";
 576         pinctrl-names = "default";
 577         pinctrl-0 = <&usb2_pins>;
 578 };
 579
 580 &elm {
 581         status = "okay";
 582 };
 583
 584 &gpmc {
 585         status = "okay";
 586         pinctrl-names = "default";
 587         pinctrl-0 = <&nand_flash_x16>;
 588         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 589         nand@0,0 {
 590                 reg = <0 0 4>;          /* device IO registers */
 591                 ti,nand-ecc-opt = "bch8";
 592                 ti,elm-id = <&elm>;
 593                 nand-bus-width = <16>;
 594                 gpmc,device-width = <2>;
 595                 gpmc,sync-clk-ps = <0>;
 596                 gpmc,cs-on-ns = <0>;
 597                 gpmc,cs-rd-off-ns = <80>;
 598                 gpmc,cs-wr-off-ns = <80>;
 599                 gpmc,adv-on-ns = <0>;
 600                 gpmc,adv-rd-off-ns = <60>;
 601                 gpmc,adv-wr-off-ns = <60>;
 602                 gpmc,we-on-ns = <10>;
 603                 gpmc,we-off-ns = <50>;
 604                 gpmc,oe-on-ns = <4>;
 605                 gpmc,oe-off-ns = <40>;
 606                 gpmc,access-ns = <40>;
 607                 gpmc,wr-access-ns = <80>;
 608                 gpmc,rd-cycle-ns = <80>;
 609                 gpmc,wr-cycle-ns = <80>;
 610                 gpmc,bus-turnaround-ns = <0>;
 611                 gpmc,cycle2cycle-delay-ns = <0>;
 612                 gpmc,clk-activation-ns = <0>;
 613                 gpmc,wait-monitoring-ns = <0>;
 614                 gpmc,wr-data-mux-bus-ns = <0>;
 615                 /* MTD partition table */
 616                 /* All SPL-* partitions are sized to minimal length
 617                  * which can be independently programmable. For
 618                  * NAND flash this is equal to size of erase-block */
 619                 #address-cells = <1>;
 620                 #size-cells = <1>;
 621                 partition@0 {
 622                         label = "NAND.SPL";
 623                         reg = <0x00000000 0x000020000>;
 624                 };
 625                 partition@1 {
 626                         label = "NAND.SPL.backup1";
 627                         reg = <0x00020000 0x00020000>;
 628                 };
 629                 partition@2 {
 630                         label = "NAND.SPL.backup2";
 631                         reg = <0x00040000 0x00020000>;
 632                 };
 633                 partition@3 {
 634                         label = "NAND.SPL.backup3";
 635                         reg = <0x00060000 0x00020000>;
 636                 };
 637                 partition@4 {
 638                         label = "NAND.u-boot-spl-os";
 639                         reg = <0x00080000 0x00040000>;
 640                 };
 641                 partition@5 {
 642                         label = "NAND.u-boot";
 643                         reg = <0x000c0000 0x00100000>;
 644                 };
 645                 partition@6 {
 646                         label = "NAND.u-boot-env";
 647                         reg = <0x001c0000 0x00020000>;
 648                 };
 649                 partition@7 {
 650                         label = "NAND.u-boot-env.backup1";
 651                         reg = <0x001e0000 0x00020000>;
 652                 };
 653                 partition@8 {
 654                         label = "NAND.kernel";
 655                         reg = <0x00200000 0x00800000>;
 656                 };
 657                 partition@9 {
 658                         label = "NAND.file-system";
 659                         reg = <0x00a00000 0x0f600000>;
 660                 };
 661         };
 662 };
 663
 664 &usb2_phy1 {
 665         phy-supply = <&ldousb_reg>;
 666 };
 667
 668 &usb2_phy2 {
 669         phy-supply = <&ldousb_reg>;
 670 };
 671
 672 &gpio7 {
 673         ti,no-reset-on-init;
 674         ti,no-idle-on-init;
 675 };
 676
 677 &mac {
 678         status = "okay";
 679         pinctrl-names = "default", "sleep";
 680         pinctrl-0 = <&cpsw_default>;
 681         pinctrl-1 = <&cpsw_sleep>;
 682         dual_emac;
 683 };
 684
 685 &cpsw_emac0 {
 686         phy_id = <&davinci_mdio>, <2>;
 687         phy-mode = "rgmii";
 688         dual_emac_res_vlan = <1>;
 689 };
 690
 691 &cpsw_emac1 {
 692         phy_id = <&davinci_mdio>, <3>;
 693         phy-mode = "rgmii";
 694         dual_emac_res_vlan = <2>;
 695 };
 696
 697 &davinci_mdio {
 698         pinctrl-names = "default", "sleep";
 699         pinctrl-0 = <&davinci_mdio_default>;
 700         pinctrl-1 = <&davinci_mdio_sleep>;
 701 };
 702
 703 &dcan1 {
 704         status = "ok";
 705         pinctrl-names = "default", "sleep", "active";
 706         pinctrl-0 = <&dcan1_pins_sleep>;
 707         pinctrl-1 = <&dcan1_pins_sleep>;
 708         pinctrl-2 = <&dcan1_pins_default>;
 709 };