arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         compatible = "ti,dra7xx";
  22         interrupt-parent = <&crossbar_mpu>;
  23
  24         aliases {
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 i2c4 = &i2c5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36                 serial6 = &uart7;
  37                 serial7 = &uart8;
  38                 serial8 = &uart9;
  39                 serial9 = &uart10;
  40                 ethernet0 = &cpsw_emac0;
  41                 ethernet1 = &cpsw_emac1;
  42                 d_can0 = &dcan1;
  43                 d_can1 = &dcan2;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&gic>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 reg = <0x48211000 0x1000>,
  60                       <0x48212000 0x1000>,
  61                       <0x48214000 0x2000>,
  62                       <0x48216000 0x2000>;
  63                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  64                 interrupt-parent = <&gic>;
  65         };
  66
  67         wakeupgen: interrupt-controller@48281000 {
  68                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  69                 interrupt-controller;
  70                 #interrupt-cells = <3>;
  71                 reg = <0x48281000 0x1000>;
  72                 interrupt-parent = <&gic>;
  73         };
  74
  75         /*
  76          * The soc node represents the soc top level view. It is used for IPs
  77          * that are not memory mapped in the MPU view or for the MPU itself.
  78          */
  79         soc {
  80                 compatible = "ti,omap-infra";
  81                 mpu {
  82                         compatible = "ti,omap5-mpu";
  83                         ti,hwmods = "mpu";
  84                 };
  85         };
  86
  87         /*
  88          * XXX: Use a flat representation of the SOC interconnect.
  89          * The real OMAP interconnect network is quite complex.
  90          * Since it will not bring real advantage to represent that in DT for
  91          * the moment, just use a fake OCP bus entry to represent the whole bus
  92          * hierarchy.
  93          */
  94         ocp {
  95                 compatible = "ti,dra7-l3-noc", "simple-bus";
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99                 ti,hwmods = "l3_main_1", "l3_main_2";
 100                 reg = <0x44000000 0x1000000>,
 101                       <0x45000000 0x1000>;
 102                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 103                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 104
 105                 l4_cfg: l4@4a000000 {
 106                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109                         ranges = <0 0x4a000000 0x22c000>;
 110
 111                         scm: scm@2000 {
 112                                 compatible = "ti,dra7-scm-core", "simple-bus";
 113                                 reg = <0x2000 0x2000>;
 114                                 #address-cells = <1>;
 115                                 #size-cells = <1>;
 116                                 ranges = <0 0x2000 0x2000>;
 117
 118                                 scm_conf: scm_conf@0 {
 119                                         compatible = "syscon", "simple-bus";
 120                                         reg = <0x0 0x1400>;
 121                                         #address-cells = <1>;
 122                                         #size-cells = <1>;
 123                                         ranges = <0 0x0 0x1400>;
 124
 125                                         pbias_regulator: pbias_regulator {
 126                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
 127                                                 reg = <0xe00 0x4>;
 128                                                 syscon = <&scm_conf>;
 129                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 130                                                         regulator-name = "pbias_mmc_omap5";
 131                                                         regulator-min-microvolt = <1800000>;
 132                                                         regulator-max-microvolt = <3000000>;
 133                                                 };
 134                                         };
 135
 136                                         scm_conf_clocks: clocks {
 137                                                 #address-cells = <1>;
 138                                                 #size-cells = <0>;
 139                                         };
 140                                 };
 141
 142                                 dra7_pmx_core: pinmux@1400 {
 143                                         compatible = "ti,dra7-padconf",
 144                                                      "pinctrl-single";
 145                                         reg = <0x1400 0x0468>;
 146                                         #address-cells = <1>;
 147                                         #size-cells = <0>;
 148                                         #interrupt-cells = <1>;
 149                                         interrupt-controller;
 150                                         pinctrl-single,register-width = <32>;
 151                                         pinctrl-single,function-mask = <0x3fffffff>;
 152                                 };
 153
 154                                 scm_conf1: scm_conf@1c04 {
 155                                         compatible = "syscon";
 156                                         reg = <0x1c04 0x0020>;
 157                                 };
 158                         };
 159
 160                         cm_core_aon: cm_core_aon@5000 {
 161                                 compatible = "ti,dra7-cm-core-aon";
 162                                 reg = <0x5000 0x2000>;
 163
 164                                 cm_core_aon_clocks: clocks {
 165                                         #address-cells = <1>;
 166                                         #size-cells = <0>;
 167                                 };
 168
 169                                 cm_core_aon_clockdomains: clockdomains {
 170                                 };
 171                         };
 172
 173                         cm_core: cm_core@8000 {
 174                                 compatible = "ti,dra7-cm-core";
 175                                 reg = <0x8000 0x3000>;
 176
 177                                 cm_core_clocks: clocks {
 178                                         #address-cells = <1>;
 179                                         #size-cells = <0>;
 180                                 };
 181
 182                                 cm_core_clockdomains: clockdomains {
 183                                 };
 184                         };
 185                 };
 186
 187                 l4_wkup: l4@4ae00000 {
 188                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 189                         #address-cells = <1>;
 190                         #size-cells = <1>;
 191                         ranges = <0 0x4ae00000 0x3f000>;
 192
 193                         counter32k: counter@4000 {
 194                                 compatible = "ti,omap-counter32k";
 195                                 reg = <0x4000 0x40>;
 196                                 ti,hwmods = "counter_32k";
 197                         };
 198
 199                         prm: prm@6000 {
 200                                 compatible = "ti,dra7-prm";
 201                                 reg = <0x6000 0x3000>;
 202                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 203
 204                                 prm_clocks: clocks {
 205                                         #address-cells = <1>;
 206                                         #size-cells = <0>;
 207                                 };
 208
 209                                 prm_clockdomains: clockdomains {
 210                                 };
 211                         };
 212                 };
 213
 214                 axi@0 {
 215                         compatible = "simple-bus";
 216                         #size-cells = <1>;
 217                         #address-cells = <1>;
 218                         ranges = <0x51000000 0x51000000 0x3000
 219                                   0x0        0x20000000 0x10000000>;
 220                         pcie1: pcie@51000000 {
 221                                 compatible = "ti,dra7-pcie";
 222                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 223                                 reg-names = "rc_dbics", "ti_conf", "config";
 224                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 225                                 #address-cells = <3>;
 226                                 #size-cells = <2>;
 227                                 device_type = "pci";
 228                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 229                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 230                                 #interrupt-cells = <1>;
 231                                 num-lanes = <1>;
 232                                 ti,hwmods = "pcie1";
 233                                 phys = <&pcie1_phy>;
 234                                 phy-names = "pcie-phy0";
 235                                 interrupt-map-mask = <0 0 0 7>;
 236                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 237                                                 <0 0 0 2 &pcie1_intc 2>,
 238                                                 <0 0 0 3 &pcie1_intc 3>,
 239                                                 <0 0 0 4 &pcie1_intc 4>;
 240                                 pcie1_intc: interrupt-controller {
 241                                         interrupt-controller;
 242                                         #address-cells = <0>;
 243                                         #interrupt-cells = <1>;
 244                                 };
 245                         };
 246                 };
 247
 248                 axi@1 {
 249                         compatible = "simple-bus";
 250                         #size-cells = <1>;
 251                         #address-cells = <1>;
 252                         ranges = <0x51800000 0x51800000 0x3000
 253                                   0x0        0x30000000 0x10000000>;
 254                         status = "disabled";
 255                         pcie@51000000 {
 256                                 compatible = "ti,dra7-pcie";
 257                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 258                                 reg-names = "rc_dbics", "ti_conf", "config";
 259                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 260                                 #address-cells = <3>;
 261                                 #size-cells = <2>;
 262                                 device_type = "pci";
 263                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 264                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 265                                 #interrupt-cells = <1>;
 266                                 num-lanes = <1>;
 267                                 ti,hwmods = "pcie2";
 268                                 phys = <&pcie2_phy>;
 269                                 phy-names = "pcie-phy0";
 270                                 interrupt-map-mask = <0 0 0 7>;
 271                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 272                                                 <0 0 0 2 &pcie2_intc 2>,
 273                                                 <0 0 0 3 &pcie2_intc 3>,
 274                                                 <0 0 0 4 &pcie2_intc 4>;
 275                                 pcie2_intc: interrupt-controller {
 276                                         interrupt-controller;
 277                                         #address-cells = <0>;
 278                                         #interrupt-cells = <1>;
 279                                 };
 280                         };
 281                 };
 282
 283                 bandgap: bandgap@4a0021e0 {
 284                         reg = <0x4a0021e0 0xc
 285                                 0x4a00232c 0xc
 286                                 0x4a002380 0x2c
 287                                 0x4a0023C0 0x3c
 288                                 0x4a002564 0x8
 289                                 0x4a002574 0x50>;
 290                                 compatible = "ti,dra752-bandgap";
 291                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 292                                 #thermal-sensor-cells = <1>;
 293                 };
 294
 295                 sdma: dma-controller@4a056000 {
 296                         compatible = "ti,omap4430-sdma";
 297                         reg = <0x4a056000 0x1000>;
 298                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 299                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 300                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 301                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 302                         #dma-cells = <1>;
 303                         dma-channels = <32>;
 304                         dma-requests = <127>;
 305                 };
 306
 307                 sdma_xbar: dma-router@4a002b78 {
 308                         compatible = "ti,dra7-dma-crossbar";
 309                         reg = <0x4a002b78 0xfc>;
 310                         #dma-cells = <1>;
 311                         dma-requests = <205>;
 312                         ti,dma-safe-map = <0>;
 313                         dma-masters = <&sdma>;
 314                 };
 315
 316                 gpio1: gpio@4ae10000 {
 317                         compatible = "ti,omap4-gpio";
 318                         reg = <0x4ae10000 0x200>;
 319                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 320                         ti,hwmods = "gpio1";
 321                         gpio-controller;
 322                         #gpio-cells = <2>;
 323                         interrupt-controller;
 324                         #interrupt-cells = <2>;
 325                 };
 326
 327                 gpio2: gpio@48055000 {
 328                         compatible = "ti,omap4-gpio";
 329                         reg = <0x48055000 0x200>;
 330                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 331                         ti,hwmods = "gpio2";
 332                         gpio-controller;
 333                         #gpio-cells = <2>;
 334                         interrupt-controller;
 335                         #interrupt-cells = <2>;
 336                 };
 337
 338                 gpio3: gpio@48057000 {
 339                         compatible = "ti,omap4-gpio";
 340                         reg = <0x48057000 0x200>;
 341                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 342                         ti,hwmods = "gpio3";
 343                         gpio-controller;
 344                         #gpio-cells = <2>;
 345                         interrupt-controller;
 346                         #interrupt-cells = <2>;
 347                 };
 348
 349                 gpio4: gpio@48059000 {
 350                         compatible = "ti,omap4-gpio";
 351                         reg = <0x48059000 0x200>;
 352                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 353                         ti,hwmods = "gpio4";
 354                         gpio-controller;
 355                         #gpio-cells = <2>;
 356                         interrupt-controller;
 357                         #interrupt-cells = <2>;
 358                 };
 359
 360                 gpio5: gpio@4805b000 {
 361                         compatible = "ti,omap4-gpio";
 362                         reg = <0x4805b000 0x200>;
 363                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 364                         ti,hwmods = "gpio5";
 365                         gpio-controller;
 366                         #gpio-cells = <2>;
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                 };
 370
 371                 gpio6: gpio@4805d000 {
 372                         compatible = "ti,omap4-gpio";
 373                         reg = <0x4805d000 0x200>;
 374                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 375                         ti,hwmods = "gpio6";
 376                         gpio-controller;
 377                         #gpio-cells = <2>;
 378                         interrupt-controller;
 379                         #interrupt-cells = <2>;
 380                 };
 381
 382                 gpio7: gpio@48051000 {
 383                         compatible = "ti,omap4-gpio";
 384                         reg = <0x48051000 0x200>;
 385                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 386                         ti,hwmods = "gpio7";
 387                         gpio-controller;
 388                         #gpio-cells = <2>;
 389                         interrupt-controller;
 390                         #interrupt-cells = <2>;
 391                 };
 392
 393                 gpio8: gpio@48053000 {
 394                         compatible = "ti,omap4-gpio";
 395                         reg = <0x48053000 0x200>;
 396                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 397                         ti,hwmods = "gpio8";
 398                         gpio-controller;
 399                         #gpio-cells = <2>;
 400                         interrupt-controller;
 401                         #interrupt-cells = <2>;
 402                 };
 403
 404                 uart1: serial@4806a000 {
 405                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 406                         reg = <0x4806a000 0x100>;
 407                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 408                         ti,hwmods = "uart1";
 409                         clock-frequency = <48000000>;
 410                         status = "disabled";
 411                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 412                         dma-names = "tx", "rx";
 413                 };
 414
 415                 uart2: serial@4806c000 {
 416                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 417                         reg = <0x4806c000 0x100>;
 418                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 419                         ti,hwmods = "uart2";
 420                         clock-frequency = <48000000>;
 421                         status = "disabled";
 422                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 423                         dma-names = "tx", "rx";
 424                 };
 425
 426                 uart3: serial@48020000 {
 427                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 428                         reg = <0x48020000 0x100>;
 429                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 430                         ti,hwmods = "uart3";
 431                         clock-frequency = <48000000>;
 432                         status = "disabled";
 433                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 434                         dma-names = "tx", "rx";
 435                 };
 436
 437                 uart4: serial@4806e000 {
 438                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 439                         reg = <0x4806e000 0x100>;
 440                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 441                         ti,hwmods = "uart4";
 442                         clock-frequency = <48000000>;
 443                         status = "disabled";
 444                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 445                         dma-names = "tx", "rx";
 446                 };
 447
 448                 uart5: serial@48066000 {
 449                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 450                         reg = <0x48066000 0x100>;
 451                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 452                         ti,hwmods = "uart5";
 453                         clock-frequency = <48000000>;
 454                         status = "disabled";
 455                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 456                         dma-names = "tx", "rx";
 457                 };
 458
 459                 uart6: serial@48068000 {
 460                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 461                         reg = <0x48068000 0x100>;
 462                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 463                         ti,hwmods = "uart6";
 464                         clock-frequency = <48000000>;
 465                         status = "disabled";
 466                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 467                         dma-names = "tx", "rx";
 468                 };
 469
 470                 uart7: serial@48420000 {
 471                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 472                         reg = <0x48420000 0x100>;
 473                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 474                         ti,hwmods = "uart7";
 475                         clock-frequency = <48000000>;
 476                         status = "disabled";
 477                 };
 478
 479                 uart8: serial@48422000 {
 480                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 481                         reg = <0x48422000 0x100>;
 482                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 483                         ti,hwmods = "uart8";
 484                         clock-frequency = <48000000>;
 485                         status = "disabled";
 486                 };
 487
 488                 uart9: serial@48424000 {
 489                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 490                         reg = <0x48424000 0x100>;
 491                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 492                         ti,hwmods = "uart9";
 493                         clock-frequency = <48000000>;
 494                         status = "disabled";
 495                 };
 496
 497                 uart10: serial@4ae2b000 {
 498                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 499                         reg = <0x4ae2b000 0x100>;
 500                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 501                         ti,hwmods = "uart10";
 502                         clock-frequency = <48000000>;
 503                         status = "disabled";
 504                 };
 505
 506                 mailbox1: mailbox@4a0f4000 {
 507                         compatible = "ti,omap4-mailbox";
 508                         reg = <0x4a0f4000 0x200>;
 509                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 510                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 511                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 512                         ti,hwmods = "mailbox1";
 513                         #mbox-cells = <1>;
 514                         ti,mbox-num-users = <3>;
 515                         ti,mbox-num-fifos = <8>;
 516                         status = "disabled";
 517                 };
 518
 519                 mailbox2: mailbox@4883a000 {
 520                         compatible = "ti,omap4-mailbox";
 521                         reg = <0x4883a000 0x200>;
 522                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 523                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 524                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 525                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 526                         ti,hwmods = "mailbox2";
 527                         #mbox-cells = <1>;
 528                         ti,mbox-num-users = <4>;
 529                         ti,mbox-num-fifos = <12>;
 530                         status = "disabled";
 531                 };
 532
 533                 mailbox3: mailbox@4883c000 {
 534                         compatible = "ti,omap4-mailbox";
 535                         reg = <0x4883c000 0x200>;
 536                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 537                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 538                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 539                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 540                         ti,hwmods = "mailbox3";
 541                         #mbox-cells = <1>;
 542                         ti,mbox-num-users = <4>;
 543                         ti,mbox-num-fifos = <12>;
 544                         status = "disabled";
 545                 };
 546
 547                 mailbox4: mailbox@4883e000 {
 548                         compatible = "ti,omap4-mailbox";
 549                         reg = <0x4883e000 0x200>;
 550                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 551                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 552                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 553                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 554                         ti,hwmods = "mailbox4";
 555                         #mbox-cells = <1>;
 556                         ti,mbox-num-users = <4>;
 557                         ti,mbox-num-fifos = <12>;
 558                         status = "disabled";
 559                 };
 560
 561                 mailbox5: mailbox@48840000 {
 562                         compatible = "ti,omap4-mailbox";
 563                         reg = <0x48840000 0x200>;
 564                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 566                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 567                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 568                         ti,hwmods = "mailbox5";
 569                         #mbox-cells = <1>;
 570                         ti,mbox-num-users = <4>;
 571                         ti,mbox-num-fifos = <12>;
 572                         status = "disabled";
 573                 };
 574
 575                 mailbox6: mailbox@48842000 {
 576                         compatible = "ti,omap4-mailbox";
 577                         reg = <0x48842000 0x200>;
 578                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 579                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 580                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 581                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 582                         ti,hwmods = "mailbox6";
 583                         #mbox-cells = <1>;
 584                         ti,mbox-num-users = <4>;
 585                         ti,mbox-num-fifos = <12>;
 586                         status = "disabled";
 587                 };
 588
 589                 mailbox7: mailbox@48844000 {
 590                         compatible = "ti,omap4-mailbox";
 591                         reg = <0x48844000 0x200>;
 592                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 593                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 594                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 595                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 596                         ti,hwmods = "mailbox7";
 597                         #mbox-cells = <1>;
 598                         ti,mbox-num-users = <4>;
 599                         ti,mbox-num-fifos = <12>;
 600                         status = "disabled";
 601                 };
 602
 603                 mailbox8: mailbox@48846000 {
 604                         compatible = "ti,omap4-mailbox";
 605                         reg = <0x48846000 0x200>;
 606                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 607                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 608                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 609                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 610                         ti,hwmods = "mailbox8";
 611                         #mbox-cells = <1>;
 612                         ti,mbox-num-users = <4>;
 613                         ti,mbox-num-fifos = <12>;
 614                         status = "disabled";
 615                 };
 616
 617                 mailbox9: mailbox@4885e000 {
 618                         compatible = "ti,omap4-mailbox";
 619                         reg = <0x4885e000 0x200>;
 620                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 621                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 622                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 623                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 624                         ti,hwmods = "mailbox9";
 625                         #mbox-cells = <1>;
 626                         ti,mbox-num-users = <4>;
 627                         ti,mbox-num-fifos = <12>;
 628                         status = "disabled";
 629                 };
 630
 631                 mailbox10: mailbox@48860000 {
 632                         compatible = "ti,omap4-mailbox";
 633                         reg = <0x48860000 0x200>;
 634                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 635                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 636                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 637                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 638                         ti,hwmods = "mailbox10";
 639                         #mbox-cells = <1>;
 640                         ti,mbox-num-users = <4>;
 641                         ti,mbox-num-fifos = <12>;
 642                         status = "disabled";
 643                 };
 644
 645                 mailbox11: mailbox@48862000 {
 646                         compatible = "ti,omap4-mailbox";
 647                         reg = <0x48862000 0x200>;
 648                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 651                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 652                         ti,hwmods = "mailbox11";
 653                         #mbox-cells = <1>;
 654                         ti,mbox-num-users = <4>;
 655                         ti,mbox-num-fifos = <12>;
 656                         status = "disabled";
 657                 };
 658
 659                 mailbox12: mailbox@48864000 {
 660                         compatible = "ti,omap4-mailbox";
 661                         reg = <0x48864000 0x200>;
 662                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 664                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 665                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 666                         ti,hwmods = "mailbox12";
 667                         #mbox-cells = <1>;
 668                         ti,mbox-num-users = <4>;
 669                         ti,mbox-num-fifos = <12>;
 670                         status = "disabled";
 671                 };
 672
 673                 mailbox13: mailbox@48802000 {
 674                         compatible = "ti,omap4-mailbox";
 675                         reg = <0x48802000 0x200>;
 676                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 677                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 679                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 680                         ti,hwmods = "mailbox13";
 681                         #mbox-cells = <1>;
 682                         ti,mbox-num-users = <4>;
 683                         ti,mbox-num-fifos = <12>;
 684                         status = "disabled";
 685                 };
 686
 687                 timer1: timer@4ae18000 {
 688                         compatible = "ti,omap5430-timer";
 689                         reg = <0x4ae18000 0x80>;
 690                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 691                         ti,hwmods = "timer1";
 692                         ti,timer-alwon;
 693                 };
 694
 695                 timer2: timer@48032000 {
 696                         compatible = "ti,omap5430-timer";
 697                         reg = <0x48032000 0x80>;
 698                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 699                         ti,hwmods = "timer2";
 700                 };
 701
 702                 timer3: timer@48034000 {
 703                         compatible = "ti,omap5430-timer";
 704                         reg = <0x48034000 0x80>;
 705                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 706                         ti,hwmods = "timer3";
 707                 };
 708
 709                 timer4: timer@48036000 {
 710                         compatible = "ti,omap5430-timer";
 711                         reg = <0x48036000 0x80>;
 712                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 713                         ti,hwmods = "timer4";
 714                 };
 715
 716                 timer5: timer@48820000 {
 717                         compatible = "ti,omap5430-timer";
 718                         reg = <0x48820000 0x80>;
 719                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 720                         ti,hwmods = "timer5";
 721                 };
 722
 723                 timer6: timer@48822000 {
 724                         compatible = "ti,omap5430-timer";
 725                         reg = <0x48822000 0x80>;
 726                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 727                         ti,hwmods = "timer6";
 728                 };
 729
 730                 timer7: timer@48824000 {
 731                         compatible = "ti,omap5430-timer";
 732                         reg = <0x48824000 0x80>;
 733                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 734                         ti,hwmods = "timer7";
 735                 };
 736
 737                 timer8: timer@48826000 {
 738                         compatible = "ti,omap5430-timer";
 739                         reg = <0x48826000 0x80>;
 740                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 741                         ti,hwmods = "timer8";
 742                 };
 743
 744                 timer9: timer@4803e000 {
 745                         compatible = "ti,omap5430-timer";
 746                         reg = <0x4803e000 0x80>;
 747                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 748                         ti,hwmods = "timer9";
 749                 };
 750
 751                 timer10: timer@48086000 {
 752                         compatible = "ti,omap5430-timer";
 753                         reg = <0x48086000 0x80>;
 754                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 755                         ti,hwmods = "timer10";
 756                 };
 757
 758                 timer11: timer@48088000 {
 759                         compatible = "ti,omap5430-timer";
 760                         reg = <0x48088000 0x80>;
 761                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 762                         ti,hwmods = "timer11";
 763                 };
 764
 765                 timer13: timer@48828000 {
 766                         compatible = "ti,omap5430-timer";
 767                         reg = <0x48828000 0x80>;
 768                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 769                         ti,hwmods = "timer13";
 770                         status = "disabled";
 771                 };
 772
 773                 timer14: timer@4882a000 {
 774                         compatible = "ti,omap5430-timer";
 775                         reg = <0x4882a000 0x80>;
 776                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 777                         ti,hwmods = "timer14";
 778                         status = "disabled";
 779                 };
 780
 781                 timer15: timer@4882c000 {
 782                         compatible = "ti,omap5430-timer";
 783                         reg = <0x4882c000 0x80>;
 784                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 785                         ti,hwmods = "timer15";
 786                         status = "disabled";
 787                 };
 788
 789                 timer16: timer@4882e000 {
 790                         compatible = "ti,omap5430-timer";
 791                         reg = <0x4882e000 0x80>;
 792                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 793                         ti,hwmods = "timer16";
 794                         status = "disabled";
 795                 };
 796
 797                 wdt2: wdt@4ae14000 {
 798                         compatible = "ti,omap3-wdt";
 799                         reg = <0x4ae14000 0x80>;
 800                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 801                         ti,hwmods = "wd_timer2";
 802                 };
 803
 804                 hwspinlock: spinlock@4a0f6000 {
 805                         compatible = "ti,omap4-hwspinlock";
 806                         reg = <0x4a0f6000 0x1000>;
 807                         ti,hwmods = "spinlock";
 808                         #hwlock-cells = <1>;
 809                 };
 810
 811                 dmm@4e000000 {
 812                         compatible = "ti,omap5-dmm";
 813                         reg = <0x4e000000 0x800>;
 814                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 815                         ti,hwmods = "dmm";
 816                 };
 817
 818                 i2c1: i2c@48070000 {
 819                         compatible = "ti,omap4-i2c";
 820                         reg = <0x48070000 0x100>;
 821                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 822                         #address-cells = <1>;
 823                         #size-cells = <0>;
 824                         ti,hwmods = "i2c1";
 825                         status = "disabled";
 826                 };
 827
 828                 i2c2: i2c@48072000 {
 829                         compatible = "ti,omap4-i2c";
 830                         reg = <0x48072000 0x100>;
 831                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 832                         #address-cells = <1>;
 833                         #size-cells = <0>;
 834                         ti,hwmods = "i2c2";
 835                         status = "disabled";
 836                 };
 837
 838                 i2c3: i2c@48060000 {
 839                         compatible = "ti,omap4-i2c";
 840                         reg = <0x48060000 0x100>;
 841                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 842                         #address-cells = <1>;
 843                         #size-cells = <0>;
 844                         ti,hwmods = "i2c3";
 845                         status = "disabled";
 846                 };
 847
 848                 i2c4: i2c@4807a000 {
 849                         compatible = "ti,omap4-i2c";
 850                         reg = <0x4807a000 0x100>;
 851                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 852                         #address-cells = <1>;
 853                         #size-cells = <0>;
 854                         ti,hwmods = "i2c4";
 855                         status = "disabled";
 856                 };
 857
 858                 i2c5: i2c@4807c000 {
 859                         compatible = "ti,omap4-i2c";
 860                         reg = <0x4807c000 0x100>;
 861                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 862                         #address-cells = <1>;
 863                         #size-cells = <0>;
 864                         ti,hwmods = "i2c5";
 865                         status = "disabled";
 866                 };
 867
 868                 mmc1: mmc@4809c000 {
 869                         compatible = "ti,omap4-hsmmc";
 870                         reg = <0x4809c000 0x400>;
 871                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 872                         ti,hwmods = "mmc1";
 873                         ti,dual-volt;
 874                         ti,needs-special-reset;
 875                         dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
 876                         dma-names = "tx", "rx";
 877                         status = "disabled";
 878                         pbias-supply = <&pbias_mmc_reg>;
 879                 };
 880
 881                 mmc2: mmc@480b4000 {
 882                         compatible = "ti,omap4-hsmmc";
 883                         reg = <0x480b4000 0x400>;
 884                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 885                         ti,hwmods = "mmc2";
 886                         ti,needs-special-reset;
 887                         dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
 888                         dma-names = "tx", "rx";
 889                         status = "disabled";
 890                 };
 891
 892                 mmc3: mmc@480ad000 {
 893                         compatible = "ti,omap4-hsmmc";
 894                         reg = <0x480ad000 0x400>;
 895                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 896                         ti,hwmods = "mmc3";
 897                         ti,needs-special-reset;
 898                         dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
 899                         dma-names = "tx", "rx";
 900                         status = "disabled";
 901                 };
 902
 903                 mmc4: mmc@480d1000 {
 904                         compatible = "ti,omap4-hsmmc";
 905                         reg = <0x480d1000 0x400>;
 906                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 907                         ti,hwmods = "mmc4";
 908                         ti,needs-special-reset;
 909                         dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
 910                         dma-names = "tx", "rx";
 911                         status = "disabled";
 912                 };
 913
 914                 abb_mpu: regulator-abb-mpu {
 915                         compatible = "ti,abb-v3";
 916                         regulator-name = "abb_mpu";
 917                         #address-cells = <0>;
 918                         #size-cells = <0>;
 919                         clocks = <&sys_clkin1>;
 920                         ti,settling-time = <50>;
 921                         ti,clock-cycles = <16>;
 922
 923                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 924                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
 925                               <0x4ae0c158 0x4>;
 926                         reg-names = "setup-address", "control-address",
 927                                     "int-address", "efuse-address",
 928                                     "ldo-address";
 929                         ti,tranxdone-status-mask = <0x80>;
 930                         /* LDOVBBMPU_FBB_MUX_CTRL */
 931                         ti,ldovbb-override-mask = <0x400>;
 932                         /* LDOVBBMPU_FBB_VSET_OUT */
 933                         ti,ldovbb-vset-mask = <0x1F>;
 934
 935                         /*
 936                          * NOTE: only FBB mode used but actual vset will
 937                          * determine final biasing
 938                          */
 939                         ti,abb_info = <
 940                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 941                         1060000         0       0x0     0 0x02000000 0x01F00000
 942                         1160000         0       0x4     0 0x02000000 0x01F00000
 943                         1210000         0       0x8     0 0x02000000 0x01F00000
 944                         >;
 945                 };
 946
 947                 abb_ivahd: regulator-abb-ivahd {
 948                         compatible = "ti,abb-v3";
 949                         regulator-name = "abb_ivahd";
 950                         #address-cells = <0>;
 951                         #size-cells = <0>;
 952                         clocks = <&sys_clkin1>;
 953                         ti,settling-time = <50>;
 954                         ti,clock-cycles = <16>;
 955
 956                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 957                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
 958                               <0x4a002470 0x4>;
 959                         reg-names = "setup-address", "control-address",
 960                                     "int-address", "efuse-address",
 961                                     "ldo-address";
 962                         ti,tranxdone-status-mask = <0x40000000>;
 963                         /* LDOVBBIVA_FBB_MUX_CTRL */
 964                         ti,ldovbb-override-mask = <0x400>;
 965                         /* LDOVBBIVA_FBB_VSET_OUT */
 966                         ti,ldovbb-vset-mask = <0x1F>;
 967
 968                         /*
 969                          * NOTE: only FBB mode used but actual vset will
 970                          * determine final biasing
 971                          */
 972                         ti,abb_info = <
 973                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 974                         1055000         0       0x0     0 0x02000000 0x01F00000
 975                         1150000         0       0x4     0 0x02000000 0x01F00000
 976                         1250000         0       0x8     0 0x02000000 0x01F00000
 977                         >;
 978                 };
 979
 980                 abb_dspeve: regulator-abb-dspeve {
 981                         compatible = "ti,abb-v3";
 982                         regulator-name = "abb_dspeve";
 983                         #address-cells = <0>;
 984                         #size-cells = <0>;
 985                         clocks = <&sys_clkin1>;
 986                         ti,settling-time = <50>;
 987                         ti,clock-cycles = <16>;
 988
 989                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 990                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
 991                               <0x4a00246c 0x4>;
 992                         reg-names = "setup-address", "control-address",
 993                                     "int-address", "efuse-address",
 994                                     "ldo-address";
 995                         ti,tranxdone-status-mask = <0x20000000>;
 996                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 997                         ti,ldovbb-override-mask = <0x400>;
 998                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 999                         ti,ldovbb-vset-mask = <0x1F>;
1000
1001                         /*
1002                          * NOTE: only FBB mode used but actual vset will
1003                          * determine final biasing
1004                          */
1005                         ti,abb_info = <
1006                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1007                         1055000         0       0x0     0 0x02000000 0x01F00000
1008                         1150000         0       0x4     0 0x02000000 0x01F00000
1009                         1250000         0       0x8     0 0x02000000 0x01F00000
1010                         >;
1011                 };
1012
1013                 abb_gpu: regulator-abb-gpu {
1014                         compatible = "ti,abb-v3";
1015                         regulator-name = "abb_gpu";
1016                         #address-cells = <0>;
1017                         #size-cells = <0>;
1018                         clocks = <&sys_clkin1>;
1019                         ti,settling-time = <50>;
1020                         ti,clock-cycles = <16>;
1021
1022                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1023                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1024                               <0x4ae0c154 0x4>;
1025                         reg-names = "setup-address", "control-address",
1026                                     "int-address", "efuse-address",
1027                                     "ldo-address";
1028                         ti,tranxdone-status-mask = <0x10000000>;
1029                         /* LDOVBBGPU_FBB_MUX_CTRL */
1030                         ti,ldovbb-override-mask = <0x400>;
1031                         /* LDOVBBGPU_FBB_VSET_OUT */
1032                         ti,ldovbb-vset-mask = <0x1F>;
1033
1034                         /*
1035                          * NOTE: only FBB mode used but actual vset will
1036                          * determine final biasing
1037                          */
1038                         ti,abb_info = <
1039                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1040                         1090000         0       0x0     0 0x02000000 0x01F00000
1041                         1210000         0       0x4     0 0x02000000 0x01F00000
1042                         1280000         0       0x8     0 0x02000000 0x01F00000
1043                         >;
1044                 };
1045
1046                 mcspi1: spi@48098000 {
1047                         compatible = "ti,omap4-mcspi";
1048                         reg = <0x48098000 0x200>;
1049                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1050                         #address-cells = <1>;
1051                         #size-cells = <0>;
1052                         ti,hwmods = "mcspi1";
1053                         ti,spi-num-cs = <4>;
1054                         dmas = <&sdma_xbar 35>,
1055                                <&sdma_xbar 36>,
1056                                <&sdma_xbar 37>,
1057                                <&sdma_xbar 38>,
1058                                <&sdma_xbar 39>,
1059                                <&sdma_xbar 40>,
1060                                <&sdma_xbar 41>,
1061                                <&sdma_xbar 42>;
1062                         dma-names = "tx0", "rx0", "tx1", "rx1",
1063                                     "tx2", "rx2", "tx3", "rx3";
1064                         status = "disabled";
1065                 };
1066
1067                 mcspi2: spi@4809a000 {
1068                         compatible = "ti,omap4-mcspi";
1069                         reg = <0x4809a000 0x200>;
1070                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1071                         #address-cells = <1>;
1072                         #size-cells = <0>;
1073                         ti,hwmods = "mcspi2";
1074                         ti,spi-num-cs = <2>;
1075                         dmas = <&sdma_xbar 43>,
1076                                <&sdma_xbar 44>,
1077                                <&sdma_xbar 45>,
1078                                <&sdma_xbar 46>;
1079                         dma-names = "tx0", "rx0", "tx1", "rx1";
1080                         status = "disabled";
1081                 };
1082
1083                 mcspi3: spi@480b8000 {
1084                         compatible = "ti,omap4-mcspi";
1085                         reg = <0x480b8000 0x200>;
1086                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1087                         #address-cells = <1>;
1088                         #size-cells = <0>;
1089                         ti,hwmods = "mcspi3";
1090                         ti,spi-num-cs = <2>;
1091                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1092                         dma-names = "tx0", "rx0";
1093                         status = "disabled";
1094                 };
1095
1096                 mcspi4: spi@480ba000 {
1097                         compatible = "ti,omap4-mcspi";
1098                         reg = <0x480ba000 0x200>;
1099                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1100                         #address-cells = <1>;
1101                         #size-cells = <0>;
1102                         ti,hwmods = "mcspi4";
1103                         ti,spi-num-cs = <1>;
1104                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1105                         dma-names = "tx0", "rx0";
1106                         status = "disabled";
1107                 };
1108
1109                 qspi: qspi@4b300000 {
1110                         compatible = "ti,dra7xxx-qspi";
1111                         reg = <0x4b300000 0x100>;
1112                         reg-names = "qspi_base";
1113                         #address-cells = <1>;
1114                         #size-cells = <0>;
1115                         ti,hwmods = "qspi";
1116                         clocks = <&qspi_gfclk_div>;
1117                         clock-names = "fck";
1118                         num-cs = <4>;
1119                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1120                         status = "disabled";
1121                 };
1122
1123                 omap_control_sata: control-phy@4a002374 {
1124                         compatible = "ti,control-phy-pipe3";
1125                         reg = <0x4a002374 0x4>;
1126                         reg-names = "power";
1127                         clocks = <&sys_clkin1>;
1128                         clock-names = "sysclk";
1129                 };
1130
1131                 /* OCP2SCP3 */
1132                 ocp2scp@4a090000 {
1133                         compatible = "ti,omap-ocp2scp";
1134                         #address-cells = <1>;
1135                         #size-cells = <1>;
1136                         ranges;
1137                         reg = <0x4a090000 0x20>;
1138                         ti,hwmods = "ocp2scp3";
1139                         sata_phy: phy@4A096000 {
1140                                 compatible = "ti,phy-pipe3-sata";
1141                                 reg = <0x4A096000 0x80>, /* phy_rx */
1142                                       <0x4A096400 0x64>, /* phy_tx */
1143                                       <0x4A096800 0x40>; /* pll_ctrl */
1144                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1145                                 ctrl-module = <&omap_control_sata>;
1146                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1147                                 clock-names = "sysclk", "refclk";
1148                                 syscon-pllreset = <&scm_conf 0x3fc>;
1149                                 #phy-cells = <0>;
1150                         };
1151
1152                         pcie1_phy: pciephy@4a094000 {
1153                                 compatible = "ti,phy-pipe3-pcie";
1154                                 reg = <0x4a094000 0x80>, /* phy_rx */
1155                                       <0x4a094400 0x64>; /* phy_tx */
1156                                 reg-names = "phy_rx", "phy_tx";
1157                                 ctrl-module = <&omap_control_pcie1phy>;
1158                                 clocks = <&dpll_pcie_ref_ck>,
1159                                          <&dpll_pcie_ref_m2ldo_ck>,
1160                                          <&optfclk_pciephy1_32khz>,
1161                                          <&optfclk_pciephy1_clk>,
1162                                          <&optfclk_pciephy1_div_clk>,
1163                                          <&optfclk_pciephy_div>;
1164                                 clock-names = "dpll_ref", "dpll_ref_m2",
1165                                               "wkupclk", "refclk",
1166                                               "div-clk", "phy-div";
1167                                 #phy-cells = <0>;
1168                         };
1169
1170                         pcie2_phy: pciephy@4a095000 {
1171                                 compatible = "ti,phy-pipe3-pcie";
1172                                 reg = <0x4a095000 0x80>, /* phy_rx */
1173                                       <0x4a095400 0x64>; /* phy_tx */
1174                                 reg-names = "phy_rx", "phy_tx";
1175                                 ctrl-module = <&omap_control_pcie2phy>;
1176                                 clocks = <&dpll_pcie_ref_ck>,
1177                                          <&dpll_pcie_ref_m2ldo_ck>,
1178                                          <&optfclk_pciephy2_32khz>,
1179                                          <&optfclk_pciephy2_clk>,
1180                                          <&optfclk_pciephy2_div_clk>,
1181                                          <&optfclk_pciephy_div>;
1182                                 clock-names = "dpll_ref", "dpll_ref_m2",
1183                                               "wkupclk", "refclk",
1184                                               "div-clk", "phy-div";
1185                                 #phy-cells = <0>;
1186                                 status = "disabled";
1187                         };
1188                 };
1189
1190                 sata: sata@4a141100 {
1191                         compatible = "snps,dwc-ahci";
1192                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1193                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1194                         phys = <&sata_phy>;
1195                         phy-names = "sata-phy";
1196                         clocks = <&sata_ref_clk>;
1197                         ti,hwmods = "sata";
1198                 };
1199
1200                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1201                         compatible = "ti,control-phy-pcie";
1202                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1203                         reg-names = "power", "control_sma", "pcie_pcs";
1204                         clocks = <&sys_clkin1>;
1205                         clock-names = "sysclk";
1206                 };
1207
1208                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1209                         compatible = "ti,control-phy-pcie";
1210                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1211                         reg-names = "power", "control_sma", "pcie_pcs";
1212                         clocks = <&sys_clkin1>;
1213                         clock-names = "sysclk";
1214                         status = "disabled";
1215                 };
1216
1217                 rtc: rtc@48838000 {
1218                         compatible = "ti,am3352-rtc";
1219                         reg = <0x48838000 0x100>;
1220                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1221                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1222                         ti,hwmods = "rtcss";
1223                         clocks = <&sys_32k_ck>;
1224                 };
1225
1226                 omap_control_usb2phy1: control-phy@4a002300 {
1227                         compatible = "ti,control-phy-usb2";
1228                         reg = <0x4a002300 0x4>;
1229                         reg-names = "power";
1230                 };
1231
1232                 omap_control_usb3phy1: control-phy@4a002370 {
1233                         compatible = "ti,control-phy-pipe3";
1234                         reg = <0x4a002370 0x4>;
1235                         reg-names = "power";
1236                 };
1237
1238                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1239                         compatible = "ti,control-phy-usb2-dra7";
1240                         reg = <0x4a002e74 0x4>;
1241                         reg-names = "power";
1242                 };
1243
1244                 /* OCP2SCP1 */
1245                 ocp2scp@4a080000 {
1246                         compatible = "ti,omap-ocp2scp";
1247                         #address-cells = <1>;
1248                         #size-cells = <1>;
1249                         ranges;
1250                         reg = <0x4a080000 0x20>;
1251                         ti,hwmods = "ocp2scp1";
1252
1253                         usb2_phy1: phy@4a084000 {
1254                                 compatible = "ti,omap-usb2";
1255                                 reg = <0x4a084000 0x400>;
1256                                 ctrl-module = <&omap_control_usb2phy1>;
1257                                 clocks = <&usb_phy1_always_on_clk32k>,
1258                                          <&usb_otg_ss1_refclk960m>;
1259                                 clock-names =   "wkupclk",
1260                                                 "refclk";
1261                                 #phy-cells = <0>;
1262                         };
1263
1264                         usb2_phy2: phy@4a085000 {
1265                                 compatible = "ti,omap-usb2";
1266                                 reg = <0x4a085000 0x400>;
1267                                 ctrl-module = <&omap_control_usb2phy2>;
1268                                 clocks = <&usb_phy2_always_on_clk32k>,
1269                                          <&usb_otg_ss2_refclk960m>;
1270                                 clock-names =   "wkupclk",
1271                                                 "refclk";
1272                                 #phy-cells = <0>;
1273                         };
1274
1275                         usb3_phy1: phy@4a084400 {
1276                                 compatible = "ti,omap-usb3";
1277                                 reg = <0x4a084400 0x80>,
1278                                       <0x4a084800 0x64>,
1279                                       <0x4a084c00 0x40>;
1280                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1281                                 ctrl-module = <&omap_control_usb3phy1>;
1282                                 clocks = <&usb_phy3_always_on_clk32k>,
1283                                          <&sys_clkin1>,
1284                                          <&usb_otg_ss1_refclk960m>;
1285                                 clock-names =   "wkupclk",
1286                                                 "sysclk",
1287                                                 "refclk";
1288                                 #phy-cells = <0>;
1289                         };
1290                 };
1291
1292                 omap_dwc3_1: omap_dwc3_1@48880000 {
1293                         compatible = "ti,dwc3";
1294                         ti,hwmods = "usb_otg_ss1";
1295                         reg = <0x48880000 0x10000>;
1296                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1297                         #address-cells = <1>;
1298                         #size-cells = <1>;
1299                         utmi-mode = <2>;
1300                         ranges;
1301                         usb1: usb@48890000 {
1302                                 compatible = "snps,dwc3";
1303                                 reg = <0x48890000 0x17000>;
1304                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1305                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1306                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1307                                 interrupt-names = "peripheral",
1308                                                   "host",
1309                                                   "otg";
1310                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1311                                 phy-names = "usb2-phy", "usb3-phy";
1312                                 tx-fifo-resize;
1313                                 maximum-speed = "super-speed";
1314                                 dr_mode = "otg";
1315                                 snps,dis_u3_susphy_quirk;
1316                                 snps,dis_u2_susphy_quirk;
1317                         };
1318                 };
1319
1320                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1321                         compatible = "ti,dwc3";
1322                         ti,hwmods = "usb_otg_ss2";
1323                         reg = <0x488c0000 0x10000>;
1324                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1325                         #address-cells = <1>;
1326                         #size-cells = <1>;
1327                         utmi-mode = <2>;
1328                         ranges;
1329                         usb2: usb@488d0000 {
1330                                 compatible = "snps,dwc3";
1331                                 reg = <0x488d0000 0x17000>;
1332                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1333                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1334                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1335                                 interrupt-names = "peripheral",
1336                                                   "host",
1337                                                   "otg";
1338                                 phys = <&usb2_phy2>;
1339                                 phy-names = "usb2-phy";
1340                                 tx-fifo-resize;
1341                                 maximum-speed = "high-speed";
1342                                 dr_mode = "otg";
1343                                 snps,dis_u3_susphy_quirk;
1344                                 snps,dis_u2_susphy_quirk;
1345                         };
1346                 };
1347
1348                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1349                 omap_dwc3_3: omap_dwc3_3@48900000 {
1350                         compatible = "ti,dwc3";
1351                         ti,hwmods = "usb_otg_ss3";
1352                         reg = <0x48900000 0x10000>;
1353                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1354                         #address-cells = <1>;
1355                         #size-cells = <1>;
1356                         utmi-mode = <2>;
1357                         ranges;
1358                         status = "disabled";
1359                         usb3: usb@48910000 {
1360                                 compatible = "snps,dwc3";
1361                                 reg = <0x48910000 0x17000>;
1362                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1363                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1364                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1365                                 interrupt-names = "peripheral",
1366                                                   "host",
1367                                                   "otg";
1368                                 tx-fifo-resize;
1369                                 maximum-speed = "high-speed";
1370                                 dr_mode = "otg";
1371                                 snps,dis_u3_susphy_quirk;
1372                                 snps,dis_u2_susphy_quirk;
1373                         };
1374                 };
1375
1376                 elm: elm@48078000 {
1377                         compatible = "ti,am3352-elm";
1378                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1379                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1380                         ti,hwmods = "elm";
1381                         status = "disabled";
1382                 };
1383
1384                 gpmc: gpmc@50000000 {
1385                         compatible = "ti,am3352-gpmc";
1386                         ti,hwmods = "gpmc";
1387                         reg = <0x50000000 0x37c>;      /* device IO registers */
1388                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1389                         gpmc,num-cs = <8>;
1390                         gpmc,num-waitpins = <2>;
1391                         #address-cells = <2>;
1392                         #size-cells = <1>;
1393                         status = "disabled";
1394                 };
1395
1396                 atl: atl@4843c000 {
1397                         compatible = "ti,dra7-atl";
1398                         reg = <0x4843c000 0x3ff>;
1399                         ti,hwmods = "atl";
1400                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1401                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1402                         clocks = <&atl_gfclk_mux>;
1403                         clock-names = "fck";
1404                         status = "disabled";
1405                 };
1406
1407                 crossbar_mpu: crossbar@4a002a48 {
1408                         compatible = "ti,irq-crossbar";
1409                         reg = <0x4a002a48 0x130>;
1410                         interrupt-controller;
1411                         interrupt-parent = <&wakeupgen>;
1412                         #interrupt-cells = <3>;
1413                         ti,max-irqs = <160>;
1414                         ti,max-crossbar-sources = <MAX_SOURCES>;
1415                         ti,reg-size = <2>;
1416                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1417                         ti,irqs-skip = <10 133 139 140>;
1418                         ti,irqs-safe-map = <0>;
1419                 };
1420
1421                 mac: ethernet@48484000 {
1422                         compatible = "ti,dra7-cpsw","ti,cpsw";
1423                         ti,hwmods = "gmac";
1424                         clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1425                         clock-names = "fck", "cpts";
1426                         cpdma_channels = <8>;
1427                         ale_entries = <1024>;
1428                         bd_ram_size = <0x2000>;
1429                         no_bd_ram = <0>;
1430                         rx_descs = <64>;
1431                         mac_control = <0x20>;
1432                         slaves = <2>;
1433                         active_slave = <0>;
1434                         cpts_clock_mult = <0x80000000>;
1435                         cpts_clock_shift = <29>;
1436                         reg = <0x48484000 0x1000
1437                                0x48485200 0x2E00>;
1438                         #address-cells = <1>;
1439                         #size-cells = <1>;
1440                         /*
1441                          * rx_thresh_pend
1442                          * rx_pend
1443                          * tx_pend
1444                          * misc_pend
1445                          */
1446                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1447                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1448                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1449                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1450                         ranges;
1451                         syscon = <&scm_conf>;
1452                         status = "disabled";
1453
1454                         davinci_mdio: mdio@48485000 {
1455                                 compatible = "ti,davinci_mdio";
1456                                 #address-cells = <1>;
1457                                 #size-cells = <0>;
1458                                 ti,hwmods = "davinci_mdio";
1459                                 bus_freq = <1000000>;
1460                                 reg = <0x48485000 0x100>;
1461                         };
1462
1463                         cpsw_emac0: slave@48480200 {
1464                                 /* Filled in by U-Boot */
1465                                 mac-address = [ 00 00 00 00 00 00 ];
1466                         };
1467
1468                         cpsw_emac1: slave@48480300 {
1469                                 /* Filled in by U-Boot */
1470                                 mac-address = [ 00 00 00 00 00 00 ];
1471                         };
1472
1473                         phy_sel: cpsw-phy-sel@4a002554 {
1474                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1475                                 reg= <0x4a002554 0x4>;
1476                                 reg-names = "gmii-sel";
1477                         };
1478                 };
1479
1480                 dcan1: can@481cc000 {
1481                         compatible = "ti,dra7-d_can";
1482                         ti,hwmods = "dcan1";
1483                         reg = <0x4ae3c000 0x2000>;
1484                         syscon-raminit = <&scm_conf 0x558 0>;
1485                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1486                         clocks = <&dcan1_sys_clk_mux>;
1487                         status = "disabled";
1488                 };
1489
1490                 dcan2: can@481d0000 {
1491                         compatible = "ti,dra7-d_can";
1492                         ti,hwmods = "dcan2";
1493                         reg = <0x48480000 0x2000>;
1494                         syscon-raminit = <&scm_conf 0x558 1>;
1495                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1496                         clocks = <&sys_clkin1>;
1497                         status = "disabled";
1498                 };
1499
1500                 dss: dss@58000000 {
1501                         compatible = "ti,dra7-dss";
1502                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1503                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1504                         status = "disabled";
1505                         ti,hwmods = "dss_core";
1506                         /* CTRL_CORE_DSS_PLL_CONTROL */
1507                         syscon-pll-ctrl = <&scm_conf 0x538>;
1508                         #address-cells = <1>;
1509                         #size-cells = <1>;
1510                         ranges;
1511
1512                         dispc@58001000 {
1513                                 compatible = "ti,dra7-dispc";
1514                                 reg = <0x58001000 0x1000>;
1515                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1516                                 ti,hwmods = "dss_dispc";
1517                                 clocks = <&dss_dss_clk>;
1518                                 clock-names = "fck";
1519                                 /* CTRL_CORE_SMA_SW_1 */
1520                                 syscon-pol = <&scm_conf 0x534>;
1521                         };
1522
1523                         hdmi: encoder@58060000 {
1524                                 compatible = "ti,dra7-hdmi";
1525                                 reg = <0x58040000 0x200>,
1526                                       <0x58040200 0x80>,
1527                                       <0x58040300 0x80>,
1528                                       <0x58060000 0x19000>;
1529                                 reg-names = "wp", "pll", "phy", "core";
1530                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1531                                 status = "disabled";
1532                                 ti,hwmods = "dss_hdmi";
1533                                 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1534                                 clock-names = "fck", "sys_clk";
1535                         };
1536                 };
1537         };
1538
1539         thermal_zones: thermal-zones {
1540                 #include "omap4-cpu-thermal.dtsi"
1541                 #include "omap5-gpu-thermal.dtsi"
1542                 #include "omap5-core-thermal.dtsi"
1543         };
1544
1545 };
1546
1547 &cpu_thermal {
1548         polling-delay = <500>; /* milliseconds */
1549 };
1550
1551 /include/ "dra7xx-clocks.dtsi"