arch/arm/boot/dts/exynos4.dtsi

   1 /*
   2  * Samsung's Exynos4 SoC series common device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
  10  * SoCs from Exynos4 series can include this file and provide values for SoCs
  11  * specfic bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <dt-bindings/clock/exynos4.h>
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24 #include "skeleton.dtsi"
  25
  26 / {
  27         interrupt-parent = <&gic>;
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 csis0 = &csis_0;
  43                 csis1 = &csis_1;
  44                 fimc0 = &fimc_0;
  45                 fimc1 = &fimc_1;
  46                 fimc2 = &fimc_2;
  47                 fimc3 = &fimc_3;
  48                 serial0 = &serial_0;
  49                 serial1 = &serial_1;
  50                 serial2 = &serial_2;
  51                 serial3 = &serial_3;
  52         };
  53
  54         clock_audss: clock-controller@03810000 {
  55                 compatible = "samsung,exynos4210-audss-clock";
  56                 reg = <0x03810000 0x0C>;
  57                 #clock-cells = <1>;
  58         };
  59
  60         i2s0: i2s@03830000 {
  61                 compatible = "samsung,s5pv210-i2s";
  62                 reg = <0x03830000 0x100>;
  63                 clocks = <&clock_audss EXYNOS_I2S_BUS>;
  64                 clock-names = "iis";
  65                 #clock-cells = <1>;
  66                 clock-output-names = "i2s_cdclk0";
  67                 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
  68                 dma-names = "tx", "rx", "tx-sec";
  69                 samsung,idma-addr = <0x03000000>;
  70                 #sound-dai-cells = <1>;
  71                 status = "disabled";
  72         };
  73
  74         chipid@10000000 {
  75                 compatible = "samsung,exynos4210-chipid";
  76                 reg = <0x10000000 0x100>;
  77         };
  78
  79         sromc@12570000 {
  80                 compatible = "samsung,exynos-srom";
  81                 reg = <0x12570000 0x10>;
  82         };
  83
  84         mipi_phy: video-phy@10020710 {
  85                 compatible = "samsung,s5pv210-mipi-video-phy";
  86                 #phy-cells = <1>;
  87                 syscon = <&pmu_system_controller>;
  88         };
  89
  90         pd_mfc: mfc-power-domain@10023C40 {
  91                 compatible = "samsung,exynos4210-pd";
  92                 reg = <0x10023C40 0x20>;
  93                 #power-domain-cells = <0>;
  94         };
  95
  96         pd_g3d: g3d-power-domain@10023C60 {
  97                 compatible = "samsung,exynos4210-pd";
  98                 reg = <0x10023C60 0x20>;
  99                 #power-domain-cells = <0>;
 100         };
 101
 102         pd_lcd0: lcd0-power-domain@10023C80 {
 103                 compatible = "samsung,exynos4210-pd";
 104                 reg = <0x10023C80 0x20>;
 105                 #power-domain-cells = <0>;
 106         };
 107
 108         pd_tv: tv-power-domain@10023C20 {
 109                 compatible = "samsung,exynos4210-pd";
 110                 reg = <0x10023C20 0x20>;
 111                 #power-domain-cells = <0>;
 112                 power-domains = <&pd_lcd0>;
 113         };
 114
 115         pd_cam: cam-power-domain@10023C00 {
 116                 compatible = "samsung,exynos4210-pd";
 117                 reg = <0x10023C00 0x20>;
 118                 #power-domain-cells = <0>;
 119         };
 120
 121         pd_gps: gps-power-domain@10023CE0 {
 122                 compatible = "samsung,exynos4210-pd";
 123                 reg = <0x10023CE0 0x20>;
 124                 #power-domain-cells = <0>;
 125         };
 126
 127         pd_gps_alive: gps-alive-power-domain@10023D00 {
 128                 compatible = "samsung,exynos4210-pd";
 129                 reg = <0x10023D00 0x20>;
 130                 #power-domain-cells = <0>;
 131         };
 132
 133         gic: interrupt-controller@10490000 {
 134                 compatible = "arm,cortex-a9-gic";
 135                 #interrupt-cells = <3>;
 136                 interrupt-controller;
 137                 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
 138         };
 139
 140         combiner: interrupt-controller@10440000 {
 141                 compatible = "samsung,exynos4210-combiner";
 142                 #interrupt-cells = <2>;
 143                 interrupt-controller;
 144                 reg = <0x10440000 0x1000>;
 145         };
 146
 147         pmu {
 148                 compatible = "arm,cortex-a9-pmu";
 149                 interrupt-parent = <&combiner>;
 150                 interrupts = <2 2>, <3 2>;
 151         };
 152
 153         sys_reg: syscon@10010000 {
 154                 compatible = "samsung,exynos4-sysreg", "syscon";
 155                 reg = <0x10010000 0x400>;
 156         };
 157
 158         pmu_system_controller: system-controller@10020000 {
 159                 compatible = "samsung,exynos4210-pmu", "syscon";
 160                 reg = <0x10020000 0x4000>;
 161                 interrupt-controller;
 162                 #interrupt-cells = <3>;
 163                 interrupt-parent = <&gic>;
 164         };
 165
 166         dsi_0: dsi@11C80000 {
 167                 compatible = "samsung,exynos4210-mipi-dsi";
 168                 reg = <0x11C80000 0x10000>;
 169                 interrupts = <0 79 0>;
 170                 power-domains = <&pd_lcd0>;
 171                 phys = <&mipi_phy 1>;
 172                 phy-names = "dsim";
 173                 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
 174                 clock-names = "bus_clk", "sclk_mipi";
 175                 status = "disabled";
 176                 #address-cells = <1>;
 177                 #size-cells = <0>;
 178         };
 179
 180         camera {
 181                 compatible = "samsung,fimc", "simple-bus";
 182                 status = "disabled";
 183                 #address-cells = <1>;
 184                 #size-cells = <1>;
 185                 #clock-cells = <1>;
 186                 clock-output-names = "cam_a_clkout", "cam_b_clkout";
 187                 ranges;
 188
 189                 fimc_0: fimc@11800000 {
 190                         compatible = "samsung,exynos4210-fimc";
 191                         reg = <0x11800000 0x1000>;
 192                         interrupts = <0 84 0>;
 193                         clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
 194                         clock-names = "fimc", "sclk_fimc";
 195                         power-domains = <&pd_cam>;
 196                         samsung,sysreg = <&sys_reg>;
 197                         iommus = <&sysmmu_fimc0>;
 198                         status = "disabled";
 199                 };
 200
 201                 fimc_1: fimc@11810000 {
 202                         compatible = "samsung,exynos4210-fimc";
 203                         reg = <0x11810000 0x1000>;
 204                         interrupts = <0 85 0>;
 205                         clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
 206                         clock-names = "fimc", "sclk_fimc";
 207                         power-domains = <&pd_cam>;
 208                         samsung,sysreg = <&sys_reg>;
 209                         iommus = <&sysmmu_fimc1>;
 210                         status = "disabled";
 211                 };
 212
 213                 fimc_2: fimc@11820000 {
 214                         compatible = "samsung,exynos4210-fimc";
 215                         reg = <0x11820000 0x1000>;
 216                         interrupts = <0 86 0>;
 217                         clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
 218                         clock-names = "fimc", "sclk_fimc";
 219                         power-domains = <&pd_cam>;
 220                         samsung,sysreg = <&sys_reg>;
 221                         iommus = <&sysmmu_fimc2>;
 222                         status = "disabled";
 223                 };
 224
 225                 fimc_3: fimc@11830000 {
 226                         compatible = "samsung,exynos4210-fimc";
 227                         reg = <0x11830000 0x1000>;
 228                         interrupts = <0 87 0>;
 229                         clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
 230                         clock-names = "fimc", "sclk_fimc";
 231                         power-domains = <&pd_cam>;
 232                         samsung,sysreg = <&sys_reg>;
 233                         iommus = <&sysmmu_fimc3>;
 234                         status = "disabled";
 235                 };
 236
 237                 csis_0: csis@11880000 {
 238                         compatible = "samsung,exynos4210-csis";
 239                         reg = <0x11880000 0x4000>;
 240                         interrupts = <0 78 0>;
 241                         clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
 242                         clock-names = "csis", "sclk_csis";
 243                         bus-width = <4>;
 244                         power-domains = <&pd_cam>;
 245                         phys = <&mipi_phy 0>;
 246                         phy-names = "csis";
 247                         status = "disabled";
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                 };
 251
 252                 csis_1: csis@11890000 {
 253                         compatible = "samsung,exynos4210-csis";
 254                         reg = <0x11890000 0x4000>;
 255                         interrupts = <0 80 0>;
 256                         clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
 257                         clock-names = "csis", "sclk_csis";
 258                         bus-width = <2>;
 259                         power-domains = <&pd_cam>;
 260                         phys = <&mipi_phy 2>;
 261                         phy-names = "csis";
 262                         status = "disabled";
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                 };
 266         };
 267
 268         watchdog: watchdog@10060000 {
 269                 compatible = "samsung,s3c2410-wdt";
 270                 reg = <0x10060000 0x100>;
 271                 interrupts = <0 43 0>;
 272                 clocks = <&clock CLK_WDT>;
 273                 clock-names = "watchdog";
 274                 status = "disabled";
 275         };
 276
 277         rtc: rtc@10070000 {
 278                 compatible = "samsung,s3c6410-rtc";
 279                 reg = <0x10070000 0x100>;
 280                 interrupt-parent = <&pmu_system_controller>;
 281                 interrupts = <0 44 0>, <0 45 0>;
 282                 clocks = <&clock CLK_RTC>;
 283                 clock-names = "rtc";
 284                 status = "disabled";
 285         };
 286
 287         keypad: keypad@100A0000 {
 288                 compatible = "samsung,s5pv210-keypad";
 289                 reg = <0x100A0000 0x100>;
 290                 interrupts = <0 109 0>;
 291                 clocks = <&clock CLK_KEYIF>;
 292                 clock-names = "keypad";
 293                 status = "disabled";
 294         };
 295
 296         sdhci_0: sdhci@12510000 {
 297                 compatible = "samsung,exynos4210-sdhci";
 298                 reg = <0x12510000 0x100>;
 299                 interrupts = <0 73 0>;
 300                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 301                 clock-names = "hsmmc", "mmc_busclk.2";
 302                 status = "disabled";
 303         };
 304
 305         sdhci_1: sdhci@12520000 {
 306                 compatible = "samsung,exynos4210-sdhci";
 307                 reg = <0x12520000 0x100>;
 308                 interrupts = <0 74 0>;
 309                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 310                 clock-names = "hsmmc", "mmc_busclk.2";
 311                 status = "disabled";
 312         };
 313
 314         sdhci_2: sdhci@12530000 {
 315                 compatible = "samsung,exynos4210-sdhci";
 316                 reg = <0x12530000 0x100>;
 317                 interrupts = <0 75 0>;
 318                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 319                 clock-names = "hsmmc", "mmc_busclk.2";
 320                 status = "disabled";
 321         };
 322
 323         sdhci_3: sdhci@12540000 {
 324                 compatible = "samsung,exynos4210-sdhci";
 325                 reg = <0x12540000 0x100>;
 326                 interrupts = <0 76 0>;
 327                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 328                 clock-names = "hsmmc", "mmc_busclk.2";
 329                 status = "disabled";
 330         };
 331
 332         exynos_usbphy: exynos-usbphy@125B0000 {
 333                 compatible = "samsung,exynos4210-usb2-phy";
 334                 reg = <0x125B0000 0x100>;
 335                 samsung,pmureg-phandle = <&pmu_system_controller>;
 336                 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
 337                 clock-names = "phy", "ref";
 338                 #phy-cells = <1>;
 339                 status = "disabled";
 340         };
 341
 342         hsotg: hsotg@12480000 {
 343                 compatible = "samsung,s3c6400-hsotg";
 344                 reg = <0x12480000 0x20000>;
 345                 interrupts = <0 71 0>;
 346                 clocks = <&clock CLK_USB_DEVICE>;
 347                 clock-names = "otg";
 348                 phys = <&exynos_usbphy 0>;
 349                 phy-names = "usb2-phy";
 350                 status = "disabled";
 351         };
 352
 353         ehci: ehci@12580000 {
 354                 compatible = "samsung,exynos4210-ehci";
 355                 reg = <0x12580000 0x100>;
 356                 interrupts = <0 70 0>;
 357                 clocks = <&clock CLK_USB_HOST>;
 358                 clock-names = "usbhost";
 359                 status = "disabled";
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 port@0 {
 363                     reg = <0>;
 364                     phys = <&exynos_usbphy 1>;
 365                     status = "disabled";
 366                 };
 367                 port@1 {
 368                     reg = <1>;
 369                     phys = <&exynos_usbphy 2>;
 370                     status = "disabled";
 371                 };
 372                 port@2 {
 373                     reg = <2>;
 374                     phys = <&exynos_usbphy 3>;
 375                     status = "disabled";
 376                 };
 377         };
 378
 379         ohci: ohci@12590000 {
 380                 compatible = "samsung,exynos4210-ohci";
 381                 reg = <0x12590000 0x100>;
 382                 interrupts = <0 70 0>;
 383                 clocks = <&clock CLK_USB_HOST>;
 384                 clock-names = "usbhost";
 385                 status = "disabled";
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 port@0 {
 389                     reg = <0>;
 390                     phys = <&exynos_usbphy 1>;
 391                     status = "disabled";
 392                 };
 393         };
 394
 395         i2s1: i2s@13960000 {
 396                 compatible = "samsung,s3c6410-i2s";
 397                 reg = <0x13960000 0x100>;
 398                 clocks = <&clock CLK_I2S1>;
 399                 clock-names = "iis";
 400                 #clock-cells = <1>;
 401                 clock-output-names = "i2s_cdclk1";
 402                 dmas = <&pdma1 12>, <&pdma1 11>;
 403                 dma-names = "tx", "rx";
 404                 #sound-dai-cells = <1>;
 405                 status = "disabled";
 406         };
 407
 408         i2s2: i2s@13970000 {
 409                 compatible = "samsung,s3c6410-i2s";
 410                 reg = <0x13970000 0x100>;
 411                 clocks = <&clock CLK_I2S2>;
 412                 clock-names = "iis";
 413                 #clock-cells = <1>;
 414                 clock-output-names = "i2s_cdclk2";
 415                 dmas = <&pdma0 14>, <&pdma0 13>;
 416                 dma-names = "tx", "rx";
 417                 #sound-dai-cells = <1>;
 418                 status = "disabled";
 419         };
 420
 421         mfc: codec@13400000 {
 422                 compatible = "samsung,mfc-v5";
 423                 reg = <0x13400000 0x10000>;
 424                 interrupts = <0 94 0>;
 425                 power-domains = <&pd_mfc>;
 426                 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
 427                 clock-names = "mfc", "sclk_mfc";
 428                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 429                 iommu-names = "left", "right";
 430                 status = "disabled";
 431         };
 432
 433         serial_0: serial@13800000 {
 434                 compatible = "samsung,exynos4210-uart";
 435                 reg = <0x13800000 0x100>;
 436                 interrupts = <0 52 0>;
 437                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 438                 clock-names = "uart", "clk_uart_baud0";
 439                 dmas = <&pdma0 15>, <&pdma0 16>;
 440                 dma-names = "rx", "tx";
 441                 status = "disabled";
 442         };
 443
 444         serial_1: serial@13810000 {
 445                 compatible = "samsung,exynos4210-uart";
 446                 reg = <0x13810000 0x100>;
 447                 interrupts = <0 53 0>;
 448                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 449                 clock-names = "uart", "clk_uart_baud0";
 450                 dmas = <&pdma1 15>, <&pdma1 16>;
 451                 dma-names = "rx", "tx";
 452                 status = "disabled";
 453         };
 454
 455         serial_2: serial@13820000 {
 456                 compatible = "samsung,exynos4210-uart";
 457                 reg = <0x13820000 0x100>;
 458                 interrupts = <0 54 0>;
 459                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 460                 clock-names = "uart", "clk_uart_baud0";
 461                 dmas = <&pdma0 17>, <&pdma0 18>;
 462                 dma-names = "rx", "tx";
 463                 status = "disabled";
 464         };
 465
 466         serial_3: serial@13830000 {
 467                 compatible = "samsung,exynos4210-uart";
 468                 reg = <0x13830000 0x100>;
 469                 interrupts = <0 55 0>;
 470                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 471                 clock-names = "uart", "clk_uart_baud0";
 472                 dmas = <&pdma1 17>, <&pdma1 18>;
 473                 dma-names = "rx", "tx";
 474                 status = "disabled";
 475         };
 476
 477         i2c_0: i2c@13860000 {
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 compatible = "samsung,s3c2440-i2c";
 481                 reg = <0x13860000 0x100>;
 482                 interrupts = <0 58 0>;
 483                 clocks = <&clock CLK_I2C0>;
 484                 clock-names = "i2c";
 485                 pinctrl-names = "default";
 486                 pinctrl-0 = <&i2c0_bus>;
 487                 status = "disabled";
 488         };
 489
 490         i2c_1: i2c@13870000 {
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 compatible = "samsung,s3c2440-i2c";
 494                 reg = <0x13870000 0x100>;
 495                 interrupts = <0 59 0>;
 496                 clocks = <&clock CLK_I2C1>;
 497                 clock-names = "i2c";
 498                 pinctrl-names = "default";
 499                 pinctrl-0 = <&i2c1_bus>;
 500                 status = "disabled";
 501         };
 502
 503         i2c_2: i2c@13880000 {
 504                 #address-cells = <1>;
 505                 #size-cells = <0>;
 506                 compatible = "samsung,s3c2440-i2c";
 507                 reg = <0x13880000 0x100>;
 508                 interrupts = <0 60 0>;
 509                 clocks = <&clock CLK_I2C2>;
 510                 clock-names = "i2c";
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&i2c2_bus>;
 513                 status = "disabled";
 514         };
 515
 516         i2c_3: i2c@13890000 {
 517                 #address-cells = <1>;
 518                 #size-cells = <0>;
 519                 compatible = "samsung,s3c2440-i2c";
 520                 reg = <0x13890000 0x100>;
 521                 interrupts = <0 61 0>;
 522                 clocks = <&clock CLK_I2C3>;
 523                 clock-names = "i2c";
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&i2c3_bus>;
 526                 status = "disabled";
 527         };
 528
 529         i2c_4: i2c@138A0000 {
 530                 #address-cells = <1>;
 531                 #size-cells = <0>;
 532                 compatible = "samsung,s3c2440-i2c";
 533                 reg = <0x138A0000 0x100>;
 534                 interrupts = <0 62 0>;
 535                 clocks = <&clock CLK_I2C4>;
 536                 clock-names = "i2c";
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c4_bus>;
 539                 status = "disabled";
 540         };
 541
 542         i2c_5: i2c@138B0000 {
 543                 #address-cells = <1>;
 544                 #size-cells = <0>;
 545                 compatible = "samsung,s3c2440-i2c";
 546                 reg = <0x138B0000 0x100>;
 547                 interrupts = <0 63 0>;
 548                 clocks = <&clock CLK_I2C5>;
 549                 clock-names = "i2c";
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c5_bus>;
 552                 status = "disabled";
 553         };
 554
 555         i2c_6: i2c@138C0000 {
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 compatible = "samsung,s3c2440-i2c";
 559                 reg = <0x138C0000 0x100>;
 560                 interrupts = <0 64 0>;
 561                 clocks = <&clock CLK_I2C6>;
 562                 clock-names = "i2c";
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&i2c6_bus>;
 565                 status = "disabled";
 566         };
 567
 568         i2c_7: i2c@138D0000 {
 569                 #address-cells = <1>;
 570                 #size-cells = <0>;
 571                 compatible = "samsung,s3c2440-i2c";
 572                 reg = <0x138D0000 0x100>;
 573                 interrupts = <0 65 0>;
 574                 clocks = <&clock CLK_I2C7>;
 575                 clock-names = "i2c";
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c7_bus>;
 578                 status = "disabled";
 579         };
 580
 581         i2c_8: i2c@138E0000 {
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 585                 reg = <0x138E0000 0x100>;
 586                 interrupts = <0 93 0>;
 587                 clocks = <&clock CLK_I2C_HDMI>;
 588                 clock-names = "i2c";
 589                 status = "disabled";
 590
 591                 hdmi_i2c_phy: hdmiphy@38 {
 592                         compatible = "exynos4210-hdmiphy";
 593                         reg = <0x38>;
 594                 };
 595         };
 596
 597         spi_0: spi@13920000 {
 598                 compatible = "samsung,exynos4210-spi";
 599                 reg = <0x13920000 0x100>;
 600                 interrupts = <0 66 0>;
 601                 dmas = <&pdma0 7>, <&pdma0 6>;
 602                 dma-names = "tx", "rx";
 603                 #address-cells = <1>;
 604                 #size-cells = <0>;
 605                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 606                 clock-names = "spi", "spi_busclk0";
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&spi0_bus>;
 609                 status = "disabled";
 610         };
 611
 612         spi_1: spi@13930000 {
 613                 compatible = "samsung,exynos4210-spi";
 614                 reg = <0x13930000 0x100>;
 615                 interrupts = <0 67 0>;
 616                 dmas = <&pdma1 7>, <&pdma1 6>;
 617                 dma-names = "tx", "rx";
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 621                 clock-names = "spi", "spi_busclk0";
 622                 pinctrl-names = "default";
 623                 pinctrl-0 = <&spi1_bus>;
 624                 status = "disabled";
 625         };
 626
 627         spi_2: spi@13940000 {
 628                 compatible = "samsung,exynos4210-spi";
 629                 reg = <0x13940000 0x100>;
 630                 interrupts = <0 68 0>;
 631                 dmas = <&pdma0 9>, <&pdma0 8>;
 632                 dma-names = "tx", "rx";
 633                 #address-cells = <1>;
 634                 #size-cells = <0>;
 635                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 636                 clock-names = "spi", "spi_busclk0";
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&spi2_bus>;
 639                 status = "disabled";
 640         };
 641
 642         pwm: pwm@139D0000 {
 643                 compatible = "samsung,exynos4210-pwm";
 644                 reg = <0x139D0000 0x1000>;
 645                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
 646                 clocks = <&clock CLK_PWM>;
 647                 clock-names = "timers";
 648                 #pwm-cells = <3>;
 649                 status = "disabled";
 650         };
 651
 652         amba {
 653                 #address-cells = <1>;
 654                 #size-cells = <1>;
 655                 compatible = "arm,amba-bus";
 656                 interrupt-parent = <&gic>;
 657                 ranges;
 658
 659                 pdma0: pdma@12680000 {
 660                         compatible = "arm,pl330", "arm,primecell";
 661                         reg = <0x12680000 0x1000>;
 662                         interrupts = <0 35 0>;
 663                         clocks = <&clock CLK_PDMA0>;
 664                         clock-names = "apb_pclk";
 665                         #dma-cells = <1>;
 666                         #dma-channels = <8>;
 667                         #dma-requests = <32>;
 668                 };
 669
 670                 pdma1: pdma@12690000 {
 671                         compatible = "arm,pl330", "arm,primecell";
 672                         reg = <0x12690000 0x1000>;
 673                         interrupts = <0 36 0>;
 674                         clocks = <&clock CLK_PDMA1>;
 675                         clock-names = "apb_pclk";
 676                         #dma-cells = <1>;
 677                         #dma-channels = <8>;
 678                         #dma-requests = <32>;
 679                 };
 680
 681                 mdma1: mdma@12850000 {
 682                         compatible = "arm,pl330", "arm,primecell";
 683                         reg = <0x12850000 0x1000>;
 684                         interrupts = <0 34 0>;
 685                         clocks = <&clock CLK_MDMA>;
 686                         clock-names = "apb_pclk";
 687                         #dma-cells = <1>;
 688                         #dma-channels = <8>;
 689                         #dma-requests = <1>;
 690                 };
 691         };
 692
 693         fimd: fimd@11c00000 {
 694                 compatible = "samsung,exynos4210-fimd";
 695                 interrupt-parent = <&combiner>;
 696                 reg = <0x11c00000 0x20000>;
 697                 interrupt-names = "fifo", "vsync", "lcd_sys";
 698                 interrupts = <11 0>, <11 1>, <11 2>;
 699                 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
 700                 clock-names = "sclk_fimd", "fimd";
 701                 power-domains = <&pd_lcd0>;
 702                 iommus = <&sysmmu_fimd0>;
 703                 samsung,sysreg = <&sys_reg>;
 704                 status = "disabled";
 705         };
 706
 707         tmu: tmu@100C0000 {
 708                 #include "exynos4412-tmu-sensor-conf.dtsi"
 709         };
 710
 711         jpeg_codec: jpeg-codec@11840000 {
 712                 compatible = "samsung,exynos4210-jpeg";
 713                 reg = <0x11840000 0x1000>;
 714                 interrupts = <0 88 0>;
 715                 clocks = <&clock CLK_JPEG>;
 716                 clock-names = "jpeg";
 717                 power-domains = <&pd_cam>;
 718                 iommus = <&sysmmu_jpeg>;
 719         };
 720
 721         hdmi: hdmi@12D00000 {
 722                 compatible = "samsung,exynos4210-hdmi";
 723                 reg = <0x12D00000 0x70000>;
 724                 interrupts = <0 92 0>;
 725                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
 726                         "mout_hdmi";
 727                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 728                         <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 729                         <&clock CLK_MOUT_HDMI>;
 730                 phy = <&hdmi_i2c_phy>;
 731                 power-domains = <&pd_tv>;
 732                 samsung,syscon-phandle = <&pmu_system_controller>;
 733                 status = "disabled";
 734         };
 735
 736         mixer: mixer@12C10000 {
 737                 compatible = "samsung,exynos4210-mixer";
 738                 interrupts = <0 91 0>;
 739                 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
 740                 power-domains = <&pd_tv>;
 741                 iommus = <&sysmmu_tv>;
 742                 status = "disabled";
 743         };
 744
 745         ppmu_dmc0: ppmu_dmc0@106a0000 {
 746                 compatible = "samsung,exynos-ppmu";
 747                 reg = <0x106a0000 0x2000>;
 748                 clocks = <&clock CLK_PPMUDMC0>;
 749                 clock-names = "ppmu";
 750                 status = "disabled";
 751         };
 752
 753         ppmu_dmc1: ppmu_dmc1@106b0000 {
 754                 compatible = "samsung,exynos-ppmu";
 755                 reg = <0x106b0000 0x2000>;
 756                 clocks = <&clock CLK_PPMUDMC1>;
 757                 clock-names = "ppmu";
 758                 status = "disabled";
 759         };
 760
 761         ppmu_cpu: ppmu_cpu@106c0000 {
 762                 compatible = "samsung,exynos-ppmu";
 763                 reg = <0x106c0000 0x2000>;
 764                 clocks = <&clock CLK_PPMUCPU>;
 765                 clock-names = "ppmu";
 766                 status = "disabled";
 767         };
 768
 769         ppmu_acp: ppmu_acp@10ae0000 {
 770                 compatible = "samsung,exynos-ppmu";
 771                 reg = <0x106e0000 0x2000>;
 772                 status = "disabled";
 773         };
 774
 775         ppmu_rightbus: ppmu_rightbus@112a0000 {
 776                 compatible = "samsung,exynos-ppmu";
 777                 reg = <0x112a0000 0x2000>;
 778                 clocks = <&clock CLK_PPMURIGHT>;
 779                 clock-names = "ppmu";
 780                 status = "disabled";
 781         };
 782
 783         ppmu_leftbus: ppmu_leftbus0@116a0000 {
 784                 compatible = "samsung,exynos-ppmu";
 785                 reg = <0x116a0000 0x2000>;
 786                 clocks = <&clock CLK_PPMULEFT>;
 787                 clock-names = "ppmu";
 788                 status = "disabled";
 789         };
 790
 791         ppmu_camif: ppmu_camif@11ac0000 {
 792                 compatible = "samsung,exynos-ppmu";
 793                 reg = <0x11ac0000 0x2000>;
 794                 clocks = <&clock CLK_PPMUCAMIF>;
 795                 clock-names = "ppmu";
 796                 status = "disabled";
 797         };
 798
 799         ppmu_lcd0: ppmu_lcd0@11e40000 {
 800                 compatible = "samsung,exynos-ppmu";
 801                 reg = <0x11e40000 0x2000>;
 802                 clocks = <&clock CLK_PPMULCD0>;
 803                 clock-names = "ppmu";
 804                 status = "disabled";
 805         };
 806
 807         ppmu_fsys: ppmu_g3d@12630000 {
 808                 compatible = "samsung,exynos-ppmu";
 809                 reg = <0x12630000 0x2000>;
 810                 status = "disabled";
 811         };
 812
 813         ppmu_image: ppmu_image@12aa0000 {
 814                 compatible = "samsung,exynos-ppmu";
 815                 reg = <0x12aa0000 0x2000>;
 816                 clocks = <&clock CLK_PPMUIMAGE>;
 817                 clock-names = "ppmu";
 818                 status = "disabled";
 819         };
 820
 821         ppmu_tv: ppmu_tv@12e40000 {
 822                 compatible = "samsung,exynos-ppmu";
 823                 reg = <0x12e40000 0x2000>;
 824                 clocks = <&clock CLK_PPMUTV>;
 825                 clock-names = "ppmu";
 826                 status = "disabled";
 827         };
 828
 829         ppmu_g3d: ppmu_g3d@13220000 {
 830                 compatible = "samsung,exynos-ppmu";
 831                 reg = <0x13220000 0x2000>;
 832                 clocks = <&clock CLK_PPMUG3D>;
 833                 clock-names = "ppmu";
 834                 status = "disabled";
 835         };
 836
 837         ppmu_mfc_left: ppmu_mfc_left@13660000 {
 838                 compatible = "samsung,exynos-ppmu";
 839                 reg = <0x13660000 0x2000>;
 840                 clocks = <&clock CLK_PPMUMFC_L>;
 841                 clock-names = "ppmu";
 842                 status = "disabled";
 843         };
 844
 845         ppmu_mfc_right: ppmu_mfc_right@13670000 {
 846                 compatible = "samsung,exynos-ppmu";
 847                 reg = <0x13670000 0x2000>;
 848                 clocks = <&clock CLK_PPMUMFC_R>;
 849                 clock-names = "ppmu";
 850                 status = "disabled";
 851         };
 852
 853         sysmmu_mfc_l: sysmmu@13620000 {
 854                 compatible = "samsung,exynos-sysmmu";
 855                 reg = <0x13620000 0x1000>;
 856                 interrupt-parent = <&combiner>;
 857                 interrupts = <5 5>;
 858                 clock-names = "sysmmu", "master";
 859                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 860                 power-domains = <&pd_mfc>;
 861                 #iommu-cells = <0>;
 862         };
 863
 864         sysmmu_mfc_r: sysmmu@13630000 {
 865                 compatible = "samsung,exynos-sysmmu";
 866                 reg = <0x13630000 0x1000>;
 867                 interrupt-parent = <&combiner>;
 868                 interrupts = <5 6>;
 869                 clock-names = "sysmmu", "master";
 870                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 871                 power-domains = <&pd_mfc>;
 872                 #iommu-cells = <0>;
 873         };
 874
 875         sysmmu_tv: sysmmu@12E20000 {
 876                 compatible = "samsung,exynos-sysmmu";
 877                 reg = <0x12E20000 0x1000>;
 878                 interrupt-parent = <&combiner>;
 879                 interrupts = <5 4>;
 880                 clock-names = "sysmmu", "master";
 881                 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 882                 power-domains = <&pd_tv>;
 883                 #iommu-cells = <0>;
 884         };
 885
 886         sysmmu_fimc0: sysmmu@11A20000 {
 887                 compatible = "samsung,exynos-sysmmu";
 888                 reg = <0x11A20000 0x1000>;
 889                 interrupt-parent = <&combiner>;
 890                 interrupts = <4 2>;
 891                 clock-names = "sysmmu", "master";
 892                 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
 893                 power-domains = <&pd_cam>;
 894                 #iommu-cells = <0>;
 895         };
 896
 897         sysmmu_fimc1: sysmmu@11A30000 {
 898                 compatible = "samsung,exynos-sysmmu";
 899                 reg = <0x11A30000 0x1000>;
 900                 interrupt-parent = <&combiner>;
 901                 interrupts = <4 3>;
 902                 clock-names = "sysmmu", "master";
 903                 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
 904                 power-domains = <&pd_cam>;
 905                 #iommu-cells = <0>;
 906         };
 907
 908         sysmmu_fimc2: sysmmu@11A40000 {
 909                 compatible = "samsung,exynos-sysmmu";
 910                 reg = <0x11A40000 0x1000>;
 911                 interrupt-parent = <&combiner>;
 912                 interrupts = <4 4>;
 913                 clock-names = "sysmmu", "master";
 914                 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
 915                 power-domains = <&pd_cam>;
 916                 #iommu-cells = <0>;
 917         };
 918
 919         sysmmu_fimc3: sysmmu@11A50000 {
 920                 compatible = "samsung,exynos-sysmmu";
 921                 reg = <0x11A50000 0x1000>;
 922                 interrupt-parent = <&combiner>;
 923                 interrupts = <4 5>;
 924                 clock-names = "sysmmu", "master";
 925                 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
 926                 power-domains = <&pd_cam>;
 927                 #iommu-cells = <0>;
 928         };
 929
 930         sysmmu_jpeg: sysmmu@11A60000 {
 931                 compatible = "samsung,exynos-sysmmu";
 932                 reg = <0x11A60000 0x1000>;
 933                 interrupt-parent = <&combiner>;
 934                 interrupts = <4 6>;
 935                 clock-names = "sysmmu", "master";
 936                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 937                 power-domains = <&pd_cam>;
 938                 #iommu-cells = <0>;
 939         };
 940
 941         sysmmu_rotator: sysmmu@12A30000 {
 942                 compatible = "samsung,exynos-sysmmu";
 943                 reg = <0x12A30000 0x1000>;
 944                 interrupt-parent = <&combiner>;
 945                 interrupts = <5 0>;
 946                 clock-names = "sysmmu", "master";
 947                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 948                 power-domains = <&pd_lcd0>;
 949                 #iommu-cells = <0>;
 950         };
 951
 952         sysmmu_fimd0: sysmmu@11E20000 {
 953                 compatible = "samsung,exynos-sysmmu";
 954                 reg = <0x11E20000 0x1000>;
 955                 interrupt-parent = <&combiner>;
 956                 interrupts = <5 2>;
 957                 clock-names = "sysmmu", "master";
 958                 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
 959                 power-domains = <&pd_lcd0>;
 960                 #iommu-cells = <0>;
 961         };
 962 };