arch/arm/boot/dts/exynos4.dtsi

   1 /*
   2  * Samsung's Exynos4 SoC series common device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
  10  * SoCs from Exynos4 series can include this file and provide values for SoCs
  11  * specfic bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <dt-bindings/clock/exynos4.h>
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24 #include "skeleton.dtsi"
  25
  26 / {
  27         interrupt-parent = <&gic>;
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 csis0 = &csis_0;
  43                 csis1 = &csis_1;
  44                 fimc0 = &fimc_0;
  45                 fimc1 = &fimc_1;
  46                 fimc2 = &fimc_2;
  47                 fimc3 = &fimc_3;
  48                 serial0 = &serial_0;
  49                 serial1 = &serial_1;
  50                 serial2 = &serial_2;
  51                 serial3 = &serial_3;
  52         };
  53
  54         clock_audss: clock-controller@03810000 {
  55                 compatible = "samsung,exynos4210-audss-clock";
  56                 reg = <0x03810000 0x0C>;
  57                 #clock-cells = <1>;
  58         };
  59
  60         i2s0: i2s@03830000 {
  61                 compatible = "samsung,s5pv210-i2s";
  62                 reg = <0x03830000 0x100>;
  63                 clocks = <&clock_audss EXYNOS_I2S_BUS>;
  64                 clock-names = "iis";
  65                 #clock-cells = <1>;
  66                 clock-output-names = "i2s_cdclk0";
  67                 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
  68                 dma-names = "tx", "rx", "tx-sec";
  69                 samsung,idma-addr = <0x03000000>;
  70                 #sound-dai-cells = <1>;
  71                 status = "disabled";
  72         };
  73
  74         chipid@10000000 {
  75                 compatible = "samsung,exynos4210-chipid";
  76                 reg = <0x10000000 0x100>;
  77         };
  78
  79         mipi_phy: video-phy@10020710 {
  80                 compatible = "samsung,s5pv210-mipi-video-phy";
  81                 #phy-cells = <1>;
  82                 syscon = <&pmu_system_controller>;
  83         };
  84
  85         pd_mfc: mfc-power-domain@10023C40 {
  86                 compatible = "samsung,exynos4210-pd";
  87                 reg = <0x10023C40 0x20>;
  88                 #power-domain-cells = <0>;
  89         };
  90
  91         pd_g3d: g3d-power-domain@10023C60 {
  92                 compatible = "samsung,exynos4210-pd";
  93                 reg = <0x10023C60 0x20>;
  94                 #power-domain-cells = <0>;
  95         };
  96
  97         pd_lcd0: lcd0-power-domain@10023C80 {
  98                 compatible = "samsung,exynos4210-pd";
  99                 reg = <0x10023C80 0x20>;
 100                 #power-domain-cells = <0>;
 101         };
 102
 103         pd_tv: tv-power-domain@10023C20 {
 104                 compatible = "samsung,exynos4210-pd";
 105                 reg = <0x10023C20 0x20>;
 106                 #power-domain-cells = <0>;
 107                 power-domains = <&pd_lcd0>;
 108         };
 109
 110         pd_cam: cam-power-domain@10023C00 {
 111                 compatible = "samsung,exynos4210-pd";
 112                 reg = <0x10023C00 0x20>;
 113                 #power-domain-cells = <0>;
 114         };
 115
 116         pd_gps: gps-power-domain@10023CE0 {
 117                 compatible = "samsung,exynos4210-pd";
 118                 reg = <0x10023CE0 0x20>;
 119                 #power-domain-cells = <0>;
 120         };
 121
 122         pd_gps_alive: gps-alive-power-domain@10023D00 {
 123                 compatible = "samsung,exynos4210-pd";
 124                 reg = <0x10023D00 0x20>;
 125                 #power-domain-cells = <0>;
 126         };
 127
 128         gic: interrupt-controller@10490000 {
 129                 compatible = "arm,cortex-a9-gic";
 130                 #interrupt-cells = <3>;
 131                 interrupt-controller;
 132                 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
 133         };
 134
 135         combiner: interrupt-controller@10440000 {
 136                 compatible = "samsung,exynos4210-combiner";
 137                 #interrupt-cells = <2>;
 138                 interrupt-controller;
 139                 reg = <0x10440000 0x1000>;
 140         };
 141
 142         pmu {
 143                 compatible = "arm,cortex-a9-pmu";
 144                 interrupt-parent = <&combiner>;
 145                 interrupts = <2 2>, <3 2>;
 146         };
 147
 148         sys_reg: syscon@10010000 {
 149                 compatible = "samsung,exynos4-sysreg", "syscon";
 150                 reg = <0x10010000 0x400>;
 151         };
 152
 153         pmu_system_controller: system-controller@10020000 {
 154                 compatible = "samsung,exynos4210-pmu", "syscon";
 155                 reg = <0x10020000 0x4000>;
 156                 interrupt-controller;
 157                 #interrupt-cells = <3>;
 158                 interrupt-parent = <&gic>;
 159         };
 160
 161         dsi_0: dsi@11C80000 {
 162                 compatible = "samsung,exynos4210-mipi-dsi";
 163                 reg = <0x11C80000 0x10000>;
 164                 interrupts = <0 79 0>;
 165                 power-domains = <&pd_lcd0>;
 166                 phys = <&mipi_phy 1>;
 167                 phy-names = "dsim";
 168                 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
 169                 clock-names = "bus_clk", "sclk_mipi";
 170                 status = "disabled";
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173         };
 174
 175         camera {
 176                 compatible = "samsung,fimc", "simple-bus";
 177                 status = "disabled";
 178                 #address-cells = <1>;
 179                 #size-cells = <1>;
 180                 #clock-cells = <1>;
 181                 clock-output-names = "cam_a_clkout", "cam_b_clkout";
 182                 ranges;
 183
 184                 fimc_0: fimc@11800000 {
 185                         compatible = "samsung,exynos4210-fimc";
 186                         reg = <0x11800000 0x1000>;
 187                         interrupts = <0 84 0>;
 188                         clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
 189                         clock-names = "fimc", "sclk_fimc";
 190                         power-domains = <&pd_cam>;
 191                         samsung,sysreg = <&sys_reg>;
 192                         iommus = <&sysmmu_fimc0>;
 193                         status = "disabled";
 194                 };
 195
 196                 fimc_1: fimc@11810000 {
 197                         compatible = "samsung,exynos4210-fimc";
 198                         reg = <0x11810000 0x1000>;
 199                         interrupts = <0 85 0>;
 200                         clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
 201                         clock-names = "fimc", "sclk_fimc";
 202                         power-domains = <&pd_cam>;
 203                         samsung,sysreg = <&sys_reg>;
 204                         iommus = <&sysmmu_fimc1>;
 205                         status = "disabled";
 206                 };
 207
 208                 fimc_2: fimc@11820000 {
 209                         compatible = "samsung,exynos4210-fimc";
 210                         reg = <0x11820000 0x1000>;
 211                         interrupts = <0 86 0>;
 212                         clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
 213                         clock-names = "fimc", "sclk_fimc";
 214                         power-domains = <&pd_cam>;
 215                         samsung,sysreg = <&sys_reg>;
 216                         iommus = <&sysmmu_fimc2>;
 217                         status = "disabled";
 218                 };
 219
 220                 fimc_3: fimc@11830000 {
 221                         compatible = "samsung,exynos4210-fimc";
 222                         reg = <0x11830000 0x1000>;
 223                         interrupts = <0 87 0>;
 224                         clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
 225                         clock-names = "fimc", "sclk_fimc";
 226                         power-domains = <&pd_cam>;
 227                         samsung,sysreg = <&sys_reg>;
 228                         iommus = <&sysmmu_fimc3>;
 229                         status = "disabled";
 230                 };
 231
 232                 csis_0: csis@11880000 {
 233                         compatible = "samsung,exynos4210-csis";
 234                         reg = <0x11880000 0x4000>;
 235                         interrupts = <0 78 0>;
 236                         clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
 237                         clock-names = "csis", "sclk_csis";
 238                         bus-width = <4>;
 239                         power-domains = <&pd_cam>;
 240                         phys = <&mipi_phy 0>;
 241                         phy-names = "csis";
 242                         status = "disabled";
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                 };
 246
 247                 csis_1: csis@11890000 {
 248                         compatible = "samsung,exynos4210-csis";
 249                         reg = <0x11890000 0x4000>;
 250                         interrupts = <0 80 0>;
 251                         clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
 252                         clock-names = "csis", "sclk_csis";
 253                         bus-width = <2>;
 254                         power-domains = <&pd_cam>;
 255                         phys = <&mipi_phy 2>;
 256                         phy-names = "csis";
 257                         status = "disabled";
 258                         #address-cells = <1>;
 259                         #size-cells = <0>;
 260                 };
 261         };
 262
 263         watchdog: watchdog@10060000 {
 264                 compatible = "samsung,s3c2410-wdt";
 265                 reg = <0x10060000 0x100>;
 266                 interrupts = <0 43 0>;
 267                 clocks = <&clock CLK_WDT>;
 268                 clock-names = "watchdog";
 269                 status = "disabled";
 270         };
 271
 272         rtc: rtc@10070000 {
 273                 compatible = "samsung,s3c6410-rtc";
 274                 reg = <0x10070000 0x100>;
 275                 interrupt-parent = <&pmu_system_controller>;
 276                 interrupts = <0 44 0>, <0 45 0>;
 277                 clocks = <&clock CLK_RTC>;
 278                 clock-names = "rtc";
 279                 status = "disabled";
 280         };
 281
 282         keypad: keypad@100A0000 {
 283                 compatible = "samsung,s5pv210-keypad";
 284                 reg = <0x100A0000 0x100>;
 285                 interrupts = <0 109 0>;
 286                 clocks = <&clock CLK_KEYIF>;
 287                 clock-names = "keypad";
 288                 status = "disabled";
 289         };
 290
 291         sdhci_0: sdhci@12510000 {
 292                 compatible = "samsung,exynos4210-sdhci";
 293                 reg = <0x12510000 0x100>;
 294                 interrupts = <0 73 0>;
 295                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 296                 clock-names = "hsmmc", "mmc_busclk.2";
 297                 status = "disabled";
 298         };
 299
 300         sdhci_1: sdhci@12520000 {
 301                 compatible = "samsung,exynos4210-sdhci";
 302                 reg = <0x12520000 0x100>;
 303                 interrupts = <0 74 0>;
 304                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 305                 clock-names = "hsmmc", "mmc_busclk.2";
 306                 status = "disabled";
 307         };
 308
 309         sdhci_2: sdhci@12530000 {
 310                 compatible = "samsung,exynos4210-sdhci";
 311                 reg = <0x12530000 0x100>;
 312                 interrupts = <0 75 0>;
 313                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 314                 clock-names = "hsmmc", "mmc_busclk.2";
 315                 status = "disabled";
 316         };
 317
 318         sdhci_3: sdhci@12540000 {
 319                 compatible = "samsung,exynos4210-sdhci";
 320                 reg = <0x12540000 0x100>;
 321                 interrupts = <0 76 0>;
 322                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 323                 clock-names = "hsmmc", "mmc_busclk.2";
 324                 status = "disabled";
 325         };
 326
 327         exynos_usbphy: exynos-usbphy@125B0000 {
 328                 compatible = "samsung,exynos4210-usb2-phy";
 329                 reg = <0x125B0000 0x100>;
 330                 samsung,pmureg-phandle = <&pmu_system_controller>;
 331                 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
 332                 clock-names = "phy", "ref";
 333                 #phy-cells = <1>;
 334                 status = "disabled";
 335         };
 336
 337         hsotg: hsotg@12480000 {
 338                 compatible = "samsung,s3c6400-hsotg";
 339                 reg = <0x12480000 0x20000>;
 340                 interrupts = <0 71 0>;
 341                 clocks = <&clock CLK_USB_DEVICE>;
 342                 clock-names = "otg";
 343                 phys = <&exynos_usbphy 0>;
 344                 phy-names = "usb2-phy";
 345                 status = "disabled";
 346         };
 347
 348         ehci: ehci@12580000 {
 349                 compatible = "samsung,exynos4210-ehci";
 350                 reg = <0x12580000 0x100>;
 351                 interrupts = <0 70 0>;
 352                 clocks = <&clock CLK_USB_HOST>;
 353                 clock-names = "usbhost";
 354                 status = "disabled";
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 port@0 {
 358                     reg = <0>;
 359                     phys = <&exynos_usbphy 1>;
 360                     status = "disabled";
 361                 };
 362                 port@1 {
 363                     reg = <1>;
 364                     phys = <&exynos_usbphy 2>;
 365                     status = "disabled";
 366                 };
 367                 port@2 {
 368                     reg = <2>;
 369                     phys = <&exynos_usbphy 3>;
 370                     status = "disabled";
 371                 };
 372         };
 373
 374         ohci: ohci@12590000 {
 375                 compatible = "samsung,exynos4210-ohci";
 376                 reg = <0x12590000 0x100>;
 377                 interrupts = <0 70 0>;
 378                 clocks = <&clock CLK_USB_HOST>;
 379                 clock-names = "usbhost";
 380                 status = "disabled";
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 port@0 {
 384                     reg = <0>;
 385                     phys = <&exynos_usbphy 1>;
 386                     status = "disabled";
 387                 };
 388         };
 389
 390         i2s1: i2s@13960000 {
 391                 compatible = "samsung,s3c6410-i2s";
 392                 reg = <0x13960000 0x100>;
 393                 clocks = <&clock CLK_I2S1>;
 394                 clock-names = "iis";
 395                 #clock-cells = <1>;
 396                 clock-output-names = "i2s_cdclk1";
 397                 dmas = <&pdma1 12>, <&pdma1 11>;
 398                 dma-names = "tx", "rx";
 399                 #sound-dai-cells = <1>;
 400                 status = "disabled";
 401         };
 402
 403         i2s2: i2s@13970000 {
 404                 compatible = "samsung,s3c6410-i2s";
 405                 reg = <0x13970000 0x100>;
 406                 clocks = <&clock CLK_I2S2>;
 407                 clock-names = "iis";
 408                 #clock-cells = <1>;
 409                 clock-output-names = "i2s_cdclk2";
 410                 dmas = <&pdma0 14>, <&pdma0 13>;
 411                 dma-names = "tx", "rx";
 412                 #sound-dai-cells = <1>;
 413                 status = "disabled";
 414         };
 415
 416         mfc: codec@13400000 {
 417                 compatible = "samsung,mfc-v5";
 418                 reg = <0x13400000 0x10000>;
 419                 interrupts = <0 94 0>;
 420                 power-domains = <&pd_mfc>;
 421                 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
 422                 clock-names = "mfc", "sclk_mfc";
 423                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 424                 iommu-names = "left", "right";
 425                 status = "disabled";
 426         };
 427
 428         serial_0: serial@13800000 {
 429                 compatible = "samsung,exynos4210-uart";
 430                 reg = <0x13800000 0x100>;
 431                 interrupts = <0 52 0>;
 432                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 433                 clock-names = "uart", "clk_uart_baud0";
 434                 dmas = <&pdma0 15>, <&pdma0 16>;
 435                 dma-names = "rx", "tx";
 436                 status = "disabled";
 437         };
 438
 439         serial_1: serial@13810000 {
 440                 compatible = "samsung,exynos4210-uart";
 441                 reg = <0x13810000 0x100>;
 442                 interrupts = <0 53 0>;
 443                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 444                 clock-names = "uart", "clk_uart_baud0";
 445                 dmas = <&pdma1 15>, <&pdma1 16>;
 446                 dma-names = "rx", "tx";
 447                 status = "disabled";
 448         };
 449
 450         serial_2: serial@13820000 {
 451                 compatible = "samsung,exynos4210-uart";
 452                 reg = <0x13820000 0x100>;
 453                 interrupts = <0 54 0>;
 454                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 455                 clock-names = "uart", "clk_uart_baud0";
 456                 dmas = <&pdma0 17>, <&pdma0 18>;
 457                 dma-names = "rx", "tx";
 458                 status = "disabled";
 459         };
 460
 461         serial_3: serial@13830000 {
 462                 compatible = "samsung,exynos4210-uart";
 463                 reg = <0x13830000 0x100>;
 464                 interrupts = <0 55 0>;
 465                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 466                 clock-names = "uart", "clk_uart_baud0";
 467                 dmas = <&pdma1 17>, <&pdma1 18>;
 468                 dma-names = "rx", "tx";
 469                 status = "disabled";
 470         };
 471
 472         i2c_0: i2c@13860000 {
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 compatible = "samsung,s3c2440-i2c";
 476                 reg = <0x13860000 0x100>;
 477                 interrupts = <0 58 0>;
 478                 clocks = <&clock CLK_I2C0>;
 479                 clock-names = "i2c";
 480                 pinctrl-names = "default";
 481                 pinctrl-0 = <&i2c0_bus>;
 482                 status = "disabled";
 483         };
 484
 485         i2c_1: i2c@13870000 {
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 compatible = "samsung,s3c2440-i2c";
 489                 reg = <0x13870000 0x100>;
 490                 interrupts = <0 59 0>;
 491                 clocks = <&clock CLK_I2C1>;
 492                 clock-names = "i2c";
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&i2c1_bus>;
 495                 status = "disabled";
 496         };
 497
 498         i2c_2: i2c@13880000 {
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 compatible = "samsung,s3c2440-i2c";
 502                 reg = <0x13880000 0x100>;
 503                 interrupts = <0 60 0>;
 504                 clocks = <&clock CLK_I2C2>;
 505                 clock-names = "i2c";
 506                 pinctrl-names = "default";
 507                 pinctrl-0 = <&i2c2_bus>;
 508                 status = "disabled";
 509         };
 510
 511         i2c_3: i2c@13890000 {
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 compatible = "samsung,s3c2440-i2c";
 515                 reg = <0x13890000 0x100>;
 516                 interrupts = <0 61 0>;
 517                 clocks = <&clock CLK_I2C3>;
 518                 clock-names = "i2c";
 519                 pinctrl-names = "default";
 520                 pinctrl-0 = <&i2c3_bus>;
 521                 status = "disabled";
 522         };
 523
 524         i2c_4: i2c@138A0000 {
 525                 #address-cells = <1>;
 526                 #size-cells = <0>;
 527                 compatible = "samsung,s3c2440-i2c";
 528                 reg = <0x138A0000 0x100>;
 529                 interrupts = <0 62 0>;
 530                 clocks = <&clock CLK_I2C4>;
 531                 clock-names = "i2c";
 532                 pinctrl-names = "default";
 533                 pinctrl-0 = <&i2c4_bus>;
 534                 status = "disabled";
 535         };
 536
 537         i2c_5: i2c@138B0000 {
 538                 #address-cells = <1>;
 539                 #size-cells = <0>;
 540                 compatible = "samsung,s3c2440-i2c";
 541                 reg = <0x138B0000 0x100>;
 542                 interrupts = <0 63 0>;
 543                 clocks = <&clock CLK_I2C5>;
 544                 clock-names = "i2c";
 545                 pinctrl-names = "default";
 546                 pinctrl-0 = <&i2c5_bus>;
 547                 status = "disabled";
 548         };
 549
 550         i2c_6: i2c@138C0000 {
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 compatible = "samsung,s3c2440-i2c";
 554                 reg = <0x138C0000 0x100>;
 555                 interrupts = <0 64 0>;
 556                 clocks = <&clock CLK_I2C6>;
 557                 clock-names = "i2c";
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&i2c6_bus>;
 560                 status = "disabled";
 561         };
 562
 563         i2c_7: i2c@138D0000 {
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 compatible = "samsung,s3c2440-i2c";
 567                 reg = <0x138D0000 0x100>;
 568                 interrupts = <0 65 0>;
 569                 clocks = <&clock CLK_I2C7>;
 570                 clock-names = "i2c";
 571                 pinctrl-names = "default";
 572                 pinctrl-0 = <&i2c7_bus>;
 573                 status = "disabled";
 574         };
 575
 576         i2c_8: i2c@138E0000 {
 577                 #address-cells = <1>;
 578                 #size-cells = <0>;
 579                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 580                 reg = <0x138E0000 0x100>;
 581                 interrupts = <0 93 0>;
 582                 clocks = <&clock CLK_I2C_HDMI>;
 583                 clock-names = "i2c";
 584                 status = "disabled";
 585
 586                 hdmi_i2c_phy: hdmiphy@38 {
 587                         compatible = "exynos4210-hdmiphy";
 588                         reg = <0x38>;
 589                 };
 590         };
 591
 592         spi_0: spi@13920000 {
 593                 compatible = "samsung,exynos4210-spi";
 594                 reg = <0x13920000 0x100>;
 595                 interrupts = <0 66 0>;
 596                 dmas = <&pdma0 7>, <&pdma0 6>;
 597                 dma-names = "tx", "rx";
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 601                 clock-names = "spi", "spi_busclk0";
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&spi0_bus>;
 604                 status = "disabled";
 605         };
 606
 607         spi_1: spi@13930000 {
 608                 compatible = "samsung,exynos4210-spi";
 609                 reg = <0x13930000 0x100>;
 610                 interrupts = <0 67 0>;
 611                 dmas = <&pdma1 7>, <&pdma1 6>;
 612                 dma-names = "tx", "rx";
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 616                 clock-names = "spi", "spi_busclk0";
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&spi1_bus>;
 619                 status = "disabled";
 620         };
 621
 622         spi_2: spi@13940000 {
 623                 compatible = "samsung,exynos4210-spi";
 624                 reg = <0x13940000 0x100>;
 625                 interrupts = <0 68 0>;
 626                 dmas = <&pdma0 9>, <&pdma0 8>;
 627                 dma-names = "tx", "rx";
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 631                 clock-names = "spi", "spi_busclk0";
 632                 pinctrl-names = "default";
 633                 pinctrl-0 = <&spi2_bus>;
 634                 status = "disabled";
 635         };
 636
 637         pwm: pwm@139D0000 {
 638                 compatible = "samsung,exynos4210-pwm";
 639                 reg = <0x139D0000 0x1000>;
 640                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
 641                 clocks = <&clock CLK_PWM>;
 642                 clock-names = "timers";
 643                 #pwm-cells = <3>;
 644                 status = "disabled";
 645         };
 646
 647         amba {
 648                 #address-cells = <1>;
 649                 #size-cells = <1>;
 650                 compatible = "arm,amba-bus";
 651                 interrupt-parent = <&gic>;
 652                 ranges;
 653
 654                 pdma0: pdma@12680000 {
 655                         compatible = "arm,pl330", "arm,primecell";
 656                         reg = <0x12680000 0x1000>;
 657                         interrupts = <0 35 0>;
 658                         clocks = <&clock CLK_PDMA0>;
 659                         clock-names = "apb_pclk";
 660                         #dma-cells = <1>;
 661                         #dma-channels = <8>;
 662                         #dma-requests = <32>;
 663                 };
 664
 665                 pdma1: pdma@12690000 {
 666                         compatible = "arm,pl330", "arm,primecell";
 667                         reg = <0x12690000 0x1000>;
 668                         interrupts = <0 36 0>;
 669                         clocks = <&clock CLK_PDMA1>;
 670                         clock-names = "apb_pclk";
 671                         #dma-cells = <1>;
 672                         #dma-channels = <8>;
 673                         #dma-requests = <32>;
 674                 };
 675
 676                 mdma1: mdma@12850000 {
 677                         compatible = "arm,pl330", "arm,primecell";
 678                         reg = <0x12850000 0x1000>;
 679                         interrupts = <0 34 0>;
 680                         clocks = <&clock CLK_MDMA>;
 681                         clock-names = "apb_pclk";
 682                         #dma-cells = <1>;
 683                         #dma-channels = <8>;
 684                         #dma-requests = <1>;
 685                 };
 686         };
 687
 688         fimd: fimd@11c00000 {
 689                 compatible = "samsung,exynos4210-fimd";
 690                 interrupt-parent = <&combiner>;
 691                 reg = <0x11c00000 0x20000>;
 692                 interrupt-names = "fifo", "vsync", "lcd_sys";
 693                 interrupts = <11 0>, <11 1>, <11 2>;
 694                 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
 695                 clock-names = "sclk_fimd", "fimd";
 696                 power-domains = <&pd_lcd0>;
 697                 iommus = <&sysmmu_fimd0>;
 698                 samsung,sysreg = <&sys_reg>;
 699                 status = "disabled";
 700         };
 701
 702         tmu: tmu@100C0000 {
 703                 #include "exynos4412-tmu-sensor-conf.dtsi"
 704         };
 705
 706         jpeg_codec: jpeg-codec@11840000 {
 707                 compatible = "samsung,exynos4210-jpeg";
 708                 reg = <0x11840000 0x1000>;
 709                 interrupts = <0 88 0>;
 710                 clocks = <&clock CLK_JPEG>;
 711                 clock-names = "jpeg";
 712                 power-domains = <&pd_cam>;
 713                 iommus = <&sysmmu_jpeg>;
 714         };
 715
 716         hdmi: hdmi@12D00000 {
 717                 compatible = "samsung,exynos4210-hdmi";
 718                 reg = <0x12D00000 0x70000>;
 719                 interrupts = <0 92 0>;
 720                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
 721                         "mout_hdmi";
 722                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 723                         <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 724                         <&clock CLK_MOUT_HDMI>;
 725                 phy = <&hdmi_i2c_phy>;
 726                 power-domains = <&pd_tv>;
 727                 samsung,syscon-phandle = <&pmu_system_controller>;
 728                 status = "disabled";
 729         };
 730
 731         mixer: mixer@12C10000 {
 732                 compatible = "samsung,exynos4210-mixer";
 733                 interrupts = <0 91 0>;
 734                 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
 735                 power-domains = <&pd_tv>;
 736                 iommus = <&sysmmu_tv>;
 737                 status = "disabled";
 738         };
 739
 740         ppmu_dmc0: ppmu_dmc0@106a0000 {
 741                 compatible = "samsung,exynos-ppmu";
 742                 reg = <0x106a0000 0x2000>;
 743                 clocks = <&clock CLK_PPMUDMC0>;
 744                 clock-names = "ppmu";
 745                 status = "disabled";
 746         };
 747
 748         ppmu_dmc1: ppmu_dmc1@106b0000 {
 749                 compatible = "samsung,exynos-ppmu";
 750                 reg = <0x106b0000 0x2000>;
 751                 clocks = <&clock CLK_PPMUDMC1>;
 752                 clock-names = "ppmu";
 753                 status = "disabled";
 754         };
 755
 756         ppmu_cpu: ppmu_cpu@106c0000 {
 757                 compatible = "samsung,exynos-ppmu";
 758                 reg = <0x106c0000 0x2000>;
 759                 clocks = <&clock CLK_PPMUCPU>;
 760                 clock-names = "ppmu";
 761                 status = "disabled";
 762         };
 763
 764         ppmu_acp: ppmu_acp@10ae0000 {
 765                 compatible = "samsung,exynos-ppmu";
 766                 reg = <0x106e0000 0x2000>;
 767                 status = "disabled";
 768         };
 769
 770         ppmu_rightbus: ppmu_rightbus@112a0000 {
 771                 compatible = "samsung,exynos-ppmu";
 772                 reg = <0x112a0000 0x2000>;
 773                 clocks = <&clock CLK_PPMURIGHT>;
 774                 clock-names = "ppmu";
 775                 status = "disabled";
 776         };
 777
 778         ppmu_leftbus: ppmu_leftbus0@116a0000 {
 779                 compatible = "samsung,exynos-ppmu";
 780                 reg = <0x116a0000 0x2000>;
 781                 clocks = <&clock CLK_PPMULEFT>;
 782                 clock-names = "ppmu";
 783                 status = "disabled";
 784         };
 785
 786         ppmu_camif: ppmu_camif@11ac0000 {
 787                 compatible = "samsung,exynos-ppmu";
 788                 reg = <0x11ac0000 0x2000>;
 789                 clocks = <&clock CLK_PPMUCAMIF>;
 790                 clock-names = "ppmu";
 791                 status = "disabled";
 792         };
 793
 794         ppmu_lcd0: ppmu_lcd0@11e40000 {
 795                 compatible = "samsung,exynos-ppmu";
 796                 reg = <0x11e40000 0x2000>;
 797                 clocks = <&clock CLK_PPMULCD0>;
 798                 clock-names = "ppmu";
 799                 status = "disabled";
 800         };
 801
 802         ppmu_fsys: ppmu_g3d@12630000 {
 803                 compatible = "samsung,exynos-ppmu";
 804                 reg = <0x12630000 0x2000>;
 805                 status = "disabled";
 806         };
 807
 808         ppmu_image: ppmu_image@12aa0000 {
 809                 compatible = "samsung,exynos-ppmu";
 810                 reg = <0x12aa0000 0x2000>;
 811                 clocks = <&clock CLK_PPMUIMAGE>;
 812                 clock-names = "ppmu";
 813                 status = "disabled";
 814         };
 815
 816         ppmu_tv: ppmu_tv@12e40000 {
 817                 compatible = "samsung,exynos-ppmu";
 818                 reg = <0x12e40000 0x2000>;
 819                 clocks = <&clock CLK_PPMUTV>;
 820                 clock-names = "ppmu";
 821                 status = "disabled";
 822         };
 823
 824         ppmu_g3d: ppmu_g3d@13220000 {
 825                 compatible = "samsung,exynos-ppmu";
 826                 reg = <0x13220000 0x2000>;
 827                 clocks = <&clock CLK_PPMUG3D>;
 828                 clock-names = "ppmu";
 829                 status = "disabled";
 830         };
 831
 832         ppmu_mfc_left: ppmu_mfc_left@13660000 {
 833                 compatible = "samsung,exynos-ppmu";
 834                 reg = <0x13660000 0x2000>;
 835                 clocks = <&clock CLK_PPMUMFC_L>;
 836                 clock-names = "ppmu";
 837                 status = "disabled";
 838         };
 839
 840         ppmu_mfc_right: ppmu_mfc_right@13670000 {
 841                 compatible = "samsung,exynos-ppmu";
 842                 reg = <0x13670000 0x2000>;
 843                 clocks = <&clock CLK_PPMUMFC_R>;
 844                 clock-names = "ppmu";
 845                 status = "disabled";
 846         };
 847
 848         sysmmu_mfc_l: sysmmu@13620000 {
 849                 compatible = "samsung,exynos-sysmmu";
 850                 reg = <0x13620000 0x1000>;
 851                 interrupt-parent = <&combiner>;
 852                 interrupts = <5 5>;
 853                 clock-names = "sysmmu", "master";
 854                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 855                 power-domains = <&pd_mfc>;
 856                 #iommu-cells = <0>;
 857         };
 858
 859         sysmmu_mfc_r: sysmmu@13630000 {
 860                 compatible = "samsung,exynos-sysmmu";
 861                 reg = <0x13630000 0x1000>;
 862                 interrupt-parent = <&combiner>;
 863                 interrupts = <5 6>;
 864                 clock-names = "sysmmu", "master";
 865                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 866                 power-domains = <&pd_mfc>;
 867                 #iommu-cells = <0>;
 868         };
 869
 870         sysmmu_tv: sysmmu@12E20000 {
 871                 compatible = "samsung,exynos-sysmmu";
 872                 reg = <0x12E20000 0x1000>;
 873                 interrupt-parent = <&combiner>;
 874                 interrupts = <5 4>;
 875                 clock-names = "sysmmu", "master";
 876                 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 877                 power-domains = <&pd_tv>;
 878                 #iommu-cells = <0>;
 879         };
 880
 881         sysmmu_fimc0: sysmmu@11A20000 {
 882                 compatible = "samsung,exynos-sysmmu";
 883                 reg = <0x11A20000 0x1000>;
 884                 interrupt-parent = <&combiner>;
 885                 interrupts = <4 2>;
 886                 clock-names = "sysmmu", "master";
 887                 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
 888                 power-domains = <&pd_cam>;
 889                 #iommu-cells = <0>;
 890         };
 891
 892         sysmmu_fimc1: sysmmu@11A30000 {
 893                 compatible = "samsung,exynos-sysmmu";
 894                 reg = <0x11A30000 0x1000>;
 895                 interrupt-parent = <&combiner>;
 896                 interrupts = <4 3>;
 897                 clock-names = "sysmmu", "master";
 898                 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
 899                 power-domains = <&pd_cam>;
 900                 #iommu-cells = <0>;
 901         };
 902
 903         sysmmu_fimc2: sysmmu@11A40000 {
 904                 compatible = "samsung,exynos-sysmmu";
 905                 reg = <0x11A40000 0x1000>;
 906                 interrupt-parent = <&combiner>;
 907                 interrupts = <4 4>;
 908                 clock-names = "sysmmu", "master";
 909                 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
 910                 power-domains = <&pd_cam>;
 911                 #iommu-cells = <0>;
 912         };
 913
 914         sysmmu_fimc3: sysmmu@11A50000 {
 915                 compatible = "samsung,exynos-sysmmu";
 916                 reg = <0x11A50000 0x1000>;
 917                 interrupt-parent = <&combiner>;
 918                 interrupts = <4 5>;
 919                 clock-names = "sysmmu", "master";
 920                 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
 921                 power-domains = <&pd_cam>;
 922                 #iommu-cells = <0>;
 923         };
 924
 925         sysmmu_jpeg: sysmmu@11A60000 {
 926                 compatible = "samsung,exynos-sysmmu";
 927                 reg = <0x11A60000 0x1000>;
 928                 interrupt-parent = <&combiner>;
 929                 interrupts = <4 6>;
 930                 clock-names = "sysmmu", "master";
 931                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 932                 power-domains = <&pd_cam>;
 933                 #iommu-cells = <0>;
 934         };
 935
 936         sysmmu_rotator: sysmmu@12A30000 {
 937                 compatible = "samsung,exynos-sysmmu";
 938                 reg = <0x12A30000 0x1000>;
 939                 interrupt-parent = <&combiner>;
 940                 interrupts = <5 0>;
 941                 clock-names = "sysmmu", "master";
 942                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 943                 power-domains = <&pd_lcd0>;
 944                 #iommu-cells = <0>;
 945         };
 946
 947         sysmmu_fimd0: sysmmu@11E20000 {
 948                 compatible = "samsung,exynos-sysmmu";
 949                 reg = <0x11E20000 0x1000>;
 950                 interrupt-parent = <&combiner>;
 951                 interrupts = <5 2>;
 952                 clock-names = "sysmmu", "master";
 953                 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
 954                 power-domains = <&pd_lcd0>;
 955                 #iommu-cells = <0>;
 956         };
 957 };