arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18
  19 #include <dt-bindings/clock/exynos-audss-clk.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420", "samsung,exynos5";
  23
  24         aliases {
  25                 mshc0 = &mmc_0;
  26                 mshc1 = &mmc_1;
  27                 mshc2 = &mmc_2;
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 pinctrl4 = &pinctrl_4;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &hsi2c_4;
  38                 i2c5 = &hsi2c_5;
  39                 i2c6 = &hsi2c_6;
  40                 i2c7 = &hsi2c_7;
  41                 i2c8 = &hsi2c_8;
  42                 i2c9 = &hsi2c_9;
  43                 i2c10 = &hsi2c_10;
  44                 gsc0 = &gsc_0;
  45                 gsc1 = &gsc_1;
  46                 spi0 = &spi_0;
  47                 spi1 = &spi_1;
  48                 spi2 = &spi_2;
  49                 usbdrdphy0 = &usbdrd_phy0;
  50                 usbdrdphy1 = &usbdrd_phy1;
  51         };
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a15";
  60                         reg = <0x0>;
  61                         clock-frequency = <1800000000>;
  62                         cci-control-port = <&cci_control1>;
  63                 };
  64
  65                 cpu1: cpu@1 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a15";
  68                         reg = <0x1>;
  69                         clock-frequency = <1800000000>;
  70                         cci-control-port = <&cci_control1>;
  71                 };
  72
  73                 cpu2: cpu@2 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a15";
  76                         reg = <0x2>;
  77                         clock-frequency = <1800000000>;
  78                         cci-control-port = <&cci_control1>;
  79                 };
  80
  81                 cpu3: cpu@3 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a15";
  84                         reg = <0x3>;
  85                         clock-frequency = <1800000000>;
  86                         cci-control-port = <&cci_control1>;
  87                 };
  88
  89                 cpu4: cpu@100 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a7";
  92                         reg = <0x100>;
  93                         clock-frequency = <1000000000>;
  94                         cci-control-port = <&cci_control0>;
  95                 };
  96
  97                 cpu5: cpu@101 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a7";
 100                         reg = <0x101>;
 101                         clock-frequency = <1000000000>;
 102                         cci-control-port = <&cci_control0>;
 103                 };
 104
 105                 cpu6: cpu@102 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a7";
 108                         reg = <0x102>;
 109                         clock-frequency = <1000000000>;
 110                         cci-control-port = <&cci_control0>;
 111                 };
 112
 113                 cpu7: cpu@103 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a7";
 116                         reg = <0x103>;
 117                         clock-frequency = <1000000000>;
 118                         cci-control-port = <&cci_control0>;
 119                 };
 120         };
 121
 122         cci: cci@10d20000 {
 123                 compatible = "arm,cci-400";
 124                 #address-cells = <1>;
 125                 #size-cells = <1>;
 126                 reg = <0x10d20000 0x1000>;
 127                 ranges = <0x0 0x10d20000 0x6000>;
 128
 129                 cci_control0: slave-if@4000 {
 130                         compatible = "arm,cci-400-ctrl-if";
 131                         interface-type = "ace";
 132                         reg = <0x4000 0x1000>;
 133                 };
 134                 cci_control1: slave-if@5000 {
 135                         compatible = "arm,cci-400-ctrl-if";
 136                         interface-type = "ace";
 137                         reg = <0x5000 0x1000>;
 138                 };
 139         };
 140
 141         sysram@02020000 {
 142                 compatible = "mmio-sram";
 143                 reg = <0x02020000 0x54000>;
 144                 #address-cells = <1>;
 145                 #size-cells = <1>;
 146                 ranges = <0 0x02020000 0x54000>;
 147
 148                 smp-sysram@0 {
 149                         compatible = "samsung,exynos4210-sysram";
 150                         reg = <0x0 0x1000>;
 151                 };
 152
 153                 smp-sysram@53000 {
 154                         compatible = "samsung,exynos4210-sysram-ns";
 155                         reg = <0x53000 0x1000>;
 156                 };
 157         };
 158
 159         clock: clock-controller@10010000 {
 160                 compatible = "samsung,exynos5420-clock";
 161                 reg = <0x10010000 0x30000>;
 162                 #clock-cells = <1>;
 163         };
 164
 165         clock_audss: audss-clock-controller@3810000 {
 166                 compatible = "samsung,exynos5420-audss-clock";
 167                 reg = <0x03810000 0x0C>;
 168                 #clock-cells = <1>;
 169                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 170                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 171                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 172         };
 173
 174         mfc: codec@11000000 {
 175                 compatible = "samsung,mfc-v7";
 176                 reg = <0x11000000 0x10000>;
 177                 interrupts = <0 96 0>;
 178                 clocks = <&clock CLK_MFC>;
 179                 clock-names = "mfc";
 180                 power-domains = <&mfc_pd>;
 181                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 182                 iommu-names = "left", "right";
 183         };
 184
 185         mmc_0: mmc@12200000 {
 186                 compatible = "samsung,exynos5420-dw-mshc-smu";
 187                 interrupts = <0 75 0>;
 188                 #address-cells = <1>;
 189                 #size-cells = <0>;
 190                 reg = <0x12200000 0x2000>;
 191                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 192                 clock-names = "biu", "ciu";
 193                 fifo-depth = <0x40>;
 194                 status = "disabled";
 195         };
 196
 197         mmc_1: mmc@12210000 {
 198                 compatible = "samsung,exynos5420-dw-mshc-smu";
 199                 interrupts = <0 76 0>;
 200                 #address-cells = <1>;
 201                 #size-cells = <0>;
 202                 reg = <0x12210000 0x2000>;
 203                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 204                 clock-names = "biu", "ciu";
 205                 fifo-depth = <0x40>;
 206                 status = "disabled";
 207         };
 208
 209         mmc_2: mmc@12220000 {
 210                 compatible = "samsung,exynos5420-dw-mshc";
 211                 interrupts = <0 77 0>;
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 reg = <0x12220000 0x1000>;
 215                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 216                 clock-names = "biu", "ciu";
 217                 fifo-depth = <0x40>;
 218                 status = "disabled";
 219         };
 220
 221         mct: mct@101C0000 {
 222                 compatible = "samsung,exynos4210-mct";
 223                 reg = <0x101C0000 0x800>;
 224                 interrupt-controller;
 225                 #interrupt-cells = <1>;
 226                 interrupt-parent = <&mct_map>;
 227                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 228                                 <8>, <9>, <10>, <11>;
 229                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 230                 clock-names = "fin_pll", "mct";
 231
 232                 mct_map: mct-map {
 233                         #interrupt-cells = <1>;
 234                         #address-cells = <0>;
 235                         #size-cells = <0>;
 236                         interrupt-map = <0 &combiner 23 3>,
 237                                         <1 &combiner 23 4>,
 238                                         <2 &combiner 25 2>,
 239                                         <3 &combiner 25 3>,
 240                                         <4 &gic 0 120 0>,
 241                                         <5 &gic 0 121 0>,
 242                                         <6 &gic 0 122 0>,
 243                                         <7 &gic 0 123 0>,
 244                                         <8 &gic 0 128 0>,
 245                                         <9 &gic 0 129 0>,
 246                                         <10 &gic 0 130 0>,
 247                                         <11 &gic 0 131 0>;
 248                 };
 249         };
 250
 251         gsc_pd: power-domain@10044000 {
 252                 compatible = "samsung,exynos4210-pd";
 253                 reg = <0x10044000 0x20>;
 254                 #power-domain-cells = <0>;
 255                 clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
 256                 clock-names = "asb0", "asb1";
 257         };
 258
 259         isp_pd: power-domain@10044020 {
 260                 compatible = "samsung,exynos4210-pd";
 261                 reg = <0x10044020 0x20>;
 262                 #power-domain-cells = <0>;
 263         };
 264
 265         mfc_pd: power-domain@10044060 {
 266                 compatible = "samsung,exynos4210-pd";
 267                 reg = <0x10044060 0x20>;
 268                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
 269                 clock-names = "oscclk", "clk0";
 270                 #power-domain-cells = <0>;
 271         };
 272
 273         msc_pd: power-domain@10044120 {
 274                 compatible = "samsung,exynos4210-pd";
 275                 reg = <0x10044120 0x20>;
 276                 #power-domain-cells = <0>;
 277         };
 278
 279         disp_pd: power-domain@100440C0 {
 280                 compatible = "samsung,exynos4210-pd";
 281                 reg = <0x100440C0 0x20>;
 282                 #power-domain-cells = <0>;
 283                 clocks = <&clock CLK_FIN_PLL>,
 284                          <&clock CLK_MOUT_USER_ACLK200_DISP1>,
 285                          <&clock CLK_MOUT_USER_ACLK300_DISP1>,
 286                          <&clock CLK_MOUT_USER_ACLK400_DISP1>,
 287                          <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
 288                 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
 289         };
 290
 291         pinctrl_0: pinctrl@13400000 {
 292                 compatible = "samsung,exynos5420-pinctrl";
 293                 reg = <0x13400000 0x1000>;
 294                 interrupts = <0 45 0>;
 295
 296                 wakeup-interrupt-controller {
 297                         compatible = "samsung,exynos4210-wakeup-eint";
 298                         interrupt-parent = <&gic>;
 299                         interrupts = <0 32 0>;
 300                 };
 301         };
 302
 303         pinctrl_1: pinctrl@13410000 {
 304                 compatible = "samsung,exynos5420-pinctrl";
 305                 reg = <0x13410000 0x1000>;
 306                 interrupts = <0 78 0>;
 307         };
 308
 309         pinctrl_2: pinctrl@14000000 {
 310                 compatible = "samsung,exynos5420-pinctrl";
 311                 reg = <0x14000000 0x1000>;
 312                 interrupts = <0 46 0>;
 313         };
 314
 315         pinctrl_3: pinctrl@14010000 {
 316                 compatible = "samsung,exynos5420-pinctrl";
 317                 reg = <0x14010000 0x1000>;
 318                 interrupts = <0 50 0>;
 319         };
 320
 321         pinctrl_4: pinctrl@03860000 {
 322                 compatible = "samsung,exynos5420-pinctrl";
 323                 reg = <0x03860000 0x1000>;
 324                 interrupts = <0 47 0>;
 325         };
 326
 327         amba {
 328                 #address-cells = <1>;
 329                 #size-cells = <1>;
 330                 compatible = "arm,amba-bus";
 331                 interrupt-parent = <&gic>;
 332                 ranges;
 333
 334                 adma: adma@03880000 {
 335                         compatible = "arm,pl330", "arm,primecell";
 336                         reg = <0x03880000 0x1000>;
 337                         interrupts = <0 110 0>;
 338                         clocks = <&clock_audss EXYNOS_ADMA>;
 339                         clock-names = "apb_pclk";
 340                         #dma-cells = <1>;
 341                         #dma-channels = <6>;
 342                         #dma-requests = <16>;
 343                 };
 344
 345                 pdma0: pdma@121A0000 {
 346                         compatible = "arm,pl330", "arm,primecell";
 347                         reg = <0x121A0000 0x1000>;
 348                         interrupts = <0 34 0>;
 349                         clocks = <&clock CLK_PDMA0>;
 350                         clock-names = "apb_pclk";
 351                         #dma-cells = <1>;
 352                         #dma-channels = <8>;
 353                         #dma-requests = <32>;
 354                 };
 355
 356                 pdma1: pdma@121B0000 {
 357                         compatible = "arm,pl330", "arm,primecell";
 358                         reg = <0x121B0000 0x1000>;
 359                         interrupts = <0 35 0>;
 360                         clocks = <&clock CLK_PDMA1>;
 361                         clock-names = "apb_pclk";
 362                         #dma-cells = <1>;
 363                         #dma-channels = <8>;
 364                         #dma-requests = <32>;
 365                 };
 366
 367                 mdma0: mdma@10800000 {
 368                         compatible = "arm,pl330", "arm,primecell";
 369                         reg = <0x10800000 0x1000>;
 370                         interrupts = <0 33 0>;
 371                         clocks = <&clock CLK_MDMA0>;
 372                         clock-names = "apb_pclk";
 373                         #dma-cells = <1>;
 374                         #dma-channels = <8>;
 375                         #dma-requests = <1>;
 376                 };
 377
 378                 mdma1: mdma@11C10000 {
 379                         compatible = "arm,pl330", "arm,primecell";
 380                         reg = <0x11C10000 0x1000>;
 381                         interrupts = <0 124 0>;
 382                         clocks = <&clock CLK_MDMA1>;
 383                         clock-names = "apb_pclk";
 384                         #dma-cells = <1>;
 385                         #dma-channels = <8>;
 386                         #dma-requests = <1>;
 387                         /*
 388                          * MDMA1 can support both secure and non-secure
 389                          * AXI transactions. When this is enabled in the kernel
 390                          * for boards that run in secure mode, we are getting
 391                          * imprecise external aborts causing the kernel to oops.
 392                          */
 393                         status = "disabled";
 394                 };
 395         };
 396
 397         i2s0: i2s@03830000 {
 398                 compatible = "samsung,exynos5420-i2s";
 399                 reg = <0x03830000 0x100>;
 400                 dmas = <&adma 0
 401                         &adma 2
 402                         &adma 1>;
 403                 dma-names = "tx", "rx", "tx-sec";
 404                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 405                         <&clock_audss EXYNOS_I2S_BUS>,
 406                         <&clock_audss EXYNOS_SCLK_I2S>;
 407                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 408                 #clock-cells = <1>;
 409                 clock-output-names = "i2s_cdclk0";
 410                 #sound-dai-cells = <1>;
 411                 samsung,idma-addr = <0x03000000>;
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&i2s0_bus>;
 414                 status = "disabled";
 415         };
 416
 417         i2s1: i2s@12D60000 {
 418                 compatible = "samsung,exynos5420-i2s";
 419                 reg = <0x12D60000 0x100>;
 420                 dmas = <&pdma1 12
 421                         &pdma1 11>;
 422                 dma-names = "tx", "rx";
 423                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 424                 clock-names = "iis", "i2s_opclk0";
 425                 #clock-cells = <1>;
 426                 clock-output-names = "i2s_cdclk1";
 427                 #sound-dai-cells = <1>;
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&i2s1_bus>;
 430                 status = "disabled";
 431         };
 432
 433         i2s2: i2s@12D70000 {
 434                 compatible = "samsung,exynos5420-i2s";
 435                 reg = <0x12D70000 0x100>;
 436                 dmas = <&pdma0 12
 437                         &pdma0 11>;
 438                 dma-names = "tx", "rx";
 439                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 440                 clock-names = "iis", "i2s_opclk0";
 441                 #clock-cells = <1>;
 442                 clock-output-names = "i2s_cdclk2";
 443                 #sound-dai-cells = <1>;
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&i2s2_bus>;
 446                 status = "disabled";
 447         };
 448
 449         spi_0: spi@12d20000 {
 450                 compatible = "samsung,exynos4210-spi";
 451                 reg = <0x12d20000 0x100>;
 452                 interrupts = <0 68 0>;
 453                 dmas = <&pdma0 5
 454                         &pdma0 4>;
 455                 dma-names = "tx", "rx";
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&spi0_bus>;
 460                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 461                 clock-names = "spi", "spi_busclk0";
 462                 status = "disabled";
 463         };
 464
 465         spi_1: spi@12d30000 {
 466                 compatible = "samsung,exynos4210-spi";
 467                 reg = <0x12d30000 0x100>;
 468                 interrupts = <0 69 0>;
 469                 dmas = <&pdma1 5
 470                         &pdma1 4>;
 471                 dma-names = "tx", "rx";
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&spi1_bus>;
 476                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 477                 clock-names = "spi", "spi_busclk0";
 478                 status = "disabled";
 479         };
 480
 481         spi_2: spi@12d40000 {
 482                 compatible = "samsung,exynos4210-spi";
 483                 reg = <0x12d40000 0x100>;
 484                 interrupts = <0 70 0>;
 485                 dmas = <&pdma0 7
 486                         &pdma0 6>;
 487                 dma-names = "tx", "rx";
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&spi2_bus>;
 492                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 493                 clock-names = "spi", "spi_busclk0";
 494                 status = "disabled";
 495         };
 496
 497         pwm: pwm@12dd0000 {
 498                 compatible = "samsung,exynos4210-pwm";
 499                 reg = <0x12dd0000 0x100>;
 500                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 501                 #pwm-cells = <3>;
 502                 clocks = <&clock CLK_PWM>;
 503                 clock-names = "timers";
 504         };
 505
 506         dp_phy: video-phy@10040728 {
 507                 compatible = "samsung,exynos5420-dp-video-phy";
 508                 samsung,pmu-syscon = <&pmu_system_controller>;
 509                 #phy-cells = <0>;
 510         };
 511
 512         mipi_phy: video-phy@10040714 {
 513                 compatible = "samsung,s5pv210-mipi-video-phy";
 514                 syscon = <&pmu_system_controller>;
 515                 #phy-cells = <1>;
 516         };
 517
 518         dsi@14500000 {
 519                 compatible = "samsung,exynos5410-mipi-dsi";
 520                 reg = <0x14500000 0x10000>;
 521                 interrupts = <0 82 0>;
 522                 phys = <&mipi_phy 1>;
 523                 phy-names = "dsim";
 524                 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 525                 clock-names = "bus_clk", "pll_clk";
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 status = "disabled";
 529         };
 530
 531         adc: adc@12D10000 {
 532                 compatible = "samsung,exynos-adc-v2";
 533                 reg = <0x12D10000 0x100>;
 534                 interrupts = <0 106 0>;
 535                 clocks = <&clock CLK_TSADC>;
 536                 clock-names = "adc";
 537                 #io-channel-cells = <1>;
 538                 io-channel-ranges;
 539                 samsung,syscon-phandle = <&pmu_system_controller>;
 540                 status = "disabled";
 541         };
 542
 543         i2c_0: i2c@12C60000 {
 544                 compatible = "samsung,s3c2440-i2c";
 545                 reg = <0x12C60000 0x100>;
 546                 interrupts = <0 56 0>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549                 clocks = <&clock CLK_I2C0>;
 550                 clock-names = "i2c";
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c0_bus>;
 553                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 554                 status = "disabled";
 555         };
 556
 557         i2c_1: i2c@12C70000 {
 558                 compatible = "samsung,s3c2440-i2c";
 559                 reg = <0x12C70000 0x100>;
 560                 interrupts = <0 57 0>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 clocks = <&clock CLK_I2C1>;
 564                 clock-names = "i2c";
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&i2c1_bus>;
 567                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 568                 status = "disabled";
 569         };
 570
 571         i2c_2: i2c@12C80000 {
 572                 compatible = "samsung,s3c2440-i2c";
 573                 reg = <0x12C80000 0x100>;
 574                 interrupts = <0 58 0>;
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 clocks = <&clock CLK_I2C2>;
 578                 clock-names = "i2c";
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&i2c2_bus>;
 581                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 582                 status = "disabled";
 583         };
 584
 585         i2c_3: i2c@12C90000 {
 586                 compatible = "samsung,s3c2440-i2c";
 587                 reg = <0x12C90000 0x100>;
 588                 interrupts = <0 59 0>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 clocks = <&clock CLK_I2C3>;
 592                 clock-names = "i2c";
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&i2c3_bus>;
 595                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 596                 status = "disabled";
 597         };
 598
 599         hsi2c_4: i2c@12CA0000 {
 600                 compatible = "samsung,exynos5-hsi2c";
 601                 reg = <0x12CA0000 0x1000>;
 602                 interrupts = <0 60 0>;
 603                 #address-cells = <1>;
 604                 #size-cells = <0>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&i2c4_hs_bus>;
 607                 clocks = <&clock CLK_USI0>;
 608                 clock-names = "hsi2c";
 609                 status = "disabled";
 610         };
 611
 612         hsi2c_5: i2c@12CB0000 {
 613                 compatible = "samsung,exynos5-hsi2c";
 614                 reg = <0x12CB0000 0x1000>;
 615                 interrupts = <0 61 0>;
 616                 #address-cells = <1>;
 617                 #size-cells = <0>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&i2c5_hs_bus>;
 620                 clocks = <&clock CLK_USI1>;
 621                 clock-names = "hsi2c";
 622                 status = "disabled";
 623         };
 624
 625         hsi2c_6: i2c@12CC0000 {
 626                 compatible = "samsung,exynos5-hsi2c";
 627                 reg = <0x12CC0000 0x1000>;
 628                 interrupts = <0 62 0>;
 629                 #address-cells = <1>;
 630                 #size-cells = <0>;
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&i2c6_hs_bus>;
 633                 clocks = <&clock CLK_USI2>;
 634                 clock-names = "hsi2c";
 635                 status = "disabled";
 636         };
 637
 638         hsi2c_7: i2c@12CD0000 {
 639                 compatible = "samsung,exynos5-hsi2c";
 640                 reg = <0x12CD0000 0x1000>;
 641                 interrupts = <0 63 0>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 pinctrl-names = "default";
 645                 pinctrl-0 = <&i2c7_hs_bus>;
 646                 clocks = <&clock CLK_USI3>;
 647                 clock-names = "hsi2c";
 648                 status = "disabled";
 649         };
 650
 651         hsi2c_8: i2c@12E00000 {
 652                 compatible = "samsung,exynos5-hsi2c";
 653                 reg = <0x12E00000 0x1000>;
 654                 interrupts = <0 87 0>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 pinctrl-names = "default";
 658                 pinctrl-0 = <&i2c8_hs_bus>;
 659                 clocks = <&clock CLK_USI4>;
 660                 clock-names = "hsi2c";
 661                 status = "disabled";
 662         };
 663
 664         hsi2c_9: i2c@12E10000 {
 665                 compatible = "samsung,exynos5-hsi2c";
 666                 reg = <0x12E10000 0x1000>;
 667                 interrupts = <0 88 0>;
 668                 #address-cells = <1>;
 669                 #size-cells = <0>;
 670                 pinctrl-names = "default";
 671                 pinctrl-0 = <&i2c9_hs_bus>;
 672                 clocks = <&clock CLK_USI5>;
 673                 clock-names = "hsi2c";
 674                 status = "disabled";
 675         };
 676
 677         hsi2c_10: i2c@12E20000 {
 678                 compatible = "samsung,exynos5-hsi2c";
 679                 reg = <0x12E20000 0x1000>;
 680                 interrupts = <0 203 0>;
 681                 #address-cells = <1>;
 682                 #size-cells = <0>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&i2c10_hs_bus>;
 685                 clocks = <&clock CLK_USI6>;
 686                 clock-names = "hsi2c";
 687                 status = "disabled";
 688         };
 689
 690         hdmi: hdmi@14530000 {
 691                 compatible = "samsung,exynos5420-hdmi";
 692                 reg = <0x14530000 0x70000>;
 693                 interrupts = <0 95 0>;
 694                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 695                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 696                          <&clock CLK_MOUT_HDMI>;
 697                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 698                         "sclk_hdmiphy", "mout_hdmi";
 699                 phy = <&hdmiphy>;
 700                 samsung,syscon-phandle = <&pmu_system_controller>;
 701                 status = "disabled";
 702                 power-domains = <&disp_pd>;
 703         };
 704
 705         hdmiphy: hdmiphy@145D0000 {
 706                 reg = <0x145D0000 0x20>;
 707         };
 708
 709         mixer: mixer@14450000 {
 710                 compatible = "samsung,exynos5420-mixer";
 711                 reg = <0x14450000 0x10000>;
 712                 interrupts = <0 94 0>;
 713                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 714                          <&clock CLK_SCLK_HDMI>;
 715                 clock-names = "mixer", "hdmi", "sclk_hdmi";
 716                 power-domains = <&disp_pd>;
 717                 iommus = <&sysmmu_tv>;
 718         };
 719
 720         gsc_0: video-scaler@13e00000 {
 721                 compatible = "samsung,exynos5-gsc";
 722                 reg = <0x13e00000 0x1000>;
 723                 interrupts = <0 85 0>;
 724                 clocks = <&clock CLK_GSCL0>;
 725                 clock-names = "gscl";
 726                 power-domains = <&gsc_pd>;
 727                 iommus = <&sysmmu_gscl0>;
 728         };
 729
 730         gsc_1: video-scaler@13e10000 {
 731                 compatible = "samsung,exynos5-gsc";
 732                 reg = <0x13e10000 0x1000>;
 733                 interrupts = <0 86 0>;
 734                 clocks = <&clock CLK_GSCL1>;
 735                 clock-names = "gscl";
 736                 power-domains = <&gsc_pd>;
 737                 iommus = <&sysmmu_gscl1>;
 738         };
 739
 740         jpeg_0: jpeg@11F50000 {
 741                 compatible = "samsung,exynos5420-jpeg";
 742                 reg = <0x11F50000 0x1000>;
 743                 interrupts = <0 89 0>;
 744                 clock-names = "jpeg";
 745                 clocks = <&clock CLK_JPEG>;
 746                 iommus = <&sysmmu_jpeg0>;
 747         };
 748
 749         jpeg_1: jpeg@11F60000 {
 750                 compatible = "samsung,exynos5420-jpeg";
 751                 reg = <0x11F60000 0x1000>;
 752                 interrupts = <0 168 0>;
 753                 clock-names = "jpeg";
 754                 clocks = <&clock CLK_JPEG2>;
 755                 iommus = <&sysmmu_jpeg1>;
 756         };
 757
 758         pmu_system_controller: system-controller@10040000 {
 759                 compatible = "samsung,exynos5420-pmu", "syscon";
 760                 reg = <0x10040000 0x5000>;
 761                 clock-names = "clkout16";
 762                 clocks = <&clock CLK_FIN_PLL>;
 763                 #clock-cells = <1>;
 764                 interrupt-controller;
 765                 #interrupt-cells = <3>;
 766                 interrupt-parent = <&gic>;
 767         };
 768
 769         sysreg_system_controller: syscon@10050000 {
 770                 compatible = "samsung,exynos5-sysreg", "syscon";
 771                 reg = <0x10050000 0x5000>;
 772         };
 773
 774         tmu_cpu0: tmu@10060000 {
 775                 compatible = "samsung,exynos5420-tmu";
 776                 reg = <0x10060000 0x100>;
 777                 interrupts = <0 65 0>;
 778                 clocks = <&clock CLK_TMU>;
 779                 clock-names = "tmu_apbif";
 780                 #include "exynos4412-tmu-sensor-conf.dtsi"
 781         };
 782
 783         tmu_cpu1: tmu@10064000 {
 784                 compatible = "samsung,exynos5420-tmu";
 785                 reg = <0x10064000 0x100>;
 786                 interrupts = <0 183 0>;
 787                 clocks = <&clock CLK_TMU>;
 788                 clock-names = "tmu_apbif";
 789                 #include "exynos4412-tmu-sensor-conf.dtsi"
 790         };
 791
 792         tmu_cpu2: tmu@10068000 {
 793                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 794                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 795                 interrupts = <0 184 0>;
 796                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 797                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 798                 #include "exynos4412-tmu-sensor-conf.dtsi"
 799         };
 800
 801         tmu_cpu3: tmu@1006c000 {
 802                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 803                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 804                 interrupts = <0 185 0>;
 805                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 806                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 807                 #include "exynos4412-tmu-sensor-conf.dtsi"
 808         };
 809
 810         tmu_gpu: tmu@100a0000 {
 811                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 812                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 813                 interrupts = <0 215 0>;
 814                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 815                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 816                 #include "exynos4412-tmu-sensor-conf.dtsi"
 817         };
 818
 819         thermal-zones {
 820                 cpu0_thermal: cpu0-thermal {
 821                         thermal-sensors = <&tmu_cpu0>;
 822                         #include "exynos5420-trip-points.dtsi"
 823                 };
 824                 cpu1_thermal: cpu1-thermal {
 825                        thermal-sensors = <&tmu_cpu1>;
 826                        #include "exynos5420-trip-points.dtsi"
 827                 };
 828                 cpu2_thermal: cpu2-thermal {
 829                        thermal-sensors = <&tmu_cpu2>;
 830                        #include "exynos5420-trip-points.dtsi"
 831                 };
 832                 cpu3_thermal: cpu3-thermal {
 833                        thermal-sensors = <&tmu_cpu3>;
 834                        #include "exynos5420-trip-points.dtsi"
 835                 };
 836                 gpu_thermal: gpu-thermal {
 837                        thermal-sensors = <&tmu_gpu>;
 838                        #include "exynos5420-trip-points.dtsi"
 839                 };
 840         };
 841
 842         watchdog: watchdog@101D0000 {
 843                 compatible = "samsung,exynos5420-wdt";
 844                 reg = <0x101D0000 0x100>;
 845                 interrupts = <0 42 0>;
 846                 clocks = <&clock CLK_WDT>;
 847                 clock-names = "watchdog";
 848                 samsung,syscon-phandle = <&pmu_system_controller>;
 849         };
 850
 851         sss: sss@10830000 {
 852                 compatible = "samsung,exynos4210-secss";
 853                 reg = <0x10830000 0x10000>;
 854                 interrupts = <0 112 0>;
 855                 clocks = <&clock CLK_SSS>;
 856                 clock-names = "secss";
 857         };
 858
 859         usbdrd3_0: usb@12000000 {
 860                 compatible = "samsung,exynos5250-dwusb3";
 861                 clocks = <&clock CLK_USBD300>;
 862                 clock-names = "usbdrd30";
 863                 #address-cells = <1>;
 864                 #size-cells = <1>;
 865                 ranges;
 866
 867                 usbdrd_dwc3_0: dwc3 {
 868                         compatible = "snps,dwc3";
 869                         reg = <0x12000000 0x10000>;
 870                         interrupts = <0 72 0>;
 871                         phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 872                         phy-names = "usb2-phy", "usb3-phy";
 873                 };
 874         };
 875
 876         usbdrd_phy0: phy@12100000 {
 877                 compatible = "samsung,exynos5420-usbdrd-phy";
 878                 reg = <0x12100000 0x100>;
 879                 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 880                 clock-names = "phy", "ref";
 881                 samsung,pmu-syscon = <&pmu_system_controller>;
 882                 #phy-cells = <1>;
 883         };
 884
 885         usbdrd3_1: usb@12400000 {
 886                 compatible = "samsung,exynos5250-dwusb3";
 887                 clocks = <&clock CLK_USBD301>;
 888                 clock-names = "usbdrd30";
 889                 #address-cells = <1>;
 890                 #size-cells = <1>;
 891                 ranges;
 892
 893                 usbdrd_dwc3_1: dwc3 {
 894                         compatible = "snps,dwc3";
 895                         reg = <0x12400000 0x10000>;
 896                         interrupts = <0 73 0>;
 897                         phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 898                         phy-names = "usb2-phy", "usb3-phy";
 899                 };
 900         };
 901
 902         usbdrd_phy1: phy@12500000 {
 903                 compatible = "samsung,exynos5420-usbdrd-phy";
 904                 reg = <0x12500000 0x100>;
 905                 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 906                 clock-names = "phy", "ref";
 907                 samsung,pmu-syscon = <&pmu_system_controller>;
 908                 #phy-cells = <1>;
 909         };
 910
 911         usbhost2: usb@12110000 {
 912                 compatible = "samsung,exynos4210-ehci";
 913                 reg = <0x12110000 0x100>;
 914                 interrupts = <0 71 0>;
 915
 916                 clocks = <&clock CLK_USBH20>;
 917                 clock-names = "usbhost";
 918                 #address-cells = <1>;
 919                 #size-cells = <0>;
 920                 port@0 {
 921                         reg = <0>;
 922                         phys = <&usb2_phy 1>;
 923                 };
 924         };
 925
 926         usbhost1: usb@12120000 {
 927                 compatible = "samsung,exynos4210-ohci";
 928                 reg = <0x12120000 0x100>;
 929                 interrupts = <0 71 0>;
 930
 931                 clocks = <&clock CLK_USBH20>;
 932                 clock-names = "usbhost";
 933                 #address-cells = <1>;
 934                 #size-cells = <0>;
 935                 port@0 {
 936                         reg = <0>;
 937                         phys = <&usb2_phy 1>;
 938                 };
 939         };
 940
 941         usb2_phy: phy@12130000 {
 942                 compatible = "samsung,exynos5250-usb2-phy";
 943                 reg = <0x12130000 0x100>;
 944                 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 945                 clock-names = "phy", "ref";
 946                 #phy-cells = <1>;
 947                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 948                 samsung,pmureg-phandle = <&pmu_system_controller>;
 949         };
 950
 951         sysmmu_g2dr: sysmmu@0x10A60000 {
 952                 compatible = "samsung,exynos-sysmmu";
 953                 reg = <0x10A60000 0x1000>;
 954                 interrupt-parent = <&combiner>;
 955                 interrupts = <24 5>;
 956                 clock-names = "sysmmu", "master";
 957                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 958                 #iommu-cells = <0>;
 959         };
 960
 961         sysmmu_g2dw: sysmmu@0x10A70000 {
 962                 compatible = "samsung,exynos-sysmmu";
 963                 reg = <0x10A70000 0x1000>;
 964                 interrupt-parent = <&combiner>;
 965                 interrupts = <22 2>;
 966                 clock-names = "sysmmu", "master";
 967                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 968                 #iommu-cells = <0>;
 969         };
 970
 971         sysmmu_tv: sysmmu@0x14650000 {
 972                 compatible = "samsung,exynos-sysmmu";
 973                 reg = <0x14650000 0x1000>;
 974                 interrupt-parent = <&combiner>;
 975                 interrupts = <7 4>;
 976                 clock-names = "sysmmu", "master";
 977                 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
 978                 power-domains = <&disp_pd>;
 979                 #iommu-cells = <0>;
 980         };
 981
 982         sysmmu_gscl0: sysmmu@0x13E80000 {
 983                 compatible = "samsung,exynos-sysmmu";
 984                 reg = <0x13E80000 0x1000>;
 985                 interrupt-parent = <&combiner>;
 986                 interrupts = <2 0>;
 987                 clock-names = "sysmmu", "master";
 988                 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 989                 power-domains = <&gsc_pd>;
 990                 #iommu-cells = <0>;
 991         };
 992
 993         sysmmu_gscl1: sysmmu@0x13E90000 {
 994                 compatible = "samsung,exynos-sysmmu";
 995                 reg = <0x13E90000 0x1000>;
 996                 interrupt-parent = <&combiner>;
 997                 interrupts = <2 2>;
 998                 clock-names = "sysmmu", "master";
 999                 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1000                 power-domains = <&gsc_pd>;
1001                 #iommu-cells = <0>;
1002         };
1003
1004         sysmmu_scaler0r: sysmmu@0x12880000 {
1005                 compatible = "samsung,exynos-sysmmu";
1006                 reg = <0x12880000 0x1000>;
1007                 interrupt-parent = <&combiner>;
1008                 interrupts = <22 4>;
1009                 clock-names = "sysmmu", "master";
1010                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1011                 #iommu-cells = <0>;
1012         };
1013
1014         sysmmu_scaler1r: sysmmu@0x12890000 {
1015                 compatible = "samsung,exynos-sysmmu";
1016                 reg = <0x12890000 0x1000>;
1017                 interrupts = <0 186 0>;
1018                 clock-names = "sysmmu", "master";
1019                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1020                 #iommu-cells = <0>;
1021         };
1022
1023         sysmmu_scaler2r: sysmmu@0x128A0000 {
1024                 compatible = "samsung,exynos-sysmmu";
1025                 reg = <0x128A0000 0x1000>;
1026                 interrupts = <0 188 0>;
1027                 clock-names = "sysmmu", "master";
1028                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1029                 #iommu-cells = <0>;
1030         };
1031
1032         sysmmu_scaler0w: sysmmu@0x128C0000 {
1033                 compatible = "samsung,exynos-sysmmu";
1034                 reg = <0x128C0000 0x1000>;
1035                 interrupt-parent = <&combiner>;
1036                 interrupts = <27 2>;
1037                 clock-names = "sysmmu", "master";
1038                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1039                 #iommu-cells = <0>;
1040         };
1041
1042         sysmmu_scaler1w: sysmmu@0x128D0000 {
1043                 compatible = "samsung,exynos-sysmmu";
1044                 reg = <0x128D0000 0x1000>;
1045                 interrupt-parent = <&combiner>;
1046                 interrupts = <22 6>;
1047                 clock-names = "sysmmu", "master";
1048                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1049                 #iommu-cells = <0>;
1050         };
1051
1052         sysmmu_scaler2w: sysmmu@0x128E0000 {
1053                 compatible = "samsung,exynos-sysmmu";
1054                 reg = <0x128E0000 0x1000>;
1055                 interrupt-parent = <&combiner>;
1056                 interrupts = <19 6>;
1057                 clock-names = "sysmmu", "master";
1058                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1059                 #iommu-cells = <0>;
1060         };
1061
1062         sysmmu_jpeg0: sysmmu@0x11F10000 {
1063                 compatible = "samsung,exynos-sysmmu";
1064                 reg = <0x11F10000 0x1000>;
1065                 interrupt-parent = <&combiner>;
1066                 interrupts = <4 2>;
1067                 clock-names = "sysmmu", "master";
1068                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1069                 #iommu-cells = <0>;
1070         };
1071
1072         sysmmu_jpeg1: sysmmu@0x11F20000 {
1073                 compatible = "samsung,exynos-sysmmu";
1074                 reg = <0x11F20000 0x1000>;
1075                 interrupts = <0 169 0>;
1076                 clock-names = "sysmmu", "master";
1077                 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1078                 #iommu-cells = <0>;
1079         };
1080
1081         sysmmu_mfc_l: sysmmu@0x11200000 {
1082                 compatible = "samsung,exynos-sysmmu";
1083                 reg = <0x11200000 0x1000>;
1084                 interrupt-parent = <&combiner>;
1085                 interrupts = <6 2>;
1086                 clock-names = "sysmmu", "master";
1087                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1088                 power-domains = <&mfc_pd>;
1089                 #iommu-cells = <0>;
1090         };
1091
1092         sysmmu_mfc_r: sysmmu@0x11210000 {
1093                 compatible = "samsung,exynos-sysmmu";
1094                 reg = <0x11210000 0x1000>;
1095                 interrupt-parent = <&combiner>;
1096                 interrupts = <8 5>;
1097                 clock-names = "sysmmu", "master";
1098                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1099                 power-domains = <&mfc_pd>;
1100                 #iommu-cells = <0>;
1101         };
1102
1103         sysmmu_fimd1_0: sysmmu@0x14640000 {
1104                 compatible = "samsung,exynos-sysmmu";
1105                 reg = <0x14640000 0x1000>;
1106                 interrupt-parent = <&combiner>;
1107                 interrupts = <3 2>;
1108                 clock-names = "sysmmu", "master";
1109                 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1110                 power-domains = <&disp_pd>;
1111                 #iommu-cells = <0>;
1112         };
1113
1114         sysmmu_fimd1_1: sysmmu@0x14680000 {
1115                 compatible = "samsung,exynos-sysmmu";
1116                 reg = <0x14680000 0x1000>;
1117                 interrupt-parent = <&combiner>;
1118                 interrupts = <3 0>;
1119                 clock-names = "sysmmu", "master";
1120                 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1121                 power-domains = <&disp_pd>;
1122                 #iommu-cells = <0>;
1123         };
1124 };
1125
1126 &dp {
1127         clocks = <&clock CLK_DP1>;
1128         clock-names = "dp";
1129         phys = <&dp_phy>;
1130         phy-names = "dp";
1131         power-domains = <&disp_pd>;
1132 };
1133
1134 &fimd {
1135         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1136         clock-names = "sclk_fimd", "fimd";
1137         power-domains = <&disp_pd>;
1138         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1139         iommu-names = "m0", "m1";
1140 };
1141
1142 &rtc {
1143         clocks = <&clock CLK_RTC>;
1144         clock-names = "rtc";
1145         interrupt-parent = <&pmu_system_controller>;
1146         status = "disabled";
1147 };
1148
1149 &serial_0 {
1150         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1151         clock-names = "uart", "clk_uart_baud0";
1152 };
1153
1154 &serial_1 {
1155         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1156         clock-names = "uart", "clk_uart_baud0";
1157 };
1158
1159 &serial_2 {
1160         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1161         clock-names = "uart", "clk_uart_baud0";
1162 };
1163
1164 &serial_3 {
1165         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1166         clock-names = "uart", "clk_uart_baud0";
1167 };
1168
1169 #include "exynos5420-pinctrl.dtsi"