arch/arm/boot/dts/imx27.dtsi

   1 /*
   2  * Copyright 2012 Sascha Hauer, Pengutronix
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include "skeleton.dtsi"
  13 #include "imx27-pinfunc.h"
  14
  15 #include <dt-bindings/clock/imx27-clock.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/input/input.h>
  18 #include <dt-bindings/interrupt-controller/irq.h>
  19
  20 / {
  21         aliases {
  22                 ethernet0 = &fec;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37                 spi0 = &cspi1;
  38                 spi1 = &cspi2;
  39                 spi2 = &cspi3;
  40         };
  41
  42         aitc: aitc-interrupt-controller@e0000000 {
  43                 compatible = "fsl,imx27-aitc", "fsl,avic";
  44                 interrupt-controller;
  45                 #interrupt-cells = <1>;
  46                 reg = <0x10040000 0x1000>;
  47         };
  48
  49         clocks {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 osc26m {
  54                         compatible = "fsl,imx-osc26m", "fixed-clock";
  55                         #clock-cells = <0>;
  56                         clock-frequency = <26000000>;
  57                 };
  58         };
  59
  60         cpus {
  61                 #size-cells = <0>;
  62                 #address-cells = <1>;
  63
  64                 cpu: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,arm926ej-s";
  67                         operating-points = <
  68                                 /* kHz uV */
  69                                 266000 1300000
  70                                 399000 1450000
  71                         >;
  72                         clock-latency = <62500>;
  73                         clocks = <&clks IMX27_CLK_CPU_DIV>;
  74                         voltage-tolerance = <5>;
  75                 };
  76         };
  77
  78         soc {
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81                 compatible = "simple-bus";
  82                 interrupt-parent = <&aitc>;
  83                 ranges;
  84
  85                 aipi@10000000 { /* AIPI1 */
  86                         compatible = "fsl,aipi-bus", "simple-bus";
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         reg = <0x10000000 0x20000>;
  90                         ranges;
  91
  92                         dma: dma@10001000 {
  93                                 compatible = "fsl,imx27-dma";
  94                                 reg = <0x10001000 0x1000>;
  95                                 interrupts = <32>;
  96                                 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
  97                                          <&clks IMX27_CLK_DMA_AHB_GATE>;
  98                                 clock-names = "ipg", "ahb";
  99                                 #dma-cells = <1>;
 100                                 #dma-channels = <16>;
 101                         };
 102
 103                         wdog: wdog@10002000 {
 104                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
 105                                 reg = <0x10002000 0x1000>;
 106                                 interrupts = <27>;
 107                                 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
 108                         };
 109
 110                         gpt1: timer@10003000 {
 111                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 112                                 reg = <0x10003000 0x1000>;
 113                                 interrupts = <26>;
 114                                 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
 115                                          <&clks IMX27_CLK_PER1_GATE>;
 116                                 clock-names = "ipg", "per";
 117                         };
 118
 119                         gpt2: timer@10004000 {
 120                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 121                                 reg = <0x10004000 0x1000>;
 122                                 interrupts = <25>;
 123                                 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
 124                                          <&clks IMX27_CLK_PER1_GATE>;
 125                                 clock-names = "ipg", "per";
 126                         };
 127
 128                         gpt3: timer@10005000 {
 129                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 130                                 reg = <0x10005000 0x1000>;
 131                                 interrupts = <24>;
 132                                 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
 133                                          <&clks IMX27_CLK_PER1_GATE>;
 134                                 clock-names = "ipg", "per";
 135                         };
 136
 137                         pwm: pwm@10006000 {
 138                                 #pwm-cells = <2>;
 139                                 compatible = "fsl,imx27-pwm";
 140                                 reg = <0x10006000 0x1000>;
 141                                 interrupts = <23>;
 142                                 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
 143                                          <&clks IMX27_CLK_PER1_GATE>;
 144                                 clock-names = "ipg", "per";
 145                         };
 146
 147                         rtc: rtc@10007000 {
 148                                 compatible = "fsl,imx21-rtc";
 149                                 reg = <0x10007000 0x1000>;
 150                                 interrupts = <22>;
 151                                 clocks = <&clks IMX27_CLK_CKIL>,
 152                                          <&clks IMX27_CLK_RTC_IPG_GATE>;
 153                                 clock-names = "ref", "ipg";
 154                         };
 155
 156                         kpp: kpp@10008000 {
 157                                 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
 158                                 reg = <0x10008000 0x1000>;
 159                                 interrupts = <21>;
 160                                 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
 161                                 status = "disabled";
 162                         };
 163
 164                         owire: owire@10009000 {
 165                                 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
 166                                 reg = <0x10009000 0x1000>;
 167                                 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
 168                                 status = "disabled";
 169                         };
 170
 171                         uart1: serial@1000a000 {
 172                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 173                                 reg = <0x1000a000 0x1000>;
 174                                 interrupts = <20>;
 175                                 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
 176                                          <&clks IMX27_CLK_PER1_GATE>;
 177                                 clock-names = "ipg", "per";
 178                                 status = "disabled";
 179                         };
 180
 181                         uart2: serial@1000b000 {
 182                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 183                                 reg = <0x1000b000 0x1000>;
 184                                 interrupts = <19>;
 185                                 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
 186                                          <&clks IMX27_CLK_PER1_GATE>;
 187                                 clock-names = "ipg", "per";
 188                                 status = "disabled";
 189                         };
 190
 191                         uart3: serial@1000c000 {
 192                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 193                                 reg = <0x1000c000 0x1000>;
 194                                 interrupts = <18>;
 195                                 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
 196                                          <&clks IMX27_CLK_PER1_GATE>;
 197                                 clock-names = "ipg", "per";
 198                                 status = "disabled";
 199                         };
 200
 201                         uart4: serial@1000d000 {
 202                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 203                                 reg = <0x1000d000 0x1000>;
 204                                 interrupts = <17>;
 205                                 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
 206                                          <&clks IMX27_CLK_PER1_GATE>;
 207                                 clock-names = "ipg", "per";
 208                                 status = "disabled";
 209                         };
 210
 211                         cspi1: cspi@1000e000 {
 212                                 #address-cells = <1>;
 213                                 #size-cells = <0>;
 214                                 compatible = "fsl,imx27-cspi";
 215                                 reg = <0x1000e000 0x1000>;
 216                                 interrupts = <16>;
 217                                 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
 218                                          <&clks IMX27_CLK_PER2_GATE>;
 219                                 clock-names = "ipg", "per";
 220                                 status = "disabled";
 221                         };
 222
 223                         cspi2: cspi@1000f000 {
 224                                 #address-cells = <1>;
 225                                 #size-cells = <0>;
 226                                 compatible = "fsl,imx27-cspi";
 227                                 reg = <0x1000f000 0x1000>;
 228                                 interrupts = <15>;
 229                                 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
 230                                          <&clks IMX27_CLK_PER2_GATE>;
 231                                 clock-names = "ipg", "per";
 232                                 status = "disabled";
 233                         };
 234
 235                         ssi1: ssi@10010000 {
 236                                 #sound-dai-cells = <0>;
 237                                 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
 238                                 reg = <0x10010000 0x1000>;
 239                                 interrupts = <14>;
 240                                 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
 241                                 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
 242                                 dma-names = "rx0", "tx0", "rx1", "tx1";
 243                                 fsl,fifo-depth = <8>;
 244                                 status = "disabled";
 245                         };
 246
 247                         ssi2: ssi@10011000 {
 248                                 #sound-dai-cells = <0>;
 249                                 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
 250                                 reg = <0x10011000 0x1000>;
 251                                 interrupts = <13>;
 252                                 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
 253                                 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
 254                                 dma-names = "rx0", "tx0", "rx1", "tx1";
 255                                 fsl,fifo-depth = <8>;
 256                                 status = "disabled";
 257                         };
 258
 259                         i2c1: i2c@10012000 {
 260                                 #address-cells = <1>;
 261                                 #size-cells = <0>;
 262                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 263                                 reg = <0x10012000 0x1000>;
 264                                 interrupts = <12>;
 265                                 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
 266                                 status = "disabled";
 267                         };
 268
 269                         sdhci1: sdhci@10013000 {
 270                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 271                                 reg = <0x10013000 0x1000>;
 272                                 interrupts = <11>;
 273                                 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
 274                                          <&clks IMX27_CLK_PER2_GATE>;
 275                                 clock-names = "ipg", "per";
 276                                 dmas = <&dma 7>;
 277                                 dma-names = "rx-tx";
 278                                 status = "disabled";
 279                         };
 280
 281                         sdhci2: sdhci@10014000 {
 282                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 283                                 reg = <0x10014000 0x1000>;
 284                                 interrupts = <10>;
 285                                 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
 286                                          <&clks IMX27_CLK_PER2_GATE>;
 287                                 clock-names = "ipg", "per";
 288                                 dmas = <&dma 6>;
 289                                 dma-names = "rx-tx";
 290                                 status = "disabled";
 291                         };
 292
 293                         iomuxc: iomuxc@10015000 {
 294                                 compatible = "fsl,imx27-iomuxc";
 295                                 reg = <0x10015000 0x600>;
 296                                 #address-cells = <1>;
 297                                 #size-cells = <1>;
 298                                 ranges;
 299
 300                                 gpio1: gpio@10015000 {
 301                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 302                                         reg = <0x10015000 0x100>;
 303                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 304                                         interrupts = <8>;
 305                                         gpio-controller;
 306                                         #gpio-cells = <2>;
 307                                         interrupt-controller;
 308                                         #interrupt-cells = <2>;
 309                                 };
 310
 311                                 gpio2: gpio@10015100 {
 312                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 313                                         reg = <0x10015100 0x100>;
 314                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 315                                         interrupts = <8>;
 316                                         gpio-controller;
 317                                         #gpio-cells = <2>;
 318                                         interrupt-controller;
 319                                         #interrupt-cells = <2>;
 320                                 };
 321
 322                                 gpio3: gpio@10015200 {
 323                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 324                                         reg = <0x10015200 0x100>;
 325                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 326                                         interrupts = <8>;
 327                                         gpio-controller;
 328                                         #gpio-cells = <2>;
 329                                         interrupt-controller;
 330                                         #interrupt-cells = <2>;
 331                                 };
 332
 333                                 gpio4: gpio@10015300 {
 334                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 335                                         reg = <0x10015300 0x100>;
 336                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 337                                         interrupts = <8>;
 338                                         gpio-controller;
 339                                         #gpio-cells = <2>;
 340                                         interrupt-controller;
 341                                         #interrupt-cells = <2>;
 342                                 };
 343
 344                                 gpio5: gpio@10015400 {
 345                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 346                                         reg = <0x10015400 0x100>;
 347                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 348                                         interrupts = <8>;
 349                                         gpio-controller;
 350                                         #gpio-cells = <2>;
 351                                         interrupt-controller;
 352                                         #interrupt-cells = <2>;
 353                                 };
 354
 355                                 gpio6: gpio@10015500 {
 356                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 357                                         reg = <0x10015500 0x100>;
 358                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 359                                         interrupts = <8>;
 360                                         gpio-controller;
 361                                         #gpio-cells = <2>;
 362                                         interrupt-controller;
 363                                         #interrupt-cells = <2>;
 364                                 };
 365                         };
 366
 367                         audmux: audmux@10016000 {
 368                                 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
 369                                 reg = <0x10016000 0x1000>;
 370                                 clocks = <&clks IMX27_CLK_DUMMY>;
 371                                 clock-names = "audmux";
 372                                 status = "disabled";
 373                         };
 374
 375                         cspi3: cspi@10017000 {
 376                                 #address-cells = <1>;
 377                                 #size-cells = <0>;
 378                                 compatible = "fsl,imx27-cspi";
 379                                 reg = <0x10017000 0x1000>;
 380                                 interrupts = <6>;
 381                                 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
 382                                          <&clks IMX27_CLK_PER2_GATE>;
 383                                 clock-names = "ipg", "per";
 384                                 status = "disabled";
 385                         };
 386
 387                         gpt4: timer@10019000 {
 388                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 389                                 reg = <0x10019000 0x1000>;
 390                                 interrupts = <4>;
 391                                 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
 392                                          <&clks IMX27_CLK_PER1_GATE>;
 393                                 clock-names = "ipg", "per";
 394                         };
 395
 396                         gpt5: timer@1001a000 {
 397                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 398                                 reg = <0x1001a000 0x1000>;
 399                                 interrupts = <3>;
 400                                 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
 401                                          <&clks IMX27_CLK_PER1_GATE>;
 402                                 clock-names = "ipg", "per";
 403                         };
 404
 405                         uart5: serial@1001b000 {
 406                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 407                                 reg = <0x1001b000 0x1000>;
 408                                 interrupts = <49>;
 409                                 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
 410                                          <&clks IMX27_CLK_PER1_GATE>;
 411                                 clock-names = "ipg", "per";
 412                                 status = "disabled";
 413                         };
 414
 415                         uart6: serial@1001c000 {
 416                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 417                                 reg = <0x1001c000 0x1000>;
 418                                 interrupts = <48>;
 419                                 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
 420                                          <&clks IMX27_CLK_PER1_GATE>;
 421                                 clock-names = "ipg", "per";
 422                                 status = "disabled";
 423                         };
 424
 425                         i2c2: i2c@1001d000 {
 426                                 #address-cells = <1>;
 427                                 #size-cells = <0>;
 428                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 429                                 reg = <0x1001d000 0x1000>;
 430                                 interrupts = <1>;
 431                                 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
 432                                 status = "disabled";
 433                         };
 434
 435                         sdhci3: sdhci@1001e000 {
 436                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 437                                 reg = <0x1001e000 0x1000>;
 438                                 interrupts = <9>;
 439                                 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
 440                                          <&clks IMX27_CLK_PER2_GATE>;
 441                                 clock-names = "ipg", "per";
 442                                 dmas = <&dma 36>;
 443                                 dma-names = "rx-tx";
 444                                 status = "disabled";
 445                         };
 446
 447                         gpt6: timer@1001f000 {
 448                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 449                                 reg = <0x1001f000 0x1000>;
 450                                 interrupts = <2>;
 451                                 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
 452                                          <&clks IMX27_CLK_PER1_GATE>;
 453                                 clock-names = "ipg", "per";
 454                         };
 455                 };
 456
 457                 aipi@10020000 { /* AIPI2 */
 458                         compatible = "fsl,aipi-bus", "simple-bus";
 459                         #address-cells = <1>;
 460                         #size-cells = <1>;
 461                         reg = <0x10020000 0x20000>;
 462                         ranges;
 463
 464                         fb: fb@10021000 {
 465                                 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
 466                                 interrupts = <61>;
 467                                 reg = <0x10021000 0x1000>;
 468                                 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
 469                                          <&clks IMX27_CLK_LCDC_AHB_GATE>,
 470                                          <&clks IMX27_CLK_PER3_GATE>;
 471                                 clock-names = "ipg", "ahb", "per";
 472                                 status = "disabled";
 473                         };
 474
 475                         coda: coda@10023000 {
 476                                 compatible = "fsl,imx27-vpu", "cnm,codadx6";
 477                                 reg = <0x10023000 0x0200>;
 478                                 interrupts = <53>;
 479                                 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
 480                                          <&clks IMX27_CLK_VPU_AHB_GATE>;
 481                                 clock-names = "per", "ahb";
 482                                 iram = <&iram>;
 483                         };
 484
 485                         usbotg: usb@10024000 {
 486                                 compatible = "fsl,imx27-usb";
 487                                 reg = <0x10024000 0x200>;
 488                                 interrupts = <56>;
 489                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
 490                                         <&clks IMX27_CLK_USB_AHB_GATE>,
 491                                         <&clks IMX27_CLK_USB_DIV>;
 492                                 clock-names = "ipg", "ahb", "per";
 493                                 fsl,usbmisc = <&usbmisc 0>;
 494                                 status = "disabled";
 495                         };
 496
 497                         usbh1: usb@10024200 {
 498                                 compatible = "fsl,imx27-usb";
 499                                 reg = <0x10024200 0x200>;
 500                                 interrupts = <54>;
 501                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
 502                                         <&clks IMX27_CLK_USB_AHB_GATE>,
 503                                         <&clks IMX27_CLK_USB_DIV>;
 504                                 clock-names = "ipg", "ahb", "per";
 505                                 fsl,usbmisc = <&usbmisc 1>;
 506                                 dr_mode = "host";
 507                                 status = "disabled";
 508                         };
 509
 510                         usbh2: usb@10024400 {
 511                                 compatible = "fsl,imx27-usb";
 512                                 reg = <0x10024400 0x200>;
 513                                 interrupts = <55>;
 514                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
 515                                         <&clks IMX27_CLK_USB_AHB_GATE>,
 516                                         <&clks IMX27_CLK_USB_DIV>;
 517                                 clock-names = "ipg", "ahb", "per";
 518                                 fsl,usbmisc = <&usbmisc 2>;
 519                                 dr_mode = "host";
 520                                 status = "disabled";
 521                         };
 522
 523                         usbmisc: usbmisc@10024600 {
 524                                 #index-cells = <1>;
 525                                 compatible = "fsl,imx27-usbmisc";
 526                                 reg = <0x10024600 0x200>;
 527                         };
 528
 529                         sahara2: sahara@10025000 {
 530                                 compatible = "fsl,imx27-sahara";
 531                                 reg = <0x10025000 0x1000>;
 532                                 interrupts = <59>;
 533                                 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
 534                                          <&clks IMX27_CLK_SAHARA_AHB_GATE>;
 535                                 clock-names = "ipg", "ahb";
 536                         };
 537
 538                         clks: ccm@10027000{
 539                                 compatible = "fsl,imx27-ccm";
 540                                 reg = <0x10027000 0x1000>;
 541                                 #clock-cells = <1>;
 542                         };
 543
 544                         iim: iim@10028000 {
 545                                 compatible = "fsl,imx27-iim";
 546                                 reg = <0x10028000 0x1000>;
 547                                 interrupts = <62>;
 548                                 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
 549                         };
 550
 551                         fec: ethernet@1002b000 {
 552                                 compatible = "fsl,imx27-fec";
 553                                 reg = <0x1002b000 0x1000>;
 554                                 interrupts = <50>;
 555                                 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
 556                                          <&clks IMX27_CLK_FEC_AHB_GATE>;
 557                                 clock-names = "ipg", "ahb";
 558                                 status = "disabled";
 559                         };
 560                 };
 561
 562                 nfc: nand@d8000000 {
 563                         #address-cells = <1>;
 564                         #size-cells = <1>;
 565                         compatible = "fsl,imx27-nand";
 566                         reg = <0xd8000000 0x1000>;
 567                         interrupts = <29>;
 568                         clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
 569                         status = "disabled";
 570                 };
 571
 572                 weim: weim@d8002000 {
 573                         #address-cells = <2>;
 574                         #size-cells = <1>;
 575                         compatible = "fsl,imx27-weim";
 576                         reg = <0xd8002000 0x1000>;
 577                         clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
 578                         ranges = <
 579                                 0 0 0xc0000000 0x08000000
 580                                 1 0 0xc8000000 0x08000000
 581                                 2 0 0xd0000000 0x02000000
 582                                 3 0 0xd2000000 0x02000000
 583                                 4 0 0xd4000000 0x02000000
 584                                 5 0 0xd6000000 0x02000000
 585                         >;
 586                         status = "disabled";
 587                 };
 588
 589                 iram: iram@ffff4c00 {
 590                         compatible = "mmio-sram";
 591                         reg = <0xffff4c00 0xb400>;
 592                 };
 593         };
 594 };