arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi

   1 /*
   2  * Copyright 2013 Boundary Devices, Inc.
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/input/input.h>
  15
  16 / {
  17         chosen {
  18                 stdout-path = &uart2;
  19         };
  20
  21         memory {
  22                 reg = <0x10000000 0x40000000>;
  23         };
  24
  25         regulators {
  26                 compatible = "simple-bus";
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 reg_2p5v: regulator@0 {
  31                         compatible = "regulator-fixed";
  32                         reg = <0>;
  33                         regulator-name = "2P5V";
  34                         regulator-min-microvolt = <2500000>;
  35                         regulator-max-microvolt = <2500000>;
  36                         regulator-always-on;
  37                 };
  38
  39                 reg_3p3v: regulator@1 {
  40                         compatible = "regulator-fixed";
  41                         reg = <1>;
  42                         regulator-name = "3P3V";
  43                         regulator-min-microvolt = <3300000>;
  44                         regulator-max-microvolt = <3300000>;
  45                         regulator-always-on;
  46                 };
  47
  48                 reg_usb_otg_vbus: regulator@2 {
  49                         compatible = "regulator-fixed";
  50                         reg = <2>;
  51                         regulator-name = "usb_otg_vbus";
  52                         regulator-min-microvolt = <5000000>;
  53                         regulator-max-microvolt = <5000000>;
  54                         gpio = <&gpio3 22 0>;
  55                         enable-active-high;
  56                 };
  57
  58                 reg_can_xcvr: regulator@3 {
  59                         compatible = "regulator-fixed";
  60                         reg = <3>;
  61                         regulator-name = "CAN XCVR";
  62                         regulator-min-microvolt = <3300000>;
  63                         regulator-max-microvolt = <3300000>;
  64                         pinctrl-names = "default";
  65                         pinctrl-0 = <&pinctrl_can_xcvr>;
  66                         gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
  67                 };
  68         };
  69
  70         gpio-keys {
  71                 compatible = "gpio-keys";
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&pinctrl_gpio_keys>;
  74
  75                 power {
  76                         label = "Power Button";
  77                         gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
  78                         linux,code = <KEY_POWER>;
  79                         gpio-key,wakeup;
  80                 };
  81
  82                 menu {
  83                         label = "Menu";
  84                         gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  85                         linux,code = <KEY_MENU>;
  86                 };
  87
  88                 home {
  89                         label = "Home";
  90                         gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
  91                         linux,code = <KEY_HOME>;
  92                 };
  93
  94                 back {
  95                         label = "Back";
  96                         gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  97                         linux,code = <KEY_BACK>;
  98                 };
  99
 100                 volume-up {
 101                         label = "Volume Up";
 102                         gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
 103                         linux,code = <KEY_VOLUMEUP>;
 104                 };
 105
 106                 volume-down {
 107                         label = "Volume Down";
 108                         gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
 109                         linux,code = <KEY_VOLUMEDOWN>;
 110                 };
 111         };
 112
 113         sound {
 114                 compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
 115                              "fsl,imx-audio-sgtl5000";
 116                 model = "imx6q-nitrogen6x-sgtl5000";
 117                 ssi-controller = <&ssi1>;
 118                 audio-codec = <&codec>;
 119                 audio-routing =
 120                         "MIC_IN", "Mic Jack",
 121                         "Mic Jack", "Mic Bias",
 122                         "Headphone Jack", "HP_OUT";
 123                 mux-int-port = <1>;
 124                 mux-ext-port = <3>;
 125         };
 126
 127         backlight_lcd {
 128                 compatible = "pwm-backlight";
 129                 pwms = <&pwm1 0 5000000>;
 130                 brightness-levels = <0 4 8 16 32 64 128 255>;
 131                 default-brightness-level = <7>;
 132                 power-supply = <&reg_3p3v>;
 133                 status = "okay";
 134         };
 135
 136         backlight_lvds: backlight_lvds {
 137                 compatible = "pwm-backlight";
 138                 pwms = <&pwm4 0 5000000>;
 139                 brightness-levels = <0 4 8 16 32 64 128 255>;
 140                 default-brightness-level = <7>;
 141                 power-supply = <&reg_3p3v>;
 142                 status = "okay";
 143         };
 144
 145         panel {
 146                 compatible = "hannstar,hsd100pxn1";
 147                 backlight = <&backlight_lvds>;
 148
 149                 port {
 150                         panel_in: endpoint {
 151                                 remote-endpoint = <&lvds0_out>;
 152                         };
 153                 };
 154         };
 155 };
 156
 157 &audmux {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_audmux>;
 160         status = "okay";
 161 };
 162
 163 &can1 {
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_can1>;
 166         xceiver-supply = <&reg_can_xcvr>;
 167         status = "okay";
 168 };
 169
 170 &clks {
 171         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 172                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 173         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 174                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 175 };
 176
 177 &ecspi1 {
 178         fsl,spi-num-chipselects = <1>;
 179         cs-gpios = <&gpio3 19 0>;
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_ecspi1>;
 182         status = "okay";
 183
 184         flash: m25p80@0 {
 185                 compatible = "sst,sst25vf016b";
 186                 spi-max-frequency = <20000000>;
 187                 reg = <0>;
 188         };
 189 };
 190
 191 &fec {
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&pinctrl_enet>;
 194         phy-mode = "rgmii";
 195         phy-reset-gpios = <&gpio1 27 0>;
 196         txen-skew-ps = <0>;
 197         txc-skew-ps = <3000>;
 198         rxdv-skew-ps = <0>;
 199         rxc-skew-ps = <3000>;
 200         rxd0-skew-ps = <0>;
 201         rxd1-skew-ps = <0>;
 202         rxd2-skew-ps = <0>;
 203         rxd3-skew-ps = <0>;
 204         txd0-skew-ps = <0>;
 205         txd1-skew-ps = <0>;
 206         txd2-skew-ps = <0>;
 207         txd3-skew-ps = <0>;
 208         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 209                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 210         status = "okay";
 211 };
 212
 213 &hdmi {
 214         ddc-i2c-bus = <&i2c2>;
 215         status = "okay";
 216 };
 217
 218 &i2c1 {
 219         clock-frequency = <100000>;
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_i2c1>;
 222         status = "okay";
 223
 224         codec: sgtl5000@0a {
 225                 compatible = "fsl,sgtl5000";
 226                 reg = <0x0a>;
 227                 clocks = <&clks 201>;
 228                 VDDA-supply = <&reg_2p5v>;
 229                 VDDIO-supply = <&reg_3p3v>;
 230         };
 231
 232         rtc: rtc@6f {
 233                 compatible = "isil,isl1208";
 234                 reg = <0x6f>;
 235         };
 236 };
 237
 238 &i2c2 {
 239         clock-frequency = <100000>;
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_i2c2>;
 242         status = "okay";
 243 };
 244
 245 &i2c3 {
 246         clock-frequency = <100000>;
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_i2c3>;
 249         status = "okay";
 250 };
 251
 252 &iomuxc {
 253         pinctrl-names = "default";
 254         pinctrl-0 = <&pinctrl_hog>;
 255
 256         imx6q-nitrogen6x {
 257                 pinctrl_hog: hoggrp {
 258                         fsl,pins = <
 259                                 /* SGTL5000 sys_mclk */
 260                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x030b0
 261                         >;
 262                 };
 263
 264                 pinctrl_audmux: audmuxgrp {
 265                         fsl,pins = <
 266                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 267                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 268                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 269                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 270                         >;
 271                 };
 272
 273                 pinctrl_can1: can1grp {
 274                         fsl,pins = <
 275                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
 276                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
 277                         >;
 278                 };
 279
 280                 pinctrl_can_xcvr: can-xcvrgrp {
 281                         fsl,pins = <
 282                                 /* Flexcan XCVR enable */
 283                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 284                         >;
 285                 };
 286
 287                 pinctrl_ecspi1: ecspi1grp {
 288                         fsl,pins = <
 289                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 290                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 291                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 292                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x000b1 /* CS */
 293                         >;
 294                 };
 295
 296                 pinctrl_enet: enetgrp {
 297                         fsl,pins = <
 298                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 299                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 300                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
 301                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
 302                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
 303                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
 304                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
 305                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
 306                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 307                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 308                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 309                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 310                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 311                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 312                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 313                                 /* Phy reset */
 314                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x000b0
 315                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 316                         >;
 317                 };
 318
 319                 pinctrl_gpio_keys: gpio_keysgrp {
 320                         fsl,pins = <
 321                                 /* Power Button */
 322                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x1b0b0
 323                                 /* Menu Button */
 324                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 325                                 /* Home Button */
 326                                 MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x1b0b0
 327                                 /* Back Button */
 328                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x1b0b0
 329                                 /* Volume Up Button */
 330                                 MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
 331                                 /* Volume Down Button */
 332                                 MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 333                         >;
 334                 };
 335
 336                 pinctrl_i2c1: i2c1grp {
 337                         fsl,pins = <
 338                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 339                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 340                         >;
 341                 };
 342
 343                 pinctrl_i2c2: i2c2grp {
 344                         fsl,pins = <
 345                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 346                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 347                         >;
 348                 };
 349
 350                 pinctrl_i2c3: i2c3grp {
 351                         fsl,pins = <
 352                                 MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
 353                                 MX6QDL_PAD_GPIO_16__I2C3_SDA            0x4001b8b1
 354                         >;
 355                 };
 356
 357                 pinctrl_pwm1: pwm1grp {
 358                         fsl,pins = <
 359                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
 360                         >;
 361                 };
 362
 363                 pinctrl_pwm3: pwm3grp {
 364                         fsl,pins = <
 365                                 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
 366                         >;
 367                 };
 368
 369                 pinctrl_pwm4: pwm4grp {
 370                         fsl,pins = <
 371                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
 372                         >;
 373                 };
 374
 375                 pinctrl_uart1: uart1grp {
 376                         fsl,pins = <
 377                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 378                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 379                         >;
 380                 };
 381
 382                 pinctrl_uart2: uart2grp {
 383                         fsl,pins = <
 384                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
 385                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
 386                         >;
 387                 };
 388
 389                 pinctrl_usbotg: usbotggrp {
 390                         fsl,pins = <
 391                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID   0x17059
 392                                 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
 393                                 /* power enable, high active */
 394                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x000b0
 395                         >;
 396                 };
 397
 398                 pinctrl_usdhc3: usdhc3grp {
 399                         fsl,pins = <
 400                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 401                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 402                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 403                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 404                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 405                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 406                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
 407                         >;
 408                 };
 409
 410                 pinctrl_usdhc4: usdhc4grp {
 411                         fsl,pins = <
 412                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 413                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 414                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 415                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 416                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 417                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 418                                 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
 419                         >;
 420                 };
 421         };
 422 };
 423
 424 &ldb {
 425         status = "okay";
 426
 427         lvds-channel@0 {
 428                 fsl,data-mapping = "spwg";
 429                 fsl,data-width = <18>;
 430                 status = "okay";
 431
 432                 port@4 {
 433                         reg = <4>;
 434
 435                         lvds0_out: endpoint {
 436                                 remote-endpoint = <&panel_in>;
 437                         };
 438                 };
 439         };
 440 };
 441
 442 &pcie {
 443         status = "okay";
 444 };
 445
 446 &pwm1 {
 447         pinctrl-names = "default";
 448         pinctrl-0 = <&pinctrl_pwm1>;
 449         status = "okay";
 450 };
 451
 452 &pwm3 {
 453         pinctrl-names = "default";
 454         pinctrl-0 = <&pinctrl_pwm3>;
 455         status = "okay";
 456 };
 457
 458 &pwm4 {
 459         pinctrl-names = "default";
 460         pinctrl-0 = <&pinctrl_pwm4>;
 461         status = "okay";
 462 };
 463
 464 &ssi1 {
 465         status = "okay";
 466 };
 467
 468 &uart1 {
 469         pinctrl-names = "default";
 470         pinctrl-0 = <&pinctrl_uart1>;
 471         status = "okay";
 472 };
 473
 474 &uart2 {
 475         pinctrl-names = "default";
 476         pinctrl-0 = <&pinctrl_uart2>;
 477         status = "okay";
 478 };
 479
 480 &usbh1 {
 481         status = "okay";
 482 };
 483
 484 &usbotg {
 485         vbus-supply = <&reg_usb_otg_vbus>;
 486         pinctrl-names = "default";
 487         pinctrl-0 = <&pinctrl_usbotg>;
 488         disable-over-current;
 489         status = "okay";
 490 };
 491
 492 &usdhc3 {
 493         pinctrl-names = "default";
 494         pinctrl-0 = <&pinctrl_usdhc3>;
 495         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 496         vmmc-supply = <&reg_3p3v>;
 497         status = "okay";
 498 };
 499
 500 &usdhc4 {
 501         pinctrl-names = "default";
 502         pinctrl-0 = <&pinctrl_usdhc4>;
 503         cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
 504         vmmc-supply = <&reg_3p3v>;
 505         status = "okay";
 506 };