arch/arm/boot/dts/imx6qdl-rex.dtsi

   1 /*
   2  * Copyright 2014 FEDEVEL, Inc.
   3  *
   4  * Author: Robert Nelson <robertcnelson@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         chosen {
  17                 stdout-path = &uart1;
  18         };
  19
  20         regulators {
  21                 compatible = "simple-bus";
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 reg_3p3v: regulator@0 {
  26                         compatible = "regulator-fixed";
  27                         reg = <0>;
  28                         regulator-name = "3P3V";
  29                         regulator-min-microvolt = <3300000>;
  30                         regulator-max-microvolt = <3300000>;
  31                         regulator-always-on;
  32                 };
  33
  34                 reg_usbh1_vbus: regulator@1 {
  35                         compatible = "regulator-fixed";
  36                         reg = <1>;
  37                         pinctrl-names = "default";
  38                         pinctrl-0 = <&pinctrl_usbh1>;
  39                         regulator-name = "usbh1_vbus";
  40                         regulator-min-microvolt = <5000000>;
  41                         regulator-max-microvolt = <5000000>;
  42                         gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
  43                         enable-active-high;
  44                 };
  45
  46                 reg_usb_otg_vbus: regulator@2 {
  47                         compatible = "regulator-fixed";
  48                         reg = <2>;
  49                         pinctrl-names = "default";
  50                         pinctrl-0 = <&pinctrl_usbotg>;
  51                         regulator-name = "usb_otg_vbus";
  52                         regulator-min-microvolt = <5000000>;
  53                         regulator-max-microvolt = <5000000>;
  54                         gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  55                         enable-active-high;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&pinctrl_led>;
  63
  64                 led0: usr {
  65                         label = "usr";
  66                         gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
  67                         default-state = "off";
  68                         linux,default-trigger = "heartbeat";
  69                 };
  70         };
  71
  72         sound {
  73                 compatible = "fsl,imx6-rex-sgtl5000",
  74                              "fsl,imx-audio-sgtl5000";
  75                 model = "imx6-rex-sgtl5000";
  76                 ssi-controller = <&ssi1>;
  77                 audio-codec = <&codec>;
  78                 audio-routing =
  79                         "MIC_IN", "Mic Jack",
  80                         "Mic Jack", "Mic Bias",
  81                         "Headphone Jack", "HP_OUT";
  82                 mux-int-port = <1>;
  83                 mux-ext-port = <3>;
  84         };
  85 };
  86
  87 &audmux {
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_audmux>;
  90         status = "okay";
  91 };
  92
  93 &ecspi2 {
  94         fsl,spi-num-chipselects = <1>;
  95         cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_ecspi2>;
  98         status = "okay";
  99 };
 100
 101 &ecspi3 {
 102         fsl,spi-num-chipselects = <1>;
 103         cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pinctrl_ecspi3>;
 106         status = "okay";
 107 };
 108
 109 &fec {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_enet>;
 112         phy-mode = "rgmii";
 113         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 114         status = "okay";
 115 };
 116
 117 &hdmi {
 118         ddc-i2c-bus = <&i2c2>;
 119         status = "okay";
 120 };
 121
 122 &i2c1 {
 123         clock-frequency = <100000>;
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_i2c1>;
 126         status = "okay";
 127
 128         codec: sgtl5000@0a {
 129                 compatible = "fsl,sgtl5000";
 130                 reg = <0x0a>;
 131                 clocks = <&clks 201>;
 132                 VDDA-supply = <&reg_3p3v>;
 133                 VDDIO-supply = <&reg_3p3v>;
 134         };
 135 };
 136
 137 &i2c2 {
 138         clock-frequency = <100000>;
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_i2c2>;
 141         status = "okay";
 142
 143         eeprom@57 {
 144                 compatible = "at,24c02";
 145                 reg = <0x57>;
 146         };
 147 };
 148
 149 &i2c3 {
 150         clock-frequency = <100000>;
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_i2c3>;
 153         status = "okay";
 154 };
 155
 156 &iomuxc {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_hog>;
 159
 160         imx6qdl-rex {
 161                 pinctrl_hog: hoggrp {
 162                         fsl,pins = <
 163                                 /* SGTL5000 sys_mclk */
 164                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x030b0
 165                         >;
 166                 };
 167
 168                 pinctrl_audmux: audmuxgrp {
 169                         fsl,pins = <
 170                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 171                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 172                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 173                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 174                         >;
 175                 };
 176
 177                 pinctrl_ecspi2: ecspi2grp {
 178                         fsl,pins = <
 179                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 180                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 181                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 182                                 /* CS */
 183                                 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26       0x000b1
 184                         >;
 185                 };
 186
 187                 pinctrl_ecspi3: ecspi3grp {
 188                         fsl,pins = <
 189                                 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO     0x100b1
 190                                 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI     0x100b1
 191                                 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK     0x100b1
 192                                 /* CS */
 193                                 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x000b1
 194                         >;
 195                 };
 196
 197                 pinctrl_enet: enetgrp {
 198                         fsl,pins = <
 199                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 200                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 201                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 202                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 203                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 204                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 205                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 206                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 207                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 208                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 209                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 210                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 211                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 212                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 213                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 214                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 215                                 /* Phy reset */
 216                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x000b0
 217                         >;
 218                 };
 219
 220                 pinctrl_i2c1: i2c1grp {
 221                         fsl,pins = <
 222                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 223                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 224                         >;
 225                 };
 226
 227                 pinctrl_i2c2: i2c2grp {
 228                         fsl,pins = <
 229                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 230                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 231                         >;
 232                 };
 233
 234                 pinctrl_i2c3: i2c3grp {
 235                         fsl,pins = <
 236                                 MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
 237                                 MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
 238                         >;
 239                 };
 240
 241                 pinctrl_led: ledgrp {
 242                         fsl,pins = <
 243                                 /* user led */
 244                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x80000000
 245                         >;
 246                 };
 247
 248                 pinctrl_uart1: uart1grp {
 249                         fsl,pins = <
 250                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 251                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 252                         >;
 253                 };
 254
 255                 pinctrl_uart2: uart2grp {
 256                         fsl,pins = <
 257                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 258                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 259                         >;
 260                 };
 261
 262                 pinctrl_usbh1: usbh1grp {
 263                         fsl,pins = <
 264                                 /* power enable, high active */
 265                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x10b0
 266                         >;
 267                 };
 268
 269                 pinctrl_usbotg: usbotggrp {
 270                         fsl,pins = <
 271                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 272                                 MX6QDL_PAD_EIM_D21__USB_OTG_OC          0x1b0b0
 273                                 /* power enable, high active */
 274                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x10b0
 275                         >;
 276                 };
 277
 278                 pinctrl_usdhc2: usdhc2grp {
 279                         fsl,pins = <
 280                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 281                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 282                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 283                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 284                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 285                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 286                                 /* CD */
 287                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x1b0b0
 288                                 /* WP */
 289                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x1f0b0
 290                         >;
 291                 };
 292
 293                 pinctrl_usdhc3: usdhc3grp {
 294                         fsl,pins = <
 295                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 296                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 297                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 298                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 299                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 300                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 301                                 /* CD */
 302                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x1b0b0
 303                                 /* WP */
 304                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1f0b0
 305                         >;
 306                 };
 307         };
 308 };
 309
 310 &ssi1 {
 311         status = "okay";
 312 };
 313
 314 &uart1 {
 315         pinctrl-names = "default";
 316         pinctrl-0 = <&pinctrl_uart1>;
 317         status = "okay";
 318 };
 319
 320 &uart2 {
 321         pinctrl-names = "default";
 322         pinctrl-0 = <&pinctrl_uart2>;
 323         status = "okay";
 324 };
 325
 326 &usbh1 {
 327         vbus-supply = <&reg_usbh1_vbus>;
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_usbh1>;
 330         status = "okay";
 331 };
 332
 333 &usbotg {
 334         vbus-supply = <&reg_usb_otg_vbus>;
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_usbotg>;
 337         status = "okay";
 338 };
 339
 340 &usdhc2 {
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pinctrl_usdhc2>;
 343         bus-width = <4>;
 344         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 345         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 346         status = "okay";
 347 };
 348
 349 &usdhc3 {
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&pinctrl_usdhc3>;
 352         bus-width = <4>;
 353         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 354         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 355         status = "okay";
 356 };