arch/arm/boot/dts/ls1021a.dtsi

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton64.dtsi"
  49 #include <dt-bindings/interrupt-controller/arm-gic.h>
  50
  51 / {
  52         compatible = "fsl,ls1021a";
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 crypto = &crypto;
  57                 ethernet0 = &enet0;
  58                 ethernet1 = &enet1;
  59                 ethernet2 = &enet2;
  60                 serial0 = &lpuart0;
  61                 serial1 = &lpuart1;
  62                 serial2 = &lpuart2;
  63                 serial3 = &lpuart3;
  64                 serial4 = &lpuart4;
  65                 serial5 = &lpuart5;
  66                 sysclk = &sysclk;
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 cpu@f00 {
  74                         compatible = "arm,cortex-a7";
  75                         device_type = "cpu";
  76                         reg = <0xf00>;
  77                         clocks = <&cluster1_clk>;
  78                 };
  79
  80                 cpu@f01 {
  81                         compatible = "arm,cortex-a7";
  82                         device_type = "cpu";
  83                         reg = <0xf01>;
  84                         clocks = <&cluster1_clk>;
  85                 };
  86         };
  87
  88         timer {
  89                 compatible = "arm,armv7-timer";
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  93                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  94         };
  95
  96         pmu {
  97                 compatible = "arm,cortex-a7-pmu";
  98                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  99                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 100         };
 101
 102         soc {
 103                 compatible = "simple-bus";
 104                 #address-cells = <2>;
 105                 #size-cells = <2>;
 106                 device_type = "soc";
 107                 interrupt-parent = <&gic>;
 108                 ranges;
 109
 110                 gic: interrupt-controller@1400000 {
 111                         compatible = "arm,cortex-a7-gic";
 112                         #interrupt-cells = <3>;
 113                         interrupt-controller;
 114                         reg = <0x0 0x1401000 0x0 0x1000>,
 115                               <0x0 0x1402000 0x0 0x1000>,
 116                               <0x0 0x1404000 0x0 0x2000>,
 117                               <0x0 0x1406000 0x0 0x2000>;
 118                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 119
 120                 };
 121
 122                 ifc: ifc@1530000 {
 123                         compatible = "fsl,ifc", "simple-bus";
 124                         reg = <0x0 0x1530000 0x0 0x10000>;
 125                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 126                 };
 127
 128                 dcfg: dcfg@1ee0000 {
 129                         compatible = "fsl,ls1021a-dcfg", "syscon";
 130                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 131                         big-endian;
 132                 };
 133
 134                 esdhc: esdhc@1560000 {
 135                         compatible = "fsl,esdhc";
 136                         reg = <0x0 0x1560000 0x0 0x10000>;
 137                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 138                         clock-frequency = <0>;
 139                         voltage-ranges = <1800 1800 3300 3300>;
 140                         sdhci,auto-cmd12;
 141                         big-endian;
 142                         bus-width = <4>;
 143                         status = "disabled";
 144                 };
 145
 146                 scfg: scfg@1570000 {
 147                         compatible = "fsl,ls1021a-scfg", "syscon";
 148                         reg = <0x0 0x1570000 0x0 0x10000>;
 149                         big-endian;
 150                 };
 151
 152                 crypto: crypto@1700000 {
 153                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 154                         fsl,sec-era = <7>;
 155                         #address-cells = <1>;
 156                         #size-cells = <1>;
 157                         reg              = <0x0 0x1700000 0x0 0x100000>;
 158                         ranges           = <0x0 0x0 0x1700000 0x100000>;
 159                         interrupts       = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 160
 161                         sec_jr0: jr@10000 {
 162                                 compatible = "fsl,sec-v5.0-job-ring",
 163                                      "fsl,sec-v4.0-job-ring";
 164                                 reg = <0x10000 0x10000>;
 165                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 166                         };
 167
 168                         sec_jr1: jr@20000 {
 169                                 compatible = "fsl,sec-v5.0-job-ring",
 170                                      "fsl,sec-v4.0-job-ring";
 171                                 reg = <0x20000 0x10000>;
 172                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 173                         };
 174
 175                         sec_jr2: jr@30000 {
 176                                 compatible = "fsl,sec-v5.0-job-ring",
 177                                      "fsl,sec-v4.0-job-ring";
 178                                 reg = <0x30000 0x10000>;
 179                                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 180                         };
 181
 182                         sec_jr3: jr@40000 {
 183                                 compatible = "fsl,sec-v5.0-job-ring",
 184                                      "fsl,sec-v4.0-job-ring";
 185                                 reg = <0x40000 0x10000>;
 186                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 187                         };
 188
 189                 };
 190
 191                 clockgen: clocking@1ee1000 {
 192                         #address-cells = <1>;
 193                         #size-cells = <1>;
 194                         ranges = <0x0 0x0 0x1ee1000 0x10000>;
 195
 196                         sysclk: sysclk {
 197                                 compatible = "fixed-clock";
 198                                 #clock-cells = <0>;
 199                                 clock-output-names = "sysclk";
 200                         };
 201
 202                         cga_pll1: pll@800 {
 203                                 compatible = "fsl,qoriq-core-pll-2.0";
 204                                 #clock-cells = <1>;
 205                                 reg = <0x800 0x10>;
 206                                 clocks = <&sysclk>;
 207                                 clock-output-names = "cga-pll1", "cga-pll1-div2",
 208                                                      "cga-pll1-div4";
 209                         };
 210
 211                         platform_clk: pll@c00 {
 212                                 compatible = "fsl,qoriq-core-pll-2.0";
 213                                 #clock-cells = <1>;
 214                                 reg = <0xc00 0x10>;
 215                                 clocks = <&sysclk>;
 216                                 clock-output-names = "platform-clk", "platform-clk-div2";
 217                         };
 218
 219                         cluster1_clk: clk0c0@0 {
 220                                 compatible = "fsl,qoriq-core-mux-2.0";
 221                                 #clock-cells = <0>;
 222                                 reg = <0x0 0x10>;
 223                                 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
 224                                 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
 225                                 clock-output-names = "cluster1-clk";
 226                         };
 227                 };
 228
 229                 dspi0: dspi@2100000 {
 230                         compatible = "fsl,ls1021a-v1.0-dspi";
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                         reg = <0x0 0x2100000 0x0 0x10000>;
 234                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 235                         clock-names = "dspi";
 236                         clocks = <&platform_clk 1>;
 237                         spi-num-chipselects = <5>;
 238                         big-endian;
 239                         status = "disabled";
 240                 };
 241
 242                 dspi1: dspi@2110000 {
 243                         compatible = "fsl,ls1021a-v1.0-dspi";
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         reg = <0x0 0x2110000 0x0 0x10000>;
 247                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 248                         clock-names = "dspi";
 249                         clocks = <&platform_clk 1>;
 250                         spi-num-chipselects = <5>;
 251                         big-endian;
 252                         status = "disabled";
 253                 };
 254
 255                 i2c0: i2c@2180000 {
 256                         compatible = "fsl,vf610-i2c";
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         reg = <0x0 0x2180000 0x0 0x10000>;
 260                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 261                         clock-names = "i2c";
 262                         clocks = <&platform_clk 1>;
 263                         status = "disabled";
 264                 };
 265
 266                 i2c1: i2c@2190000 {
 267                         compatible = "fsl,vf610-i2c";
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         reg = <0x0 0x2190000 0x0 0x10000>;
 271                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 272                         clock-names = "i2c";
 273                         clocks = <&platform_clk 1>;
 274                         status = "disabled";
 275                 };
 276
 277                 i2c2: i2c@21a0000 {
 278                         compatible = "fsl,vf610-i2c";
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         reg = <0x0 0x21a0000 0x0 0x10000>;
 282                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 283                         clock-names = "i2c";
 284                         clocks = <&platform_clk 1>;
 285                         status = "disabled";
 286                 };
 287
 288                 uart0: serial@21c0500 {
 289                         compatible = "fsl,16550-FIFO64", "ns16550a";
 290                         reg = <0x0 0x21c0500 0x0 0x100>;
 291                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 292                         clock-frequency = <0>;
 293                         fifo-size = <15>;
 294                         status = "disabled";
 295                 };
 296
 297                 uart1: serial@21c0600 {
 298                         compatible = "fsl,16550-FIFO64", "ns16550a";
 299                         reg = <0x0 0x21c0600 0x0 0x100>;
 300                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 301                         clock-frequency = <0>;
 302                         fifo-size = <15>;
 303                         status = "disabled";
 304                 };
 305
 306                 uart2: serial@21d0500 {
 307                         compatible = "fsl,16550-FIFO64", "ns16550a";
 308                         reg = <0x0 0x21d0500 0x0 0x100>;
 309                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 310                         clock-frequency = <0>;
 311                         fifo-size = <15>;
 312                         status = "disabled";
 313                 };
 314
 315                 uart3: serial@21d0600 {
 316                         compatible = "fsl,16550-FIFO64", "ns16550a";
 317                         reg = <0x0 0x21d0600 0x0 0x100>;
 318                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 319                         clock-frequency = <0>;
 320                         fifo-size = <15>;
 321                         status = "disabled";
 322                 };
 323
 324                 lpuart0: serial@2950000 {
 325                         compatible = "fsl,ls1021a-lpuart";
 326                         reg = <0x0 0x2950000 0x0 0x1000>;
 327                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 328                         clocks = <&sysclk>;
 329                         clock-names = "ipg";
 330                         status = "disabled";
 331                 };
 332
 333                 lpuart1: serial@2960000 {
 334                         compatible = "fsl,ls1021a-lpuart";
 335                         reg = <0x0 0x2960000 0x0 0x1000>;
 336                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&platform_clk 1>;
 338                         clock-names = "ipg";
 339                         status = "disabled";
 340                 };
 341
 342                 lpuart2: serial@2970000 {
 343                         compatible = "fsl,ls1021a-lpuart";
 344                         reg = <0x0 0x2970000 0x0 0x1000>;
 345                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&platform_clk 1>;
 347                         clock-names = "ipg";
 348                         status = "disabled";
 349                 };
 350
 351                 lpuart3: serial@2980000 {
 352                         compatible = "fsl,ls1021a-lpuart";
 353                         reg = <0x0 0x2980000 0x0 0x1000>;
 354                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&platform_clk 1>;
 356                         clock-names = "ipg";
 357                         status = "disabled";
 358                 };
 359
 360                 lpuart4: serial@2990000 {
 361                         compatible = "fsl,ls1021a-lpuart";
 362                         reg = <0x0 0x2990000 0x0 0x1000>;
 363                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 364                         clocks = <&platform_clk 1>;
 365                         clock-names = "ipg";
 366                         status = "disabled";
 367                 };
 368
 369                 lpuart5: serial@29a0000 {
 370                         compatible = "fsl,ls1021a-lpuart";
 371                         reg = <0x0 0x29a0000 0x0 0x1000>;
 372                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 373                         clocks = <&platform_clk 1>;
 374                         clock-names = "ipg";
 375                         status = "disabled";
 376                 };
 377
 378                 wdog0: watchdog@2ad0000 {
 379                         compatible = "fsl,imx21-wdt";
 380                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 381                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 382                         clocks = <&platform_clk 1>;
 383                         clock-names = "wdog-en";
 384                         big-endian;
 385                 };
 386
 387                 sai1: sai@2b50000 {
 388                         #sound-dai-cells = <0>;
 389                         compatible = "fsl,vf610-sai";
 390                         reg = <0x0 0x2b50000 0x0 0x10000>;
 391                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 392                         clocks = <&platform_clk 1>, <&platform_clk 1>,
 393                                  <&platform_clk 1>, <&platform_clk 1>;
 394                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 395                         dma-names = "tx", "rx";
 396                         dmas = <&edma0 1 47>,
 397                                <&edma0 1 46>;
 398                         status = "disabled";
 399                 };
 400
 401                 sai2: sai@2b60000 {
 402                         #sound-dai-cells = <0>;
 403                         compatible = "fsl,vf610-sai";
 404                         reg = <0x0 0x2b60000 0x0 0x10000>;
 405                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 406                         clocks = <&platform_clk 1>, <&platform_clk 1>,
 407                                  <&platform_clk 1>, <&platform_clk 1>;
 408                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 409                         dma-names = "tx", "rx";
 410                         dmas = <&edma0 1 45>,
 411                                <&edma0 1 44>;
 412                         status = "disabled";
 413                 };
 414
 415                 edma0: edma@2c00000 {
 416                         #dma-cells = <2>;
 417                         compatible = "fsl,vf610-edma";
 418                         reg = <0x0 0x2c00000 0x0 0x10000>,
 419                               <0x0 0x2c10000 0x0 0x10000>,
 420                               <0x0 0x2c20000 0x0 0x10000>;
 421                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 422                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 423                         interrupt-names = "edma-tx", "edma-err";
 424                         dma-channels = <32>;
 425                         big-endian;
 426                         clock-names = "dmamux0", "dmamux1";
 427                         clocks = <&platform_clk 1>,
 428                                  <&platform_clk 1>;
 429                 };
 430
 431                 mdio0: mdio@2d24000 {
 432                         compatible = "gianfar";
 433                         device_type = "mdio";
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         reg = <0x0 0x2d24000 0x0 0x4000>;
 437                 };
 438
 439                 enet0: ethernet@2d10000 {
 440                         compatible = "fsl,etsec2";
 441                         device_type = "network";
 442                         #address-cells = <2>;
 443                         #size-cells = <2>;
 444                         interrupt-parent = <&gic>;
 445                         model = "eTSEC";
 446                         fsl,magic-packet;
 447                         ranges;
 448                         dma-coherent;
 449
 450                         queue-group@2d10000 {
 451                                 #address-cells = <2>;
 452                                 #size-cells = <2>;
 453                                 reg = <0x0 0x2d10000 0x0 0x1000>;
 454                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 455                                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 456                                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 457                         };
 458
 459                         queue-group@2d14000  {
 460                                 #address-cells = <2>;
 461                                 #size-cells = <2>;
 462                                 reg = <0x0 0x2d14000 0x0 0x1000>;
 463                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 464                                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 465                                         <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 466                         };
 467                 };
 468
 469                 enet1: ethernet@2d50000 {
 470                         compatible = "fsl,etsec2";
 471                         device_type = "network";
 472                         #address-cells = <2>;
 473                         #size-cells = <2>;
 474                         interrupt-parent = <&gic>;
 475                         model = "eTSEC";
 476                         ranges;
 477                         dma-coherent;
 478
 479                         queue-group@2d50000  {
 480                                 #address-cells = <2>;
 481                                 #size-cells = <2>;
 482                                 reg = <0x0 0x2d50000 0x0 0x1000>;
 483                                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 484                                         <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 485                                         <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 486                         };
 487
 488                         queue-group@2d54000  {
 489                                 #address-cells = <2>;
 490                                 #size-cells = <2>;
 491                                 reg = <0x0 0x2d54000 0x0 0x1000>;
 492                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 493                                         <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 494                                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 495                         };
 496                 };
 497
 498                 enet2: ethernet@2d90000 {
 499                         compatible = "fsl,etsec2";
 500                         device_type = "network";
 501                         #address-cells = <2>;
 502                         #size-cells = <2>;
 503                         interrupt-parent = <&gic>;
 504                         model = "eTSEC";
 505                         ranges;
 506                         dma-coherent;
 507
 508                         queue-group@2d90000  {
 509                                 #address-cells = <2>;
 510                                 #size-cells = <2>;
 511                                 reg = <0x0 0x2d90000 0x0 0x1000>;
 512                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 513                                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 514                                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 515                         };
 516
 517                         queue-group@2d94000  {
 518                                 #address-cells = <2>;
 519                                 #size-cells = <2>;
 520                                 reg = <0x0 0x2d94000 0x0 0x1000>;
 521                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 522                                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 523                                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 524                         };
 525                 };
 526
 527                 usb@8600000 {
 528                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 529                         reg = <0x0 0x8600000 0x0 0x1000>;
 530                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 531                         dr_mode = "host";
 532                         phy_type = "ulpi";
 533                 };
 534
 535                 usb3@3100000 {
 536                         compatible = "snps,dwc3";
 537                         reg = <0x0 0x3100000 0x0 0x10000>;
 538                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 539                         dr_mode = "host";
 540                         snps,quirk-frame-length-adjustment = <0x20>;
 541                 };
 542         };
 543 };