arch/arm/boot/dts/ls1021a.dtsi

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton64.dtsi"
  49 #include <dt-bindings/interrupt-controller/arm-gic.h>
  50
  51 / {
  52         compatible = "fsl,ls1021a";
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 ethernet0 = &enet0;
  57                 ethernet1 = &enet1;
  58                 ethernet2 = &enet2;
  59                 serial0 = &lpuart0;
  60                 serial1 = &lpuart1;
  61                 serial2 = &lpuart2;
  62                 serial3 = &lpuart3;
  63                 serial4 = &lpuart4;
  64                 serial5 = &lpuart5;
  65                 sysclk = &sysclk;
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 cpu@f00 {
  73                         compatible = "arm,cortex-a7";
  74                         device_type = "cpu";
  75                         reg = <0xf00>;
  76                         clocks = <&cluster1_clk>;
  77                 };
  78
  79                 cpu@f01 {
  80                         compatible = "arm,cortex-a7";
  81                         device_type = "cpu";
  82                         reg = <0xf01>;
  83                         clocks = <&cluster1_clk>;
  84                 };
  85         };
  86
  87         timer {
  88                 compatible = "arm,armv7-timer";
  89                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  93         };
  94
  95         pmu {
  96                 compatible = "arm,cortex-a7-pmu";
  97                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  98                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
  99         };
 100
 101         soc {
 102                 compatible = "simple-bus";
 103                 #address-cells = <2>;
 104                 #size-cells = <2>;
 105                 device_type = "soc";
 106                 interrupt-parent = <&gic>;
 107                 ranges;
 108
 109                 gic: interrupt-controller@1400000 {
 110                         compatible = "arm,cortex-a7-gic";
 111                         #interrupt-cells = <3>;
 112                         interrupt-controller;
 113                         reg = <0x0 0x1401000 0x0 0x1000>,
 114                               <0x0 0x1402000 0x0 0x1000>,
 115                               <0x0 0x1404000 0x0 0x2000>,
 116                               <0x0 0x1406000 0x0 0x2000>;
 117                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 118
 119                 };
 120
 121                 ifc: ifc@1530000 {
 122                         compatible = "fsl,ifc", "simple-bus";
 123                         reg = <0x0 0x1530000 0x0 0x10000>;
 124                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 125                 };
 126
 127                 dcfg: dcfg@1ee0000 {
 128                         compatible = "fsl,ls1021a-dcfg", "syscon";
 129                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 130                         big-endian;
 131                 };
 132
 133                 esdhc: esdhc@1560000 {
 134                         compatible = "fsl,esdhc";
 135                         reg = <0x0 0x1560000 0x0 0x10000>;
 136                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 137                         clock-frequency = <0>;
 138                         voltage-ranges = <1800 1800 3300 3300>;
 139                         sdhci,auto-cmd12;
 140                         big-endian;
 141                         bus-width = <4>;
 142                         status = "disabled";
 143                 };
 144
 145                 scfg: scfg@1570000 {
 146                         compatible = "fsl,ls1021a-scfg", "syscon";
 147                         reg = <0x0 0x1570000 0x0 0x10000>;
 148                         big-endian;
 149                 };
 150
 151                 clockgen: clocking@1ee1000 {
 152                         #address-cells = <1>;
 153                         #size-cells = <1>;
 154                         ranges = <0x0 0x0 0x1ee1000 0x10000>;
 155
 156                         sysclk: sysclk {
 157                                 compatible = "fixed-clock";
 158                                 #clock-cells = <0>;
 159                                 clock-output-names = "sysclk";
 160                         };
 161
 162                         cga_pll1: pll@800 {
 163                                 compatible = "fsl,qoriq-core-pll-2.0";
 164                                 #clock-cells = <1>;
 165                                 reg = <0x800 0x10>;
 166                                 clocks = <&sysclk>;
 167                                 clock-output-names = "cga-pll1", "cga-pll1-div2",
 168                                                      "cga-pll1-div4";
 169                         };
 170
 171                         platform_clk: pll@c00 {
 172                                 compatible = "fsl,qoriq-core-pll-2.0";
 173                                 #clock-cells = <1>;
 174                                 reg = <0xc00 0x10>;
 175                                 clocks = <&sysclk>;
 176                                 clock-output-names = "platform-clk", "platform-clk-div2";
 177                         };
 178
 179                         cluster1_clk: clk0c0@0 {
 180                                 compatible = "fsl,qoriq-core-mux-2.0";
 181                                 #clock-cells = <0>;
 182                                 reg = <0x0 0x10>;
 183                                 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
 184                                 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
 185                                 clock-output-names = "cluster1-clk";
 186                         };
 187                 };
 188
 189                 dspi0: dspi@2100000 {
 190                         compatible = "fsl,ls1021a-v1.0-dspi";
 191                         #address-cells = <1>;
 192                         #size-cells = <0>;
 193                         reg = <0x0 0x2100000 0x0 0x10000>;
 194                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 195                         clock-names = "dspi";
 196                         clocks = <&platform_clk 1>;
 197                         spi-num-chipselects = <5>;
 198                         big-endian;
 199                         status = "disabled";
 200                 };
 201
 202                 dspi1: dspi@2110000 {
 203                         compatible = "fsl,ls1021a-v1.0-dspi";
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                         reg = <0x0 0x2110000 0x0 0x10000>;
 207                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 208                         clock-names = "dspi";
 209                         clocks = <&platform_clk 1>;
 210                         spi-num-chipselects = <5>;
 211                         big-endian;
 212                         status = "disabled";
 213                 };
 214
 215                 i2c0: i2c@2180000 {
 216                         compatible = "fsl,vf610-i2c";
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                         reg = <0x0 0x2180000 0x0 0x10000>;
 220                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 221                         clock-names = "i2c";
 222                         clocks = <&platform_clk 1>;
 223                         status = "disabled";
 224                 };
 225
 226                 i2c1: i2c@2190000 {
 227                         compatible = "fsl,vf610-i2c";
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         reg = <0x0 0x2190000 0x0 0x10000>;
 231                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 232                         clock-names = "i2c";
 233                         clocks = <&platform_clk 1>;
 234                         status = "disabled";
 235                 };
 236
 237                 i2c2: i2c@21a0000 {
 238                         compatible = "fsl,vf610-i2c";
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         reg = <0x0 0x21a0000 0x0 0x10000>;
 242                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 243                         clock-names = "i2c";
 244                         clocks = <&platform_clk 1>;
 245                         status = "disabled";
 246                 };
 247
 248                 uart0: serial@21c0500 {
 249                         compatible = "fsl,16550-FIFO64", "ns16550a";
 250                         reg = <0x0 0x21c0500 0x0 0x100>;
 251                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 252                         clock-frequency = <0>;
 253                         fifo-size = <15>;
 254                         status = "disabled";
 255                 };
 256
 257                 uart1: serial@21c0600 {
 258                         compatible = "fsl,16550-FIFO64", "ns16550a";
 259                         reg = <0x0 0x21c0600 0x0 0x100>;
 260                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 261                         clock-frequency = <0>;
 262                         fifo-size = <15>;
 263                         status = "disabled";
 264                 };
 265
 266                 uart2: serial@21d0500 {
 267                         compatible = "fsl,16550-FIFO64", "ns16550a";
 268                         reg = <0x0 0x21d0500 0x0 0x100>;
 269                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 270                         clock-frequency = <0>;
 271                         fifo-size = <15>;
 272                         status = "disabled";
 273                 };
 274
 275                 uart3: serial@21d0600 {
 276                         compatible = "fsl,16550-FIFO64", "ns16550a";
 277                         reg = <0x0 0x21d0600 0x0 0x100>;
 278                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 279                         clock-frequency = <0>;
 280                         fifo-size = <15>;
 281                         status = "disabled";
 282                 };
 283
 284                 lpuart0: serial@2950000 {
 285                         compatible = "fsl,ls1021a-lpuart";
 286                         reg = <0x0 0x2950000 0x0 0x1000>;
 287                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&sysclk>;
 289                         clock-names = "ipg";
 290                         status = "disabled";
 291                 };
 292
 293                 lpuart1: serial@2960000 {
 294                         compatible = "fsl,ls1021a-lpuart";
 295                         reg = <0x0 0x2960000 0x0 0x1000>;
 296                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 297                         clocks = <&platform_clk 1>;
 298                         clock-names = "ipg";
 299                         status = "disabled";
 300                 };
 301
 302                 lpuart2: serial@2970000 {
 303                         compatible = "fsl,ls1021a-lpuart";
 304                         reg = <0x0 0x2970000 0x0 0x1000>;
 305                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&platform_clk 1>;
 307                         clock-names = "ipg";
 308                         status = "disabled";
 309                 };
 310
 311                 lpuart3: serial@2980000 {
 312                         compatible = "fsl,ls1021a-lpuart";
 313                         reg = <0x0 0x2980000 0x0 0x1000>;
 314                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 315                         clocks = <&platform_clk 1>;
 316                         clock-names = "ipg";
 317                         status = "disabled";
 318                 };
 319
 320                 lpuart4: serial@2990000 {
 321                         compatible = "fsl,ls1021a-lpuart";
 322                         reg = <0x0 0x2990000 0x0 0x1000>;
 323                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&platform_clk 1>;
 325                         clock-names = "ipg";
 326                         status = "disabled";
 327                 };
 328
 329                 lpuart5: serial@29a0000 {
 330                         compatible = "fsl,ls1021a-lpuart";
 331                         reg = <0x0 0x29a0000 0x0 0x1000>;
 332                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&platform_clk 1>;
 334                         clock-names = "ipg";
 335                         status = "disabled";
 336                 };
 337
 338                 wdog0: watchdog@2ad0000 {
 339                         compatible = "fsl,imx21-wdt";
 340                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 341                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 342                         clocks = <&platform_clk 1>;
 343                         clock-names = "wdog-en";
 344                         big-endian;
 345                 };
 346
 347                 sai1: sai@2b50000 {
 348                         #sound-dai-cells = <0>;
 349                         compatible = "fsl,vf610-sai";
 350                         reg = <0x0 0x2b50000 0x0 0x10000>;
 351                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 352                         clocks = <&platform_clk 1>, <&platform_clk 1>,
 353                                  <&platform_clk 1>, <&platform_clk 1>;
 354                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 355                         dma-names = "tx", "rx";
 356                         dmas = <&edma0 1 47>,
 357                                <&edma0 1 46>;
 358                         status = "disabled";
 359                 };
 360
 361                 sai2: sai@2b60000 {
 362                         #sound-dai-cells = <0>;
 363                         compatible = "fsl,vf610-sai";
 364                         reg = <0x0 0x2b60000 0x0 0x10000>;
 365                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 366                         clocks = <&platform_clk 1>, <&platform_clk 1>,
 367                                  <&platform_clk 1>, <&platform_clk 1>;
 368                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 369                         dma-names = "tx", "rx";
 370                         dmas = <&edma0 1 45>,
 371                                <&edma0 1 44>;
 372                         status = "disabled";
 373                 };
 374
 375                 edma0: edma@2c00000 {
 376                         #dma-cells = <2>;
 377                         compatible = "fsl,vf610-edma";
 378                         reg = <0x0 0x2c00000 0x0 0x10000>,
 379                               <0x0 0x2c10000 0x0 0x10000>,
 380                               <0x0 0x2c20000 0x0 0x10000>;
 381                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 382                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 383                         interrupt-names = "edma-tx", "edma-err";
 384                         dma-channels = <32>;
 385                         big-endian;
 386                         clock-names = "dmamux0", "dmamux1";
 387                         clocks = <&platform_clk 1>,
 388                                  <&platform_clk 1>;
 389                 };
 390
 391                 mdio0: mdio@2d24000 {
 392                         compatible = "gianfar";
 393                         device_type = "mdio";
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         reg = <0x0 0x2d24000 0x0 0x4000>;
 397                 };
 398
 399                 enet0: ethernet@2d10000 {
 400                         compatible = "fsl,etsec2";
 401                         device_type = "network";
 402                         #address-cells = <2>;
 403                         #size-cells = <2>;
 404                         interrupt-parent = <&gic>;
 405                         model = "eTSEC";
 406                         fsl,magic-packet;
 407                         ranges;
 408
 409                         queue-group@2d10000 {
 410                                 #address-cells = <2>;
 411                                 #size-cells = <2>;
 412                                 reg = <0x0 0x2d10000 0x0 0x1000>;
 413                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 414                                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 415                                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 416                         };
 417
 418                         queue-group@2d14000  {
 419                                 #address-cells = <2>;
 420                                 #size-cells = <2>;
 421                                 reg = <0x0 0x2d14000 0x0 0x1000>;
 422                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 423                                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 424                                         <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 425                         };
 426                 };
 427
 428                 enet1: ethernet@2d50000 {
 429                         compatible = "fsl,etsec2";
 430                         device_type = "network";
 431                         #address-cells = <2>;
 432                         #size-cells = <2>;
 433                         interrupt-parent = <&gic>;
 434                         model = "eTSEC";
 435                         ranges;
 436
 437                         queue-group@2d50000  {
 438                                 #address-cells = <2>;
 439                                 #size-cells = <2>;
 440                                 reg = <0x0 0x2d50000 0x0 0x1000>;
 441                                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 442                                         <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 443                                         <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 444                         };
 445
 446                         queue-group@2d54000  {
 447                                 #address-cells = <2>;
 448                                 #size-cells = <2>;
 449                                 reg = <0x0 0x2d54000 0x0 0x1000>;
 450                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 451                                         <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 452                                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 453                         };
 454                 };
 455
 456                 enet2: ethernet@2d90000 {
 457                         compatible = "fsl,etsec2";
 458                         device_type = "network";
 459                         #address-cells = <2>;
 460                         #size-cells = <2>;
 461                         interrupt-parent = <&gic>;
 462                         model = "eTSEC";
 463                         ranges;
 464
 465                         queue-group@2d90000  {
 466                                 #address-cells = <2>;
 467                                 #size-cells = <2>;
 468                                 reg = <0x0 0x2d90000 0x0 0x1000>;
 469                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 470                                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 471                                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 472                         };
 473
 474                         queue-group@2d94000  {
 475                                 #address-cells = <2>;
 476                                 #size-cells = <2>;
 477                                 reg = <0x0 0x2d94000 0x0 0x1000>;
 478                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 479                                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 480                                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 481                         };
 482                 };
 483
 484                 usb@8600000 {
 485                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 486                         reg = <0x0 0x8600000 0x0 0x1000>;
 487                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 488                         dr_mode = "host";
 489                         phy_type = "ulpi";
 490                 };
 491
 492                 usb3@3100000 {
 493                         compatible = "snps,dwc3";
 494                         reg = <0x0 0x3100000 0x0 0x10000>;
 495                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 496                         dr_mode = "host";
 497                 };
 498         };
 499 };