arch/arm/boot/dts/mt8135.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Joe.C <yingjoe.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <dt-bindings/clock/mt8135-clk.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/reset-controller/mt8135-resets.h>
  19 #include "skeleton64.dtsi"
  20 #include "mt8135-pinfunc.h"
  21
  22 / {
  23         compatible = "mediatek,mt8135";
  24         interrupt-parent = <&sysirq>;
  25
  26         cpu-map {
  27                 cluster0 {
  28                         core0 {
  29                                 cpu = <&cpu0>;
  30                         };
  31                         core1 {
  32                                 cpu = <&cpu1>;
  33                         };
  34                 };
  35
  36                 cluster1 {
  37                         core0 {
  38                                 cpu = <&cpu2>;
  39                         };
  40                         core1 {
  41                                 cpu = <&cpu3>;
  42                         };
  43                 };
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49                 enable-method = "mediatek,mt81xx-tz-smp";
  50
  51                 cpu0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a7";
  54                         reg = <0x000>;
  55                 };
  56
  57                 cpu1: cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a7";
  60                         reg = <0x001>;
  61                 };
  62
  63                 cpu2: cpu@100 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a15";
  66                         reg = <0x100>;
  67                 };
  68
  69                 cpu3: cpu@101 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a15";
  72                         reg = <0x101>;
  73                 };
  74         };
  75
  76         reserved-memory {
  77                 #address-cells = <2>;
  78                 #size-cells = <2>;
  79                 ranges;
  80
  81                 trustzone-bootinfo@80002000 {
  82                         compatible = "mediatek,trustzone-bootinfo";
  83                         reg = <0 0x80002000 0 0x1000>;
  84                 };
  85         };
  86
  87         clocks {
  88                 #address-cells = <2>;
  89                 #size-cells = <2>;
  90                 compatible = "simple-bus";
  91                 ranges;
  92
  93                 system_clk: dummy13m {
  94                         compatible = "fixed-clock";
  95                         clock-frequency = <13000000>;
  96                         #clock-cells = <0>;
  97                 };
  98
  99                 rtc_clk: dummy32k {
 100                         compatible = "fixed-clock";
 101                         clock-frequency = <32000>;
 102                         #clock-cells = <0>;
 103                 };
 104
 105                 clk26m: clk26m {
 106                         compatible = "fixed-clock";
 107                         #clock-cells = <0>;
 108                         clock-frequency = <26000000>;
 109                 };
 110         };
 111
 112         timer {
 113                 compatible = "arm,armv7-timer";
 114                 interrupt-parent = <&gic>;
 115                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
 116                                           IRQ_TYPE_LEVEL_LOW)>,
 117                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
 118                                           IRQ_TYPE_LEVEL_LOW)>,
 119                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
 120                                           IRQ_TYPE_LEVEL_LOW)>,
 121                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 122                                           IRQ_TYPE_LEVEL_LOW)>;
 123                 clock-frequency = <13000000>;
 124                 arm,cpu-registers-not-fw-configured;
 125         };
 126
 127         soc {
 128                 #address-cells = <2>;
 129                 #size-cells = <2>;
 130                 compatible = "simple-bus";
 131                 ranges;
 132
 133                 topckgen: topckgen@10000000 {
 134                         compatible = "mediatek,mt8135-topckgen";
 135                         reg = <0 0x10000000 0 0x1000>;
 136                         #clock-cells = <1>;
 137                 };
 138
 139                 infracfg: infracfg@10001000 {
 140                         #reset-cells = <1>;
 141                         #clock-cells = <1>;
 142                         compatible = "mediatek,mt8135-infracfg", "syscon";
 143                         reg = <0 0x10001000 0 0x1000>;
 144                 };
 145
 146                 pericfg: pericfg@10003000 {
 147                         #reset-cells = <1>;
 148                         #clock-cells = <1>;
 149                         compatible = "mediatek,mt8135-pericfg", "syscon";
 150                         reg = <0 0x10003000 0 0x1000>;
 151                 };
 152
 153                 /*
 154                  * Pinctrl access register at 0x10005000 and 0x1020c000 through
 155                  * regmap. Register 0x1000b000 is used by EINT.
 156                  */
 157                 pio: pinctrl@10005000 {
 158                         compatible = "mediatek,mt8135-pinctrl";
 159                         reg = <0 0x1000b000 0 0x1000>;
 160                         mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
 161                         pins-are-numbered;
 162                         gpio-controller;
 163                         #gpio-cells = <2>;
 164                         interrupt-controller;
 165                         #interrupt-cells = <2>;
 166                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 167                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 169                 };
 170
 171                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 172                         compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
 173                         reg = <0 0x10005000 0 0x1000>;
 174                 };
 175
 176                 timer: timer@10008000 {
 177                         compatible = "mediatek,mt8135-timer",
 178                                         "mediatek,mt6577-timer";
 179                         reg = <0 0x10008000 0 0x80>;
 180                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
 181                         clocks = <&system_clk>, <&rtc_clk>;
 182                         clock-names = "system-clk", "rtc-clk";
 183                 };
 184
 185                 pwrap: pwrap@1000f000 {
 186                         compatible = "mediatek,mt8135-pwrap";
 187                         reg = <0 0x1000f000 0 0x1000>,
 188                                 <0 0x11017000 0 0x1000>;
 189                         reg-names = "pwrap", "pwrap-bridge";
 190                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 191                         resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
 192                                         <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
 193                         reset-names = "pwrap", "pwrap-bridge";
 194                         clocks = <&clk26m>, <&clk26m>;
 195                         clock-names = "spi", "wrap";
 196                 };
 197
 198                 sysirq: interrupt-controller@10200030 {
 199                         compatible = "mediatek,mt8135-sysirq",
 200                                      "mediatek,mt6577-sysirq";
 201                         interrupt-controller;
 202                         #interrupt-cells = <3>;
 203                         interrupt-parent = <&gic>;
 204                         reg = <0 0x10200030 0 0x1c>;
 205                 };
 206
 207                 apmixedsys: apmixedsys@10209000 {
 208                         compatible = "mediatek,mt8135-apmixedsys";
 209                         reg = <0 0x10209000 0 0x1000>;
 210                         #clock-cells = <1>;
 211                 };
 212
 213                 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
 214                         compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
 215                         reg = <0 0x1020c000 0 0x1000>;
 216                 };
 217
 218                 gic: interrupt-controller@10211000 {
 219                         compatible = "arm,cortex-a15-gic";
 220                         interrupt-controller;
 221                         #interrupt-cells = <3>;
 222                         interrupt-parent = <&gic>;
 223                         reg = <0 0x10211000 0 0x1000>,
 224                               <0 0x10212000 0 0x1000>,
 225                               <0 0x10214000 0 0x2000>,
 226                               <0 0x10216000 0 0x2000>;
 227                 };
 228
 229                 uart0: serial@11006000 {
 230                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 231                         reg = <0 0x11006000 0 0x400>;
 232                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 233                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 234                         clock-names = "baud", "bus";
 235                         status = "disabled";
 236                 };
 237
 238                 uart1: serial@11007000 {
 239                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 240                         reg = <0 0x11007000 0 0x400>;
 241                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 242                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 243                         clock-names = "baud", "bus";
 244                         status = "disabled";
 245                 };
 246
 247                 uart2: serial@11008000 {
 248                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 249                         reg = <0 0x11008000 0 0x400>;
 250                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 251                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 252                         clock-names = "baud", "bus";
 253                         status = "disabled";
 254                 };
 255
 256                 uart3: serial@11009000 {
 257                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 258                         reg = <0 0x11009000 0 0x400>;
 259                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 260                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 261                         clock-names = "baud", "bus";
 262                         status = "disabled";
 263                 };
 264
 265         };
 266 };