arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&wakeupgen>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 1000000 1060000
  49                                 1500000 1250000
  50                         >;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         clock-latency = <300000>; /* From omap-cpufreq driver */
  56
  57                         /* cooling options */
  58                         cooling-min-level = <0>;
  59                         cooling-max-level = <2>;
  60                         #cooling-cells = <2>; /* min followed by max */
  61                 };
  62                 cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x1>;
  66                 };
  67         };
  68
  69         thermal-zones {
  70                 #include "omap4-cpu-thermal.dtsi"
  71                 #include "omap5-gpu-thermal.dtsi"
  72                 #include "omap5-core-thermal.dtsi"
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv7-timer";
  77                 /* PPI secure/nonsecure IRQ */
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  82                 interrupt-parent = <&gic>;
  83         };
  84
  85         pmu {
  86                 compatible = "arm,cortex-a15-pmu";
  87                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  88                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  89         };
  90
  91         gic: interrupt-controller@48211000 {
  92                 compatible = "arm,cortex-a15-gic";
  93                 interrupt-controller;
  94                 #interrupt-cells = <3>;
  95                 reg = <0x48211000 0x1000>,
  96                       <0x48212000 0x1000>,
  97                       <0x48214000 0x2000>,
  98                       <0x48216000 0x2000>;
  99                 interrupt-parent = <&gic>;
 100         };
 101
 102         wakeupgen: interrupt-controller@48281000 {
 103                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 104                 interrupt-controller;
 105                 #interrupt-cells = <3>;
 106                 reg = <0x48281000 0x1000>;
 107                 interrupt-parent = <&gic>;
 108         };
 109
 110         /*
 111          * The soc node represents the soc top level view. It is used for IPs
 112          * that are not memory mapped in the MPU view or for the MPU itself.
 113          */
 114         soc {
 115                 compatible = "ti,omap-infra";
 116                 mpu {
 117                         compatible = "ti,omap4-mpu";
 118                         ti,hwmods = "mpu";
 119                         sram = <&ocmcram>;
 120                 };
 121         };
 122
 123         /*
 124          * XXX: Use a flat representation of the OMAP3 interconnect.
 125          * The real OMAP interconnect network is quite complex.
 126          * Since it will not bring real advantage to represent that in DT for
 127          * the moment, just use a fake OCP bus entry to represent the whole bus
 128          * hierarchy.
 129          */
 130         ocp {
 131                 compatible = "ti,omap5-l3-noc", "simple-bus";
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 ranges;
 135                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 136                 reg = <0x44000000 0x2000>,
 137                       <0x44800000 0x3000>,
 138                       <0x45000000 0x4000>;
 139                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 141
 142                 l4_cfg: l4@4a000000 {
 143                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 144                         #address-cells = <1>;
 145                         #size-cells = <1>;
 146                         ranges = <0 0x4a000000 0x22a000>;
 147
 148                         scm_core: scm@2000 {
 149                                 compatible = "ti,omap5-scm-core", "simple-bus";
 150                                 reg = <0x2000 0x1000>;
 151                                 #address-cells = <1>;
 152                                 #size-cells = <1>;
 153                                 ranges = <0 0x2000 0x800>;
 154
 155                                 scm_conf: scm_conf@0 {
 156                                         compatible = "syscon";
 157                                         reg = <0x0 0x800>;
 158                                         #address-cells = <1>;
 159                                         #size-cells = <1>;
 160                                 };
 161                         };
 162
 163                         scm_padconf_core: scm@2800 {
 164                                 compatible = "ti,omap5-scm-padconf-core",
 165                                              "simple-bus";
 166                                 #address-cells = <1>;
 167                                 #size-cells = <1>;
 168                                 ranges = <0 0x2800 0x800>;
 169
 170                                 omap5_pmx_core: pinmux@40 {
 171                                         compatible = "ti,omap5-padconf",
 172                                                      "pinctrl-single";
 173                                         reg = <0x40 0x01b6>;
 174                                         #address-cells = <1>;
 175                                         #size-cells = <0>;
 176                                         #interrupt-cells = <1>;
 177                                         interrupt-controller;
 178                                         pinctrl-single,register-width = <16>;
 179                                         pinctrl-single,function-mask = <0x7fff>;
 180                                 };
 181
 182                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 183                                         compatible = "syscon",
 184                                                      "simple-bus";
 185                                         reg = <0x5a0 0xec>;
 186                                         #address-cells = <1>;
 187                                         #size-cells = <1>;
 188
 189                                         pbias_regulator: pbias_regulator {
 190                                                 compatible = "ti,pbias-omap";
 191                                                 reg = <0x60 0x4>;
 192                                                 syscon = <&omap5_padconf_global>;
 193                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 194                                                         regulator-name = "pbias_mmc_omap5";
 195                                                         regulator-min-microvolt = <1800000>;
 196                                                         regulator-max-microvolt = <3000000>;
 197                                                 };
 198                                         };
 199                                 };
 200                         };
 201
 202                         cm_core_aon: cm_core_aon@4000 {
 203                                 compatible = "ti,omap5-cm-core-aon";
 204                                 reg = <0x4000 0x2000>;
 205
 206                                 cm_core_aon_clocks: clocks {
 207                                         #address-cells = <1>;
 208                                         #size-cells = <0>;
 209                                 };
 210
 211                                 cm_core_aon_clockdomains: clockdomains {
 212                                 };
 213                         };
 214
 215                         cm_core: cm_core@8000 {
 216                                 compatible = "ti,omap5-cm-core";
 217                                 reg = <0x8000 0x3000>;
 218
 219                                 cm_core_clocks: clocks {
 220                                         #address-cells = <1>;
 221                                         #size-cells = <0>;
 222                                 };
 223
 224                                 cm_core_clockdomains: clockdomains {
 225                                 };
 226                         };
 227                 };
 228
 229                 l4_wkup: l4@4ae00000 {
 230                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 231                         #address-cells = <1>;
 232                         #size-cells = <1>;
 233                         ranges = <0 0x4ae00000 0x2b000>;
 234
 235                         counter32k: counter@4000 {
 236                                 compatible = "ti,omap-counter32k";
 237                                 reg = <0x4000 0x40>;
 238                                 ti,hwmods = "counter_32k";
 239                         };
 240
 241                         prm: prm@6000 {
 242                                 compatible = "ti,omap5-prm";
 243                                 reg = <0x6000 0x3000>;
 244                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 245
 246                                 prm_clocks: clocks {
 247                                         #address-cells = <1>;
 248                                         #size-cells = <0>;
 249                                 };
 250
 251                                 prm_clockdomains: clockdomains {
 252                                 };
 253                         };
 254
 255                         scrm: scrm@a000 {
 256                                 compatible = "ti,omap5-scrm";
 257                                 reg = <0xa000 0x2000>;
 258
 259                                 scrm_clocks: clocks {
 260                                         #address-cells = <1>;
 261                                         #size-cells = <0>;
 262                                 };
 263
 264                                 scrm_clockdomains: clockdomains {
 265                                 };
 266                         };
 267
 268                         omap5_pmx_wkup: pinmux@c840 {
 269                                 compatible = "ti,omap5-padconf",
 270                                              "pinctrl-single";
 271                                 reg = <0xc840 0x0038>;
 272                                 #address-cells = <1>;
 273                                 #size-cells = <0>;
 274                                 #interrupt-cells = <1>;
 275                                 interrupt-controller;
 276                                 pinctrl-single,register-width = <16>;
 277                                 pinctrl-single,function-mask = <0x7fff>;
 278                         };
 279                 };
 280
 281                 ocmcram: ocmcram@40300000 {
 282                         compatible = "mmio-sram";
 283                         reg = <0x40300000 0x20000>; /* 128k */
 284                 };
 285
 286                 sdma: dma-controller@4a056000 {
 287                         compatible = "ti,omap4430-sdma";
 288                         reg = <0x4a056000 0x1000>;
 289                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 292                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 293                         #dma-cells = <1>;
 294                         dma-channels = <32>;
 295                         dma-requests = <127>;
 296                 };
 297
 298                 gpio1: gpio@4ae10000 {
 299                         compatible = "ti,omap4-gpio";
 300                         reg = <0x4ae10000 0x200>;
 301                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 302                         ti,hwmods = "gpio1";
 303                         ti,gpio-always-on;
 304                         gpio-controller;
 305                         #gpio-cells = <2>;
 306                         interrupt-controller;
 307                         #interrupt-cells = <2>;
 308                 };
 309
 310                 gpio2: gpio@48055000 {
 311                         compatible = "ti,omap4-gpio";
 312                         reg = <0x48055000 0x200>;
 313                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 314                         ti,hwmods = "gpio2";
 315                         gpio-controller;
 316                         #gpio-cells = <2>;
 317                         interrupt-controller;
 318                         #interrupt-cells = <2>;
 319                 };
 320
 321                 gpio3: gpio@48057000 {
 322                         compatible = "ti,omap4-gpio";
 323                         reg = <0x48057000 0x200>;
 324                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 325                         ti,hwmods = "gpio3";
 326                         gpio-controller;
 327                         #gpio-cells = <2>;
 328                         interrupt-controller;
 329                         #interrupt-cells = <2>;
 330                 };
 331
 332                 gpio4: gpio@48059000 {
 333                         compatible = "ti,omap4-gpio";
 334                         reg = <0x48059000 0x200>;
 335                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 336                         ti,hwmods = "gpio4";
 337                         gpio-controller;
 338                         #gpio-cells = <2>;
 339                         interrupt-controller;
 340                         #interrupt-cells = <2>;
 341                 };
 342
 343                 gpio5: gpio@4805b000 {
 344                         compatible = "ti,omap4-gpio";
 345                         reg = <0x4805b000 0x200>;
 346                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 347                         ti,hwmods = "gpio5";
 348                         gpio-controller;
 349                         #gpio-cells = <2>;
 350                         interrupt-controller;
 351                         #interrupt-cells = <2>;
 352                 };
 353
 354                 gpio6: gpio@4805d000 {
 355                         compatible = "ti,omap4-gpio";
 356                         reg = <0x4805d000 0x200>;
 357                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 358                         ti,hwmods = "gpio6";
 359                         gpio-controller;
 360                         #gpio-cells = <2>;
 361                         interrupt-controller;
 362                         #interrupt-cells = <2>;
 363                 };
 364
 365                 gpio7: gpio@48051000 {
 366                         compatible = "ti,omap4-gpio";
 367                         reg = <0x48051000 0x200>;
 368                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 369                         ti,hwmods = "gpio7";
 370                         gpio-controller;
 371                         #gpio-cells = <2>;
 372                         interrupt-controller;
 373                         #interrupt-cells = <2>;
 374                 };
 375
 376                 gpio8: gpio@48053000 {
 377                         compatible = "ti,omap4-gpio";
 378                         reg = <0x48053000 0x200>;
 379                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 380                         ti,hwmods = "gpio8";
 381                         gpio-controller;
 382                         #gpio-cells = <2>;
 383                         interrupt-controller;
 384                         #interrupt-cells = <2>;
 385                 };
 386
 387                 gpmc: gpmc@50000000 {
 388                         compatible = "ti,omap4430-gpmc";
 389                         reg = <0x50000000 0x1000>;
 390                         #address-cells = <2>;
 391                         #size-cells = <1>;
 392                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 393                         gpmc,num-cs = <8>;
 394                         gpmc,num-waitpins = <4>;
 395                         ti,hwmods = "gpmc";
 396                         clocks = <&l3_iclk_div>;
 397                         clock-names = "fck";
 398                 };
 399
 400                 i2c1: i2c@48070000 {
 401                         compatible = "ti,omap4-i2c";
 402                         reg = <0x48070000 0x100>;
 403                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 404                         #address-cells = <1>;
 405                         #size-cells = <0>;
 406                         ti,hwmods = "i2c1";
 407                 };
 408
 409                 i2c2: i2c@48072000 {
 410                         compatible = "ti,omap4-i2c";
 411                         reg = <0x48072000 0x100>;
 412                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         ti,hwmods = "i2c2";
 416                 };
 417
 418                 i2c3: i2c@48060000 {
 419                         compatible = "ti,omap4-i2c";
 420                         reg = <0x48060000 0x100>;
 421                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         ti,hwmods = "i2c3";
 425                 };
 426
 427                 i2c4: i2c@4807a000 {
 428                         compatible = "ti,omap4-i2c";
 429                         reg = <0x4807a000 0x100>;
 430                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         ti,hwmods = "i2c4";
 434                 };
 435
 436                 i2c5: i2c@4807c000 {
 437                         compatible = "ti,omap4-i2c";
 438                         reg = <0x4807c000 0x100>;
 439                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         ti,hwmods = "i2c5";
 443                 };
 444
 445                 hwspinlock: spinlock@4a0f6000 {
 446                         compatible = "ti,omap4-hwspinlock";
 447                         reg = <0x4a0f6000 0x1000>;
 448                         ti,hwmods = "spinlock";
 449                         #hwlock-cells = <1>;
 450                 };
 451
 452                 mcspi1: spi@48098000 {
 453                         compatible = "ti,omap4-mcspi";
 454                         reg = <0x48098000 0x200>;
 455                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         ti,hwmods = "mcspi1";
 459                         ti,spi-num-cs = <4>;
 460                         dmas = <&sdma 35>,
 461                                <&sdma 36>,
 462                                <&sdma 37>,
 463                                <&sdma 38>,
 464                                <&sdma 39>,
 465                                <&sdma 40>,
 466                                <&sdma 41>,
 467                                <&sdma 42>;
 468                         dma-names = "tx0", "rx0", "tx1", "rx1",
 469                                     "tx2", "rx2", "tx3", "rx3";
 470                 };
 471
 472                 mcspi2: spi@4809a000 {
 473                         compatible = "ti,omap4-mcspi";
 474                         reg = <0x4809a000 0x200>;
 475                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         ti,hwmods = "mcspi2";
 479                         ti,spi-num-cs = <2>;
 480                         dmas = <&sdma 43>,
 481                                <&sdma 44>,
 482                                <&sdma 45>,
 483                                <&sdma 46>;
 484                         dma-names = "tx0", "rx0", "tx1", "rx1";
 485                 };
 486
 487                 mcspi3: spi@480b8000 {
 488                         compatible = "ti,omap4-mcspi";
 489                         reg = <0x480b8000 0x200>;
 490                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         ti,hwmods = "mcspi3";
 494                         ti,spi-num-cs = <2>;
 495                         dmas = <&sdma 15>, <&sdma 16>;
 496                         dma-names = "tx0", "rx0";
 497                 };
 498
 499                 mcspi4: spi@480ba000 {
 500                         compatible = "ti,omap4-mcspi";
 501                         reg = <0x480ba000 0x200>;
 502                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         ti,hwmods = "mcspi4";
 506                         ti,spi-num-cs = <1>;
 507                         dmas = <&sdma 70>, <&sdma 71>;
 508                         dma-names = "tx0", "rx0";
 509                 };
 510
 511                 uart1: serial@4806a000 {
 512                         compatible = "ti,omap4-uart";
 513                         reg = <0x4806a000 0x100>;
 514                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 515                         ti,hwmods = "uart1";
 516                         clock-frequency = <48000000>;
 517                 };
 518
 519                 uart2: serial@4806c000 {
 520                         compatible = "ti,omap4-uart";
 521                         reg = <0x4806c000 0x100>;
 522                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 523                         ti,hwmods = "uart2";
 524                         clock-frequency = <48000000>;
 525                 };
 526
 527                 uart3: serial@48020000 {
 528                         compatible = "ti,omap4-uart";
 529                         reg = <0x48020000 0x100>;
 530                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 531                         ti,hwmods = "uart3";
 532                         clock-frequency = <48000000>;
 533                 };
 534
 535                 uart4: serial@4806e000 {
 536                         compatible = "ti,omap4-uart";
 537                         reg = <0x4806e000 0x100>;
 538                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 539                         ti,hwmods = "uart4";
 540                         clock-frequency = <48000000>;
 541                 };
 542
 543                 uart5: serial@48066000 {
 544                         compatible = "ti,omap4-uart";
 545                         reg = <0x48066000 0x100>;
 546                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 547                         ti,hwmods = "uart5";
 548                         clock-frequency = <48000000>;
 549                 };
 550
 551                 uart6: serial@48068000 {
 552                         compatible = "ti,omap4-uart";
 553                         reg = <0x48068000 0x100>;
 554                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 555                         ti,hwmods = "uart6";
 556                         clock-frequency = <48000000>;
 557                 };
 558
 559                 mmc1: mmc@4809c000 {
 560                         compatible = "ti,omap4-hsmmc";
 561                         reg = <0x4809c000 0x400>;
 562                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 563                         ti,hwmods = "mmc1";
 564                         ti,dual-volt;
 565                         ti,needs-special-reset;
 566                         dmas = <&sdma 61>, <&sdma 62>;
 567                         dma-names = "tx", "rx";
 568                         pbias-supply = <&pbias_mmc_reg>;
 569                 };
 570
 571                 mmc2: mmc@480b4000 {
 572                         compatible = "ti,omap4-hsmmc";
 573                         reg = <0x480b4000 0x400>;
 574                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 575                         ti,hwmods = "mmc2";
 576                         ti,needs-special-reset;
 577                         dmas = <&sdma 47>, <&sdma 48>;
 578                         dma-names = "tx", "rx";
 579                 };
 580
 581                 mmc3: mmc@480ad000 {
 582                         compatible = "ti,omap4-hsmmc";
 583                         reg = <0x480ad000 0x400>;
 584                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 585                         ti,hwmods = "mmc3";
 586                         ti,needs-special-reset;
 587                         dmas = <&sdma 77>, <&sdma 78>;
 588                         dma-names = "tx", "rx";
 589                 };
 590
 591                 mmc4: mmc@480d1000 {
 592                         compatible = "ti,omap4-hsmmc";
 593                         reg = <0x480d1000 0x400>;
 594                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 595                         ti,hwmods = "mmc4";
 596                         ti,needs-special-reset;
 597                         dmas = <&sdma 57>, <&sdma 58>;
 598                         dma-names = "tx", "rx";
 599                 };
 600
 601                 mmc5: mmc@480d5000 {
 602                         compatible = "ti,omap4-hsmmc";
 603                         reg = <0x480d5000 0x400>;
 604                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 605                         ti,hwmods = "mmc5";
 606                         ti,needs-special-reset;
 607                         dmas = <&sdma 59>, <&sdma 60>;
 608                         dma-names = "tx", "rx";
 609                 };
 610
 611                 mmu_dsp: mmu@4a066000 {
 612                         compatible = "ti,omap4-iommu";
 613                         reg = <0x4a066000 0x100>;
 614                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 615                         ti,hwmods = "mmu_dsp";
 616                         #iommu-cells = <0>;
 617                 };
 618
 619                 mmu_ipu: mmu@55082000 {
 620                         compatible = "ti,omap4-iommu";
 621                         reg = <0x55082000 0x100>;
 622                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 623                         ti,hwmods = "mmu_ipu";
 624                         #iommu-cells = <0>;
 625                         ti,iommu-bus-err-back;
 626                 };
 627
 628                 keypad: keypad@4ae1c000 {
 629                         compatible = "ti,omap4-keypad";
 630                         reg = <0x4ae1c000 0x400>;
 631                         ti,hwmods = "kbd";
 632                 };
 633
 634                 mcpdm: mcpdm@40132000 {
 635                         compatible = "ti,omap4-mcpdm";
 636                         reg = <0x40132000 0x7f>, /* MPU private access */
 637                               <0x49032000 0x7f>; /* L3 Interconnect */
 638                         reg-names = "mpu", "dma";
 639                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 640                         ti,hwmods = "mcpdm";
 641                         dmas = <&sdma 65>,
 642                                <&sdma 66>;
 643                         dma-names = "up_link", "dn_link";
 644                         status = "disabled";
 645                 };
 646
 647                 dmic: dmic@4012e000 {
 648                         compatible = "ti,omap4-dmic";
 649                         reg = <0x4012e000 0x7f>, /* MPU private access */
 650                               <0x4902e000 0x7f>; /* L3 Interconnect */
 651                         reg-names = "mpu", "dma";
 652                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 653                         ti,hwmods = "dmic";
 654                         dmas = <&sdma 67>;
 655                         dma-names = "up_link";
 656                         status = "disabled";
 657                 };
 658
 659                 mcbsp1: mcbsp@40122000 {
 660                         compatible = "ti,omap4-mcbsp";
 661                         reg = <0x40122000 0xff>, /* MPU private access */
 662                               <0x49022000 0xff>; /* L3 Interconnect */
 663                         reg-names = "mpu", "dma";
 664                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 665                         interrupt-names = "common";
 666                         ti,buffer-size = <128>;
 667                         ti,hwmods = "mcbsp1";
 668                         dmas = <&sdma 33>,
 669                                <&sdma 34>;
 670                         dma-names = "tx", "rx";
 671                         status = "disabled";
 672                 };
 673
 674                 mcbsp2: mcbsp@40124000 {
 675                         compatible = "ti,omap4-mcbsp";
 676                         reg = <0x40124000 0xff>, /* MPU private access */
 677                               <0x49024000 0xff>; /* L3 Interconnect */
 678                         reg-names = "mpu", "dma";
 679                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 680                         interrupt-names = "common";
 681                         ti,buffer-size = <128>;
 682                         ti,hwmods = "mcbsp2";
 683                         dmas = <&sdma 17>,
 684                                <&sdma 18>;
 685                         dma-names = "tx", "rx";
 686                         status = "disabled";
 687                 };
 688
 689                 mcbsp3: mcbsp@40126000 {
 690                         compatible = "ti,omap4-mcbsp";
 691                         reg = <0x40126000 0xff>, /* MPU private access */
 692                               <0x49026000 0xff>; /* L3 Interconnect */
 693                         reg-names = "mpu", "dma";
 694                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 695                         interrupt-names = "common";
 696                         ti,buffer-size = <128>;
 697                         ti,hwmods = "mcbsp3";
 698                         dmas = <&sdma 19>,
 699                                <&sdma 20>;
 700                         dma-names = "tx", "rx";
 701                         status = "disabled";
 702                 };
 703
 704                 mailbox: mailbox@4a0f4000 {
 705                         compatible = "ti,omap4-mailbox";
 706                         reg = <0x4a0f4000 0x200>;
 707                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 708                         ti,hwmods = "mailbox";
 709                         #mbox-cells = <1>;
 710                         ti,mbox-num-users = <3>;
 711                         ti,mbox-num-fifos = <8>;
 712                         mbox_ipu: mbox_ipu {
 713                                 ti,mbox-tx = <0 0 0>;
 714                                 ti,mbox-rx = <1 0 0>;
 715                         };
 716                         mbox_dsp: mbox_dsp {
 717                                 ti,mbox-tx = <3 0 0>;
 718                                 ti,mbox-rx = <2 0 0>;
 719                         };
 720                 };
 721
 722                 timer1: timer@4ae18000 {
 723                         compatible = "ti,omap5430-timer";
 724                         reg = <0x4ae18000 0x80>;
 725                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 726                         ti,hwmods = "timer1";
 727                         ti,timer-alwon;
 728                 };
 729
 730                 timer2: timer@48032000 {
 731                         compatible = "ti,omap5430-timer";
 732                         reg = <0x48032000 0x80>;
 733                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 734                         ti,hwmods = "timer2";
 735                 };
 736
 737                 timer3: timer@48034000 {
 738                         compatible = "ti,omap5430-timer";
 739                         reg = <0x48034000 0x80>;
 740                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 741                         ti,hwmods = "timer3";
 742                 };
 743
 744                 timer4: timer@48036000 {
 745                         compatible = "ti,omap5430-timer";
 746                         reg = <0x48036000 0x80>;
 747                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 748                         ti,hwmods = "timer4";
 749                 };
 750
 751                 timer5: timer@40138000 {
 752                         compatible = "ti,omap5430-timer";
 753                         reg = <0x40138000 0x80>,
 754                               <0x49038000 0x80>;
 755                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 756                         ti,hwmods = "timer5";
 757                         ti,timer-dsp;
 758                         ti,timer-pwm;
 759                 };
 760
 761                 timer6: timer@4013a000 {
 762                         compatible = "ti,omap5430-timer";
 763                         reg = <0x4013a000 0x80>,
 764                               <0x4903a000 0x80>;
 765                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 766                         ti,hwmods = "timer6";
 767                         ti,timer-dsp;
 768                         ti,timer-pwm;
 769                 };
 770
 771                 timer7: timer@4013c000 {
 772                         compatible = "ti,omap5430-timer";
 773                         reg = <0x4013c000 0x80>,
 774                               <0x4903c000 0x80>;
 775                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 776                         ti,hwmods = "timer7";
 777                         ti,timer-dsp;
 778                 };
 779
 780                 timer8: timer@4013e000 {
 781                         compatible = "ti,omap5430-timer";
 782                         reg = <0x4013e000 0x80>,
 783                               <0x4903e000 0x80>;
 784                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 785                         ti,hwmods = "timer8";
 786                         ti,timer-dsp;
 787                         ti,timer-pwm;
 788                 };
 789
 790                 timer9: timer@4803e000 {
 791                         compatible = "ti,omap5430-timer";
 792                         reg = <0x4803e000 0x80>;
 793                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 794                         ti,hwmods = "timer9";
 795                         ti,timer-pwm;
 796                 };
 797
 798                 timer10: timer@48086000 {
 799                         compatible = "ti,omap5430-timer";
 800                         reg = <0x48086000 0x80>;
 801                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 802                         ti,hwmods = "timer10";
 803                         ti,timer-pwm;
 804                 };
 805
 806                 timer11: timer@48088000 {
 807                         compatible = "ti,omap5430-timer";
 808                         reg = <0x48088000 0x80>;
 809                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 810                         ti,hwmods = "timer11";
 811                         ti,timer-pwm;
 812                 };
 813
 814                 wdt2: wdt@4ae14000 {
 815                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 816                         reg = <0x4ae14000 0x80>;
 817                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 818                         ti,hwmods = "wd_timer2";
 819                 };
 820
 821                 dmm@4e000000 {
 822                         compatible = "ti,omap5-dmm";
 823                         reg = <0x4e000000 0x800>;
 824                         interrupts = <0 113 0x4>;
 825                         ti,hwmods = "dmm";
 826                 };
 827
 828                 emif1: emif@4c000000 {
 829                         compatible      = "ti,emif-4d5";
 830                         ti,hwmods       = "emif1";
 831                         ti,no-idle-on-init;
 832                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 833                         reg = <0x4c000000 0x400>;
 834                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 835                         hw-caps-read-idle-ctrl;
 836                         hw-caps-ll-interface;
 837                         hw-caps-temp-alert;
 838                 };
 839
 840                 emif2: emif@4d000000 {
 841                         compatible      = "ti,emif-4d5";
 842                         ti,hwmods       = "emif2";
 843                         ti,no-idle-on-init;
 844                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 845                         reg = <0x4d000000 0x400>;
 846                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 847                         hw-caps-read-idle-ctrl;
 848                         hw-caps-ll-interface;
 849                         hw-caps-temp-alert;
 850                 };
 851
 852                 omap_control_usb2phy: control-phy@4a002300 {
 853                         compatible = "ti,control-phy-usb2";
 854                         reg = <0x4a002300 0x4>;
 855                         reg-names = "power";
 856                 };
 857
 858                 omap_control_usb3phy: control-phy@4a002370 {
 859                         compatible = "ti,control-phy-pipe3";
 860                         reg = <0x4a002370 0x4>;
 861                         reg-names = "power";
 862                 };
 863
 864                 usb3: omap_dwc3@4a020000 {
 865                         compatible = "ti,dwc3";
 866                         ti,hwmods = "usb_otg_ss";
 867                         reg = <0x4a020000 0x10000>;
 868                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 869                         #address-cells = <1>;
 870                         #size-cells = <1>;
 871                         utmi-mode = <2>;
 872                         ranges;
 873                         dwc3@4a030000 {
 874                                 compatible = "snps,dwc3";
 875                                 reg = <0x4a030000 0x10000>;
 876                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 877                                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 878                                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 879                                 interrupt-names = "peripheral",
 880                                                   "host",
 881                                                   "otg";
 882                                 phys = <&usb2_phy>, <&usb3_phy>;
 883                                 phy-names = "usb2-phy", "usb3-phy";
 884                                 dr_mode = "peripheral";
 885                                 tx-fifo-resize;
 886                         };
 887                 };
 888
 889                 ocp2scp@4a080000 {
 890                         compatible = "ti,omap-ocp2scp";
 891                         #address-cells = <1>;
 892                         #size-cells = <1>;
 893                         reg = <0x4a080000 0x20>;
 894                         ranges;
 895                         ti,hwmods = "ocp2scp1";
 896                         usb2_phy: usb2phy@4a084000 {
 897                                 compatible = "ti,omap-usb2";
 898                                 reg = <0x4a084000 0x7c>;
 899                                 ctrl-module = <&omap_control_usb2phy>;
 900                                 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 901                                 clock-names = "wkupclk", "refclk";
 902                                 #phy-cells = <0>;
 903                         };
 904
 905                         usb3_phy: usb3phy@4a084400 {
 906                                 compatible = "ti,omap-usb3";
 907                                 reg = <0x4a084400 0x80>,
 908                                       <0x4a084800 0x64>,
 909                                       <0x4a084c00 0x40>;
 910                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 911                                 ctrl-module = <&omap_control_usb3phy>;
 912                                 clocks = <&usb_phy_cm_clk32k>,
 913                                          <&sys_clkin>,
 914                                          <&usb_otg_ss_refclk960m>;
 915                                 clock-names =   "wkupclk",
 916                                                 "sysclk",
 917                                                 "refclk";
 918                                 #phy-cells = <0>;
 919                         };
 920                 };
 921
 922                 usbhstll: usbhstll@4a062000 {
 923                         compatible = "ti,usbhs-tll";
 924                         reg = <0x4a062000 0x1000>;
 925                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 926                         ti,hwmods = "usb_tll_hs";
 927                 };
 928
 929                 usbhshost: usbhshost@4a064000 {
 930                         compatible = "ti,usbhs-host";
 931                         reg = <0x4a064000 0x800>;
 932                         ti,hwmods = "usb_host_hs";
 933                         #address-cells = <1>;
 934                         #size-cells = <1>;
 935                         ranges;
 936                         clocks = <&l3init_60m_fclk>,
 937                                  <&xclk60mhsp1_ck>,
 938                                  <&xclk60mhsp2_ck>;
 939                         clock-names = "refclk_60m_int",
 940                                       "refclk_60m_ext_p1",
 941                                       "refclk_60m_ext_p2";
 942
 943                         usbhsohci: ohci@4a064800 {
 944                                 compatible = "ti,ohci-omap3";
 945                                 reg = <0x4a064800 0x400>;
 946                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 947                         };
 948
 949                         usbhsehci: ehci@4a064c00 {
 950                                 compatible = "ti,ehci-omap";
 951                                 reg = <0x4a064c00 0x400>;
 952                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 953                         };
 954                 };
 955
 956                 bandgap: bandgap@4a0021e0 {
 957                         reg = <0x4a0021e0 0xc
 958                                0x4a00232c 0xc
 959                                0x4a002380 0x2c
 960                                0x4a0023C0 0x3c>;
 961                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 962                         compatible = "ti,omap5430-bandgap";
 963
 964                         #thermal-sensor-cells = <1>;
 965                 };
 966
 967                 omap_control_sata: control-phy@4a002374 {
 968                         compatible = "ti,control-phy-pipe3";
 969                         reg = <0x4a002374 0x4>;
 970                         reg-names = "power";
 971                         clocks = <&sys_clkin>;
 972                         clock-names = "sysclk";
 973                 };
 974
 975                 /* OCP2SCP3 */
 976                 ocp2scp@4a090000 {
 977                         compatible = "ti,omap-ocp2scp";
 978                         #address-cells = <1>;
 979                         #size-cells = <1>;
 980                         reg = <0x4a090000 0x20>;
 981                         ranges;
 982                         ti,hwmods = "ocp2scp3";
 983                         sata_phy: phy@4a096000 {
 984                                 compatible = "ti,phy-pipe3-sata";
 985                                 reg = <0x4A096000 0x80>, /* phy_rx */
 986                                       <0x4A096400 0x64>, /* phy_tx */
 987                                       <0x4A096800 0x40>; /* pll_ctrl */
 988                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 989                                 ctrl-module = <&omap_control_sata>;
 990                                 clocks = <&sys_clkin>, <&sata_ref_clk>;
 991                                 clock-names = "sysclk", "refclk";
 992                                 #phy-cells = <0>;
 993                         };
 994                 };
 995
 996                 sata: sata@4a141100 {
 997                         compatible = "snps,dwc-ahci";
 998                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 999                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1000                         phys = <&sata_phy>;
1001                         phy-names = "sata-phy";
1002                         clocks = <&sata_ref_clk>;
1003                         ti,hwmods = "sata";
1004                 };
1005
1006                 dss: dss@58000000 {
1007                         compatible = "ti,omap5-dss";
1008                         reg = <0x58000000 0x80>;
1009                         status = "disabled";
1010                         ti,hwmods = "dss_core";
1011                         clocks = <&dss_dss_clk>;
1012                         clock-names = "fck";
1013                         #address-cells = <1>;
1014                         #size-cells = <1>;
1015                         ranges;
1016
1017                         dispc@58001000 {
1018                                 compatible = "ti,omap5-dispc";
1019                                 reg = <0x58001000 0x1000>;
1020                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1021                                 ti,hwmods = "dss_dispc";
1022                                 clocks = <&dss_dss_clk>;
1023                                 clock-names = "fck";
1024                         };
1025
1026                         rfbi: encoder@58002000  {
1027                                 compatible = "ti,omap5-rfbi";
1028                                 reg = <0x58002000 0x100>;
1029                                 status = "disabled";
1030                                 ti,hwmods = "dss_rfbi";
1031                                 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1032                                 clock-names = "fck", "ick";
1033                         };
1034
1035                         dsi1: encoder@58004000 {
1036                                 compatible = "ti,omap5-dsi";
1037                                 reg = <0x58004000 0x200>,
1038                                       <0x58004200 0x40>,
1039                                       <0x58004300 0x40>;
1040                                 reg-names = "proto", "phy", "pll";
1041                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1042                                 status = "disabled";
1043                                 ti,hwmods = "dss_dsi1";
1044                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1045                                 clock-names = "fck", "sys_clk";
1046                         };
1047
1048                         dsi2: encoder@58005000 {
1049                                 compatible = "ti,omap5-dsi";
1050                                 reg = <0x58009000 0x200>,
1051                                       <0x58009200 0x40>,
1052                                       <0x58009300 0x40>;
1053                                 reg-names = "proto", "phy", "pll";
1054                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1055                                 status = "disabled";
1056                                 ti,hwmods = "dss_dsi2";
1057                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1058                                 clock-names = "fck", "sys_clk";
1059                         };
1060
1061                         hdmi: encoder@58060000 {
1062                                 compatible = "ti,omap5-hdmi";
1063                                 reg = <0x58040000 0x200>,
1064                                       <0x58040200 0x80>,
1065                                       <0x58040300 0x80>,
1066                                       <0x58060000 0x19000>;
1067                                 reg-names = "wp", "pll", "phy", "core";
1068                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1069                                 status = "disabled";
1070                                 ti,hwmods = "dss_hdmi";
1071                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1072                                 clock-names = "fck", "sys_clk";
1073                                 dmas = <&sdma 76>;
1074                                 dma-names = "audio_tx";
1075                         };
1076                 };
1077
1078                 abb_mpu: regulator-abb-mpu {
1079                         compatible = "ti,abb-v2";
1080                         regulator-name = "abb_mpu";
1081                         #address-cells = <0>;
1082                         #size-cells = <0>;
1083                         clocks = <&sys_clkin>;
1084                         ti,settling-time = <50>;
1085                         ti,clock-cycles = <16>;
1086
1087                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1088                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1089                         reg-names = "base-address", "int-address",
1090                                     "efuse-address", "ldo-address";
1091                         ti,tranxdone-status-mask = <0x80>;
1092                         /* LDOVBBMPU_MUX_CTRL */
1093                         ti,ldovbb-override-mask = <0x400>;
1094                         /* LDOVBBMPU_VSET_OUT */
1095                         ti,ldovbb-vset-mask = <0x1F>;
1096
1097                         /*
1098                          * NOTE: only FBB mode used but actual vset will
1099                          * determine final biasing
1100                          */
1101                         ti,abb_info = <
1102                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1103                         1060000         0       0x0     0 0x02000000 0x01F00000
1104                         1250000         0       0x4     0 0x02000000 0x01F00000
1105                         >;
1106                 };
1107
1108                 abb_mm: regulator-abb-mm {
1109                         compatible = "ti,abb-v2";
1110                         regulator-name = "abb_mm";
1111                         #address-cells = <0>;
1112                         #size-cells = <0>;
1113                         clocks = <&sys_clkin>;
1114                         ti,settling-time = <50>;
1115                         ti,clock-cycles = <16>;
1116
1117                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1118                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1119                         reg-names = "base-address", "int-address",
1120                                     "efuse-address", "ldo-address";
1121                         ti,tranxdone-status-mask = <0x80000000>;
1122                         /* LDOVBBMM_MUX_CTRL */
1123                         ti,ldovbb-override-mask = <0x400>;
1124                         /* LDOVBBMM_VSET_OUT */
1125                         ti,ldovbb-vset-mask = <0x1F>;
1126
1127                         /*
1128                          * NOTE: only FBB mode used but actual vset will
1129                          * determine final biasing
1130                          */
1131                         ti,abb_info = <
1132                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1133                         1025000         0       0x0     0 0x02000000 0x01F00000
1134                         1120000         0       0x4     0 0x02000000 0x01F00000
1135                         >;
1136                 };
1137         };
1138 };
1139
1140 &cpu_thermal {
1141         polling-delay = <500>; /* milliseconds */
1142 };
1143
1144 /include/ "omap54xx-clocks.dtsi"