arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 / {
  10         model = "Qualcomm APQ8064";
  11         compatible = "qcom,apq8064";
  12         interrupt-parent = <&intc>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         compatible = "qcom,krait";
  20                         enable-method = "qcom,kpss-acc-v1";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         qcom,acc = <&acc0>;
  25                         qcom,saw = <&saw0>;
  26                         cpu-idle-states = <&CPU_SPC>;
  27                 };
  28
  29                 cpu@1 {
  30                         compatible = "qcom,krait";
  31                         enable-method = "qcom,kpss-acc-v1";
  32                         device_type = "cpu";
  33                         reg = <1>;
  34                         next-level-cache = <&L2>;
  35                         qcom,acc = <&acc1>;
  36                         qcom,saw = <&saw1>;
  37                         cpu-idle-states = <&CPU_SPC>;
  38                 };
  39
  40                 cpu@2 {
  41                         compatible = "qcom,krait";
  42                         enable-method = "qcom,kpss-acc-v1";
  43                         device_type = "cpu";
  44                         reg = <2>;
  45                         next-level-cache = <&L2>;
  46                         qcom,acc = <&acc2>;
  47                         qcom,saw = <&saw2>;
  48                         cpu-idle-states = <&CPU_SPC>;
  49                 };
  50
  51                 cpu@3 {
  52                         compatible = "qcom,krait";
  53                         enable-method = "qcom,kpss-acc-v1";
  54                         device_type = "cpu";
  55                         reg = <3>;
  56                         next-level-cache = <&L2>;
  57                         qcom,acc = <&acc3>;
  58                         qcom,saw = <&saw3>;
  59                         cpu-idle-states = <&CPU_SPC>;
  60                 };
  61
  62                 L2: l2-cache {
  63                         compatible = "cache";
  64                         cache-level = <2>;
  65                 };
  66
  67                 idle-states {
  68                         CPU_SPC: spc {
  69                                 compatible = "qcom,idle-state-spc",
  70                                                 "arm,idle-state";
  71                                 entry-latency-us = <400>;
  72                                 exit-latency-us = <900>;
  73                                 min-residency-us = <3000>;
  74                         };
  75                 };
  76         };
  77
  78         cpu-pmu {
  79                 compatible = "qcom,krait-pmu";
  80                 interrupts = <1 10 0x304>;
  81         };
  82
  83         soc: soc {
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 ranges;
  87                 compatible = "simple-bus";
  88
  89                 tlmm_pinmux: pinctrl@800000 {
  90                         compatible = "qcom,apq8064-pinctrl";
  91                         reg = <0x800000 0x4000>;
  92
  93                         gpio-controller;
  94                         #gpio-cells = <2>;
  95                         interrupt-controller;
  96                         #interrupt-cells = <2>;
  97                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
  98
  99                         pinctrl-names = "default";
 100                         pinctrl-0 = <&ps_hold>;
 101
 102                         sdc4_gpios: sdc4-gpios {
 103                                 pios {
 104                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 105                                         function = "sdc4";
 106                                 };
 107                         };
 108
 109                         ps_hold: ps_hold {
 110                                 mux {
 111                                         pins = "gpio78";
 112                                         function = "ps_hold";
 113                                 };
 114                         };
 115
 116                         i2c1_pins: i2c1 {
 117                                 mux {
 118                                         pins = "gpio20", "gpio21";
 119                                         function = "gsbi1";
 120                                 };
 121                         };
 122
 123                         i2c3_pins: i2c3 {
 124                                 mux {
 125                                         pins = "gpio8", "gpio9";
 126                                         function = "gsbi3";
 127                                 };
 128                         };
 129
 130                         gsbi6_uart_2pins: gsbi6_uart_2pins {
 131                                 mux {
 132                                         pins = "gpio14", "gpio15";
 133                                         function = "gsbi6";
 134                                 };
 135                         };
 136
 137                         gsbi6_uart_4pins: gsbi6_uart_4pins {
 138                                 mux {
 139                                         pins = "gpio14", "gpio15", "gpio16", "gpio17";
 140                                         function = "gsbi6";
 141                                 };
 142                         };
 143
 144                         gsbi7_uart_2pins: gsbi7_uart_2pins {
 145                                 mux {
 146                                         pins = "gpio82", "gpio83";
 147                                         function = "gsbi7";
 148                                 };
 149                         };
 150
 151                         gsbi7_uart_4pins: gsbi7_uart_4pins {
 152                                 mux {
 153                                         pins = "gpio82", "gpio83", "gpio84", "gpio85";
 154                                         function = "gsbi7";
 155                                 };
 156                         };
 157                 };
 158
 159                 intc: interrupt-controller@2000000 {
 160                         compatible = "qcom,msm-qgic2";
 161                         interrupt-controller;
 162                         #interrupt-cells = <3>;
 163                         reg = <0x02000000 0x1000>,
 164                               <0x02002000 0x1000>;
 165                 };
 166
 167                 timer@200a000 {
 168                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 169                         interrupts = <1 1 0x301>,
 170                                      <1 2 0x301>,
 171                                      <1 3 0x301>;
 172                         reg = <0x0200a000 0x100>;
 173                         clock-frequency = <27000000>,
 174                                           <32768>;
 175                         cpu-offset = <0x80000>;
 176                 };
 177
 178                 acc0: clock-controller@2088000 {
 179                         compatible = "qcom,kpss-acc-v1";
 180                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 181                 };
 182
 183                 acc1: clock-controller@2098000 {
 184                         compatible = "qcom,kpss-acc-v1";
 185                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 186                 };
 187
 188                 acc2: clock-controller@20a8000 {
 189                         compatible = "qcom,kpss-acc-v1";
 190                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 191                 };
 192
 193                 acc3: clock-controller@20b8000 {
 194                         compatible = "qcom,kpss-acc-v1";
 195                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 196                 };
 197
 198                 saw0: power-controller@2089000 {
 199                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 200                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 201                         regulator;
 202                 };
 203
 204                 saw1: power-controller@2099000 {
 205                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 206                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 207                         regulator;
 208                 };
 209
 210                 saw2: power-controller@20a9000 {
 211                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 212                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 213                         regulator;
 214                 };
 215
 216                 saw3: power-controller@20b9000 {
 217                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 218                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 219                         regulator;
 220                 };
 221
 222                 gsbi1: gsbi@12440000 {
 223                         status = "disabled";
 224                         compatible = "qcom,gsbi-v1.0.0";
 225                         cell-index = <1>;
 226                         reg = <0x12440000 0x100>;
 227                         clocks = <&gcc GSBI1_H_CLK>;
 228                         clock-names = "iface";
 229                         #address-cells = <1>;
 230                         #size-cells = <1>;
 231                         ranges;
 232
 233                         syscon-tcsr = <&tcsr>;
 234
 235                         i2c1: i2c@12460000 {
 236                                 compatible = "qcom,i2c-qup-v1.1.1";
 237                                 pinctrl-0 = <&i2c1_pins>;
 238                                 pinctrl-names = "default";
 239                                 reg = <0x12460000 0x1000>;
 240                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 241                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 242                                 clock-names = "core", "iface";
 243                                 #address-cells = <1>;
 244                                 #size-cells = <0>;
 245                         };
 246                 };
 247
 248                 gsbi2: gsbi@12480000 {
 249                         status = "disabled";
 250                         compatible = "qcom,gsbi-v1.0.0";
 251                         cell-index = <2>;
 252                         reg = <0x12480000 0x100>;
 253                         clocks = <&gcc GSBI2_H_CLK>;
 254                         clock-names = "iface";
 255                         #address-cells = <1>;
 256                         #size-cells = <1>;
 257                         ranges;
 258
 259                         syscon-tcsr = <&tcsr>;
 260
 261                         i2c2: i2c@124a0000 {
 262                                 compatible = "qcom,i2c-qup-v1.1.1";
 263                                 reg = <0x124a0000 0x1000>;
 264                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 265                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 266                                 clock-names = "core", "iface";
 267                                 #address-cells = <1>;
 268                                 #size-cells = <0>;
 269                         };
 270                 };
 271
 272                 gsbi3: gsbi@16200000 {
 273                         status = "disabled";
 274                         compatible = "qcom,gsbi-v1.0.0";
 275                         cell-index = <3>;
 276                         reg = <0x16200000 0x100>;
 277                         clocks = <&gcc GSBI3_H_CLK>;
 278                         clock-names = "iface";
 279                         #address-cells = <1>;
 280                         #size-cells = <1>;
 281                         ranges;
 282                         i2c3: i2c@16280000 {
 283                                 compatible = "qcom,i2c-qup-v1.1.1";
 284                                 pinctrl-0 = <&i2c3_pins>;
 285                                 pinctrl-names = "default";
 286                                 reg = <0x16280000 0x1000>;
 287                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 288                                 clocks = <&gcc GSBI3_QUP_CLK>,
 289                                          <&gcc GSBI3_H_CLK>;
 290                                 clock-names = "core", "iface";
 291                         };
 292                 };
 293
 294                 gsbi6: gsbi@16500000 {
 295                         status = "disabled";
 296                         compatible = "qcom,gsbi-v1.0.0";
 297                         cell-index = <6>;
 298                         reg = <0x16500000 0x03>;
 299                         clocks = <&gcc GSBI6_H_CLK>;
 300                         clock-names = "iface";
 301                         #address-cells = <1>;
 302                         #size-cells = <1>;
 303                         ranges;
 304
 305                         gsbi6_serial: serial@16540000 {
 306                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 307                                 reg = <0x16540000 0x100>,
 308                                       <0x16500000 0x03>;
 309                                 interrupts = <0 156 0x0>;
 310                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 311                                 clock-names = "core", "iface";
 312                                 status = "disabled";
 313                         };
 314                 };
 315
 316                 gsbi7: gsbi@16600000 {
 317                         status = "disabled";
 318                         compatible = "qcom,gsbi-v1.0.0";
 319                         cell-index = <7>;
 320                         reg = <0x16600000 0x100>;
 321                         clocks = <&gcc GSBI7_H_CLK>;
 322                         clock-names = "iface";
 323                         #address-cells = <1>;
 324                         #size-cells = <1>;
 325                         ranges;
 326                         syscon-tcsr = <&tcsr>;
 327
 328                         gsbi7_serial: serial@16640000 {
 329                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 330                                 reg = <0x16640000 0x1000>,
 331                                       <0x16600000 0x1000>;
 332                                 interrupts = <0 158 0x0>;
 333                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 334                                 clock-names = "core", "iface";
 335                                 status = "disabled";
 336                         };
 337                 };
 338
 339                 qcom,ssbi@500000 {
 340                         compatible = "qcom,ssbi";
 341                         reg = <0x00500000 0x1000>;
 342                         qcom,controller-type = "pmic-arbiter";
 343
 344                         pmicintc: pmic@0 {
 345                                 compatible = "qcom,pm8921";
 346                                 interrupt-parent = <&tlmm_pinmux>;
 347                                 interrupts = <74 8>;
 348                                 #interrupt-cells = <2>;
 349                                 interrupt-controller;
 350                                 #address-cells = <1>;
 351                                 #size-cells = <0>;
 352
 353                                 pm8921_gpio: gpio@150 {
 354
 355                                         compatible = "qcom,pm8921-gpio";
 356                                         reg = <0x150>;
 357                                         interrupts = <192 1>, <193 1>, <194 1>,
 358                                                      <195 1>, <196 1>, <197 1>,
 359                                                      <198 1>, <199 1>, <200 1>,
 360                                                      <201 1>, <202 1>, <203 1>,
 361                                                      <204 1>, <205 1>, <206 1>,
 362                                                      <207 1>, <208 1>, <209 1>,
 363                                                      <210 1>, <211 1>, <212 1>,
 364                                                      <213 1>, <214 1>, <215 1>,
 365                                                      <216 1>, <217 1>, <218 1>,
 366                                                      <219 1>, <220 1>, <221 1>,
 367                                                      <222 1>, <223 1>, <224 1>,
 368                                                      <225 1>, <226 1>, <227 1>,
 369                                                      <228 1>, <229 1>, <230 1>,
 370                                                      <231 1>, <232 1>, <233 1>,
 371                                                      <234 1>, <235 1>;
 372
 373                                         gpio-controller;
 374                                         #gpio-cells = <2>;
 375
 376                                 };
 377
 378                                 pm8921_mpps: mpps@50 {
 379                                         compatible = "qcom,pm8921-mpp";
 380                                         reg = <0x50>;
 381                                         gpio-controller;
 382                                         #gpio-cells = <2>;
 383                                         interrupts =
 384                                         <128 1>, <129 1>, <130 1>, <131 1>,
 385                                         <132 1>, <133 1>, <134 1>, <135 1>,
 386                                         <136 1>, <137 1>, <138 1>, <139 1>;
 387                                 };
 388
 389                                 rtc@11d {
 390                                         compatible = "qcom,pm8921-rtc";
 391                                         interrupt-parent = <&pmicintc>;
 392                                         interrupts = <39 1>;
 393                                         reg = <0x11d>;
 394                                         allow-set-time;
 395                                 };
 396
 397                                 pwrkey@1c {
 398                                         compatible = "qcom,pm8921-pwrkey";
 399                                         reg = <0x1c>;
 400                                         interrupt-parent = <&pmicintc>;
 401                                         interrupts = <50 1>, <51 1>;
 402                                         debounce = <15625>;
 403                                         pull-up;
 404                                 };
 405                         };
 406                 };
 407
 408                 gcc: clock-controller@900000 {
 409                         compatible = "qcom,gcc-apq8064";
 410                         reg = <0x00900000 0x4000>;
 411                         #clock-cells = <1>;
 412                         #reset-cells = <1>;
 413                 };
 414
 415                 lcc: clock-controller@28000000 {
 416                         compatible = "qcom,lcc-apq8064";
 417                         reg = <0x28000000 0x1000>;
 418                         #clock-cells = <1>;
 419                         #reset-cells = <1>;
 420                 };
 421
 422                 mmcc: clock-controller@4000000 {
 423                         compatible = "qcom,mmcc-apq8064";
 424                         reg = <0x4000000 0x1000>;
 425                         #clock-cells = <1>;
 426                         #reset-cells = <1>;
 427                 };
 428
 429                 l2cc: clock-controller@2011000 {
 430                         compatible      = "syscon";
 431                         reg             = <0x2011000 0x1000>;
 432                 };
 433
 434                 rpm@108000 {
 435                         compatible      = "qcom,rpm-apq8064";
 436                         reg             = <0x108000 0x1000>;
 437                         qcom,ipc        = <&l2cc 0x8 2>;
 438
 439                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 440                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 441                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 442                         interrupt-names = "ack", "err", "wakeup";
 443
 444                         regulators {
 445                                 compatible = "qcom,rpm-pm8921-regulators";
 446
 447                                 pm8921_hdmi_switch: hdmi-switch {
 448                                         bias-pull-down;
 449                                 };
 450                         };
 451                 };
 452
 453                 usb1_phy: phy@12500000 {
 454                         compatible      = "qcom,usb-otg-ci";
 455                         reg             = <0x12500000 0x400>;
 456                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 457                         status          = "disabled";
 458                         dr_mode         = "host";
 459
 460                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 461                                           <&gcc USB_HS1_H_CLK>;
 462                         clock-names     = "core", "iface";
 463
 464                         resets          = <&gcc USB_HS1_RESET>;
 465                         reset-names     = "link";
 466                 };
 467
 468                 usb3_phy: phy@12520000 {
 469                         compatible      = "qcom,usb-otg-ci";
 470                         reg             = <0x12520000 0x400>;
 471                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 472                         status          = "disabled";
 473                         dr_mode         = "host";
 474
 475                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 476                                           <&gcc USB_HS3_H_CLK>;
 477                         clock-names     = "core", "iface";
 478
 479                         resets          = <&gcc USB_HS3_RESET>;
 480                         reset-names     = "link";
 481                 };
 482
 483                 usb4_phy: phy@12530000 {
 484                         compatible      = "qcom,usb-otg-ci";
 485                         reg             = <0x12530000 0x400>;
 486                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 487                         status          = "disabled";
 488                         dr_mode         = "host";
 489
 490                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 491                                           <&gcc USB_HS4_H_CLK>;
 492                         clock-names     = "core", "iface";
 493
 494                         resets          = <&gcc USB_HS4_RESET>;
 495                         reset-names     = "link";
 496                 };
 497
 498                 gadget1: gadget@12500000 {
 499                         compatible      = "qcom,ci-hdrc";
 500                         reg             = <0x12500000 0x400>;
 501                         status          = "disabled";
 502                         dr_mode         = "peripheral";
 503                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 504                         usb-phy         = <&usb1_phy>;
 505                 };
 506
 507                 usb1: usb@12500000 {
 508                         compatible      = "qcom,ehci-host";
 509                         reg             = <0x12500000 0x400>;
 510                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 511                         status          = "disabled";
 512                         usb-phy         = <&usb1_phy>;
 513                 };
 514
 515                 usb3: usb@12520000 {
 516                         compatible      = "qcom,ehci-host";
 517                         reg             = <0x12520000 0x400>;
 518                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 519                         status          = "disabled";
 520                         usb-phy         = <&usb3_phy>;
 521                 };
 522
 523                 usb4: usb@12530000 {
 524                         compatible      = "qcom,ehci-host";
 525                         reg             = <0x12530000 0x400>;
 526                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 527                         status          = "disabled";
 528                         usb-phy         = <&usb4_phy>;
 529                 };
 530
 531                 sata_phy0: phy@1b400000 {
 532                         compatible      = "qcom,apq8064-sata-phy";
 533                         status          = "disabled";
 534                         reg             = <0x1b400000 0x200>;
 535                         reg-names       = "phy_mem";
 536                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 537                         clock-names     = "cfg";
 538                         #phy-cells      = <0>;
 539                 };
 540
 541                 sata0: sata@29000000 {
 542                         compatible              = "generic-ahci";
 543                         status                  = "disabled";
 544                         reg                     = <0x29000000 0x180>;
 545                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 546
 547                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 548                                                 <&gcc SATA_H_CLK>,
 549                                                 <&gcc SATA_A_CLK>,
 550                                                 <&gcc SATA_RXOOB_CLK>,
 551                                                 <&gcc SATA_PMALIVE_CLK>;
 552                         clock-names             = "slave_iface",
 553                                                 "iface",
 554                                                 "bus",
 555                                                 "rxoob",
 556                                                 "core_pmalive";
 557
 558                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 559                                                 <&gcc SATA_PMALIVE_CLK>;
 560                         assigned-clock-rates    = <100000000>, <100000000>;
 561
 562                         phys                    = <&sata_phy0>;
 563                         phy-names               = "sata-phy";
 564                 };
 565
 566                 /* Temporary fixed regulator */
 567                 sdcc1bam:dma@12402000{
 568                         compatible = "qcom,bam-v1.3.0";
 569                         reg = <0x12402000 0x8000>;
 570                         interrupts = <0 98 0>;
 571                         clocks = <&gcc SDC1_H_CLK>;
 572                         clock-names = "bam_clk";
 573                         #dma-cells = <1>;
 574                         qcom,ee = <0>;
 575                 };
 576
 577                 sdcc3bam:dma@12182000{
 578                         compatible = "qcom,bam-v1.3.0";
 579                         reg = <0x12182000 0x8000>;
 580                         interrupts = <0 96 0>;
 581                         clocks = <&gcc SDC3_H_CLK>;
 582                         clock-names = "bam_clk";
 583                         #dma-cells = <1>;
 584                         qcom,ee = <0>;
 585                 };
 586
 587                 sdcc4bam:dma@121c2000{
 588                         compatible = "qcom,bam-v1.3.0";
 589                         reg = <0x121c2000 0x8000>;
 590                         interrupts = <0 95 0>;
 591                         clocks = <&gcc SDC4_H_CLK>;
 592                         clock-names = "bam_clk";
 593                         #dma-cells = <1>;
 594                         qcom,ee = <0>;
 595                 };
 596
 597                 amba {
 598                         compatible = "arm,amba-bus";
 599                         #address-cells = <1>;
 600                         #size-cells = <1>;
 601                         ranges;
 602                         sdcc1: sdcc@12400000 {
 603                                 status          = "disabled";
 604                                 compatible      = "arm,pl18x", "arm,primecell";
 605                                 arm,primecell-periphid = <0x00051180>;
 606                                 reg             = <0x12400000 0x2000>;
 607                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 608                                 interrupt-names = "cmd_irq";
 609                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 610                                 clock-names     = "mclk", "apb_pclk";
 611                                 bus-width       = <8>;
 612                                 max-frequency   = <96000000>;
 613                                 non-removable;
 614                                 cap-sd-highspeed;
 615                                 cap-mmc-highspeed;
 616                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 617                                 dma-names = "tx", "rx";
 618                         };
 619
 620                         sdcc3: sdcc@12180000 {
 621                                 compatible      = "arm,pl18x", "arm,primecell";
 622                                 arm,primecell-periphid = <0x00051180>;
 623                                 status          = "disabled";
 624                                 reg             = <0x12180000 0x2000>;
 625                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 626                                 interrupt-names = "cmd_irq";
 627                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 628                                 clock-names     = "mclk", "apb_pclk";
 629                                 bus-width       = <4>;
 630                                 cap-sd-highspeed;
 631                                 cap-mmc-highspeed;
 632                                 max-frequency   = <192000000>;
 633                                 no-1-8-v;
 634                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 635                                 dma-names = "tx", "rx";
 636                         };
 637
 638                         sdcc4: sdcc@121c0000 {
 639                                 compatible      = "arm,pl18x", "arm,primecell";
 640                                 arm,primecell-periphid = <0x00051180>;
 641                                 status          = "disabled";
 642                                 reg             = <0x121c0000 0x2000>;
 643                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 644                                 interrupt-names = "cmd_irq";
 645                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 646                                 clock-names     = "mclk", "apb_pclk";
 647                                 bus-width       = <4>;
 648                                 cap-sd-highspeed;
 649                                 cap-mmc-highspeed;
 650                                 max-frequency   = <48000000>;
 651                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 652                                 dma-names = "tx", "rx";
 653                                 pinctrl-names = "default";
 654                                 pinctrl-0 = <&sdc4_gpios>;
 655                         };
 656                 };
 657
 658                 tcsr: syscon@1a400000 {
 659                         compatible = "qcom,tcsr-apq8064", "syscon";
 660                         reg = <0x1a400000 0x100>;
 661                 };
 662         };
 663 };