3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
5 #include "skeleton.dtsi"
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
17 smem_region: smem@fa00000 {
18 reg = <0xfa00000 0x200000>;
24 compatible = "simple-bus";
27 compatible = "qcom,scm";
28 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>,
29 <&gcc GCC_CE1_AHB_CLK>;
30 clock-names = "core", "bus", "iface";
37 interrupts = <1 9 0xf04>;
40 compatible = "qcom,krait";
41 enable-method = "qcom,kpss-acc-v2";
44 next-level-cache = <&L2>;
47 cpu-idle-states = <&CPU_SPC>;
51 compatible = "qcom,krait";
52 enable-method = "qcom,kpss-acc-v2";
55 next-level-cache = <&L2>;
58 cpu-idle-states = <&CPU_SPC>;
62 compatible = "qcom,krait";
63 enable-method = "qcom,kpss-acc-v2";
66 next-level-cache = <&L2>;
69 cpu-idle-states = <&CPU_SPC>;
73 compatible = "qcom,krait";
74 enable-method = "qcom,kpss-acc-v2";
77 next-level-cache = <&L2>;
80 cpu-idle-states = <&CPU_SPC>;
91 compatible = "qcom,idle-state-spc",
93 entry-latency-us = <150>;
94 exit-latency-us = <200>;
95 min-residency-us = <2000>;
101 compatible = "qcom,krait-pmu";
102 interrupts = <1 7 0xf04>;
106 compatible = "arm,armv7-timer";
107 interrupts = <1 2 0xf08>,
111 clock-frequency = <19200000>;
115 compatible = "qcom,smem";
117 memory-region = <&smem_region>;
118 qcom,rpm-msg-ram = <&rpm_msg_ram>;
120 hwlocks = <&tcsr_mutex 3>;
124 #address-cells = <1>;
127 compatible = "simple-bus";
129 intc: interrupt-controller@f9000000 {
130 compatible = "qcom,msm-qgic2";
131 interrupt-controller;
132 #interrupt-cells = <3>;
133 reg = <0xf9000000 0x1000>,
137 apcs: syscon@f9011000 {
138 compatible = "syscon";
139 reg = <0xf9011000 0x1000>;
143 #address-cells = <1>;
146 compatible = "arm,armv7-timer-mem";
147 reg = <0xf9020000 0x1000>;
148 clock-frequency = <19200000>;
152 interrupts = <0 8 0x4>,
154 reg = <0xf9021000 0x1000>,
160 interrupts = <0 9 0x4>;
161 reg = <0xf9023000 0x1000>;
167 interrupts = <0 10 0x4>;
168 reg = <0xf9024000 0x1000>;
174 interrupts = <0 11 0x4>;
175 reg = <0xf9025000 0x1000>;
181 interrupts = <0 12 0x4>;
182 reg = <0xf9026000 0x1000>;
188 interrupts = <0 13 0x4>;
189 reg = <0xf9027000 0x1000>;
195 interrupts = <0 14 0x4>;
196 reg = <0xf9028000 0x1000>;
201 saw0: power-controller@f9089000 {
202 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
203 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
206 saw1: power-controller@f9099000 {
207 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
208 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
211 saw2: power-controller@f90a9000 {
212 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
213 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
216 saw3: power-controller@f90b9000 {
217 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
218 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
221 saw_l2: power-controller@f9012000 {
222 compatible = "qcom,saw2";
223 reg = <0xf9012000 0x1000>;
227 acc0: clock-controller@f9088000 {
228 compatible = "qcom,kpss-acc-v2";
229 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
232 acc1: clock-controller@f9098000 {
233 compatible = "qcom,kpss-acc-v2";
234 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
237 acc2: clock-controller@f90a8000 {
238 compatible = "qcom,kpss-acc-v2";
239 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
242 acc3: clock-controller@f90b8000 {
243 compatible = "qcom,kpss-acc-v2";
244 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
248 compatible = "qcom,pshold";
249 reg = <0xfc4ab000 0x4>;
252 gcc: clock-controller@fc400000 {
253 compatible = "qcom,gcc-msm8974";
256 #power-domain-cells = <1>;
257 reg = <0xfc400000 0x4000>;
260 tcsr_mutex_block: syscon@fd484000 {
261 compatible = "syscon";
262 reg = <0xfd484000 0x2000>;
265 mmcc: clock-controller@fd8c0000 {
266 compatible = "qcom,mmcc-msm8974";
269 #power-domain-cells = <1>;
270 reg = <0xfd8c0000 0x6000>;
273 tcsr_mutex: tcsr-mutex {
274 compatible = "qcom,tcsr-mutex";
275 syscon = <&tcsr_mutex_block 0 0x80>;
280 rpm_msg_ram: memory@fc428000 {
281 compatible = "qcom,rpm-msg-ram";
282 reg = <0xfc428000 0x4000>;
285 blsp1_uart2: serial@f991e000 {
286 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
287 reg = <0xf991e000 0x1000>;
288 interrupts = <0 108 0x0>;
289 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
290 clock-names = "core", "iface";
295 compatible = "qcom,sdhci-msm-v4";
296 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
297 reg-names = "hc_mem", "core_mem";
298 interrupts = <0 123 0>, <0 138 0>;
299 interrupt-names = "hc_irq", "pwr_irq";
300 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
301 clock-names = "core", "iface";
306 compatible = "qcom,sdhci-msm-v4";
307 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
308 reg-names = "hc_mem", "core_mem";
309 interrupts = <0 125 0>, <0 221 0>;
310 interrupt-names = "hc_irq", "pwr_irq";
311 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
312 clock-names = "core", "iface";
317 compatible = "qcom,prng";
318 reg = <0xf9bff000 0x200>;
319 clocks = <&gcc GCC_PRNG_AHB_CLK>;
320 clock-names = "core";
323 msmgpio: pinctrl@fd510000 {
324 compatible = "qcom,msm8974-pinctrl";
325 reg = <0xfd510000 0x4000>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 interrupts = <0 208 0>;
333 blsp_i2c11: i2c@f9967000 {
335 compatible = "qcom,i2c-qup-v2.1.1";
336 reg = <0xf9967000 0x1000>;
337 interrupts = <0 105 IRQ_TYPE_NONE>;
338 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
339 clock-names = "core", "iface";
340 #address-cells = <1>;
344 spmi_bus: spmi@fc4cf000 {
345 compatible = "qcom,spmi-pmic-arb";
346 reg-names = "core", "intr", "cnfg";
347 reg = <0xfc4cf000 0x1000>,
350 interrupt-names = "periph_irq";
351 interrupts = <0 190 0>;
354 #address-cells = <2>;
356 interrupt-controller;
357 #interrupt-cells = <4>;
362 compatible = "qcom,smd";
365 interrupts = <0 168 1>;
366 qcom,ipc = <&apcs 8 0>;
367 qcom,smd-edge = <15>;
370 compatible = "qcom,rpm-msm8974";
371 qcom,smd-channels = "rpm_requests";
374 compatible = "qcom,rpm-pm8841-regulators";
387 compatible = "qcom,rpm-pm8941-regulators";
419 pm8941_lvs1: lvs1 {};
420 pm8941_lvs2: lvs2 {};
421 pm8941_lvs3: lvs3 {};
423 pm8941_5vs1: 5vs1 {};
424 pm8941_5vs2: 5vs2 {};