arch/arm/boot/dts/ste-dbx5x0.dtsi

   1 /*
   2  * Copyright 2012 Linaro Ltd
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/mfd/dbx500-prcmu.h>
  14 #include <dt-bindings/arm/ux500_pm_domains.h>
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 enable-method = "ste,dbx500-smp";
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&CPU0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&CPU1>;
  30                                 };
  31                         };
  32                 };
  33                 CPU0: cpu@300 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         reg = <0x300>;
  37                 };
  38                 CPU1: cpu@301 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a9";
  41                         reg = <0x301>;
  42                 };
  43         };
  44
  45         soc {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 compatible = "stericsson,db8500";
  49                 interrupt-parent = <&intc>;
  50                 ranges;
  51
  52                 ptm@801ae000 {
  53                         compatible = "arm,coresight-etm3x", "arm,primecell";
  54                         reg = <0x801ae000 0x1000>;
  55
  56                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  57                         clock-names = "apb_pclk", "atclk";
  58                         cpu = <&CPU0>;
  59                         port {
  60                                 ptm0_out_port: endpoint {
  61                                         remote-endpoint = <&funnel_in_port0>;
  62                                 };
  63                         };
  64                 };
  65
  66                 ptm@801af000 {
  67                         compatible = "arm,coresight-etm3x", "arm,primecell";
  68                         reg = <0x801af000 0x1000>;
  69
  70                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  71                         clock-names = "apb_pclk", "atclk";
  72                         cpu = <&CPU1>;
  73                         port {
  74                                 ptm1_out_port: endpoint {
  75                                         remote-endpoint = <&funnel_in_port1>;
  76                                 };
  77                         };
  78                 };
  79
  80                 funnel@801a6000 {
  81                         compatible = "arm,coresight-funnel", "arm,primecell";
  82                         reg = <0x801a6000 0x1000>;
  83
  84                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  85                         clock-names = "apb_pclk", "atclk";
  86                         ports {
  87                                 #address-cells = <1>;
  88                                 #size-cells = <0>;
  89
  90                                 /* funnel output ports */
  91                                 port@0 {
  92                                         reg = <0>;
  93                                         funnel_out_port: endpoint {
  94                                                 remote-endpoint =
  95                                                         <&replicator_in_port0>;
  96                                         };
  97                                 };
  98
  99                                 /* funnel input ports */
 100                                 port@1 {
 101                                         reg = <0>;
 102                                         funnel_in_port0: endpoint {
 103                                                 slave-mode;
 104                                                 remote-endpoint = <&ptm0_out_port>;
 105                                         };
 106                                 };
 107
 108                                 port@2 {
 109                                         reg = <1>;
 110                                         funnel_in_port1: endpoint {
 111                                                 slave-mode;
 112                                                 remote-endpoint = <&ptm1_out_port>;
 113                                         };
 114                                 };
 115                         };
 116                 };
 117
 118                 replicator {
 119                         compatible = "arm,coresight-replicator";
 120                         clocks = <&prcmu_clk PRCMU_APEATCLK>;
 121                         clock-names = "atclk";
 122
 123                         ports {
 124                                 #address-cells = <1>;
 125                                 #size-cells = <0>;
 126
 127                                 /* replicator output ports */
 128                                 port@0 {
 129                                         reg = <0>;
 130                                         replicator_out_port0: endpoint {
 131                                                 remote-endpoint = <&tpiu_in_port>;
 132                                         };
 133                                 };
 134                                 port@1 {
 135                                         reg = <1>;
 136                                         replicator_out_port1: endpoint {
 137                                                 remote-endpoint = <&etb_in_port>;
 138                                         };
 139                                 };
 140
 141                                 /* replicator input port */
 142                                 port@2 {
 143                                         reg = <0>;
 144                                         replicator_in_port0: endpoint {
 145                                                 slave-mode;
 146                                                 remote-endpoint = <&funnel_out_port>;
 147                                         };
 148                                 };
 149                         };
 150                 };
 151
 152                 tpiu@80190000 {
 153                         compatible = "arm,coresight-tpiu", "arm,primecell";
 154                         reg = <0x80190000 0x1000>;
 155
 156                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 157                         clock-names = "apb_pclk", "atclk";
 158                         port {
 159                                 tpiu_in_port: endpoint {
 160                                         slave-mode;
 161                                         remote-endpoint = <&replicator_out_port0>;
 162                                 };
 163                         };
 164                 };
 165
 166                 etb@801a4000 {
 167                         compatible = "arm,coresight-etb10", "arm,primecell";
 168                         reg = <0x801a4000 0x1000>;
 169
 170                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 171                         clock-names = "apb_pclk", "atclk";
 172                         port {
 173                                 etb_in_port: endpoint {
 174                                         slave-mode;
 175                                         remote-endpoint = <&replicator_out_port1>;
 176                                 };
 177                         };
 178                 };
 179
 180                 intc: interrupt-controller@a0411000 {
 181                         compatible = "arm,cortex-a9-gic";
 182                         #interrupt-cells = <3>;
 183                         #address-cells = <1>;
 184                         interrupt-controller;
 185                         reg = <0xa0411000 0x1000>,
 186                               <0xa0410100 0x100>;
 187                 };
 188
 189                 scu@a04100000 {
 190                         compatible = "arm,cortex-a9-scu";
 191                         reg = <0xa0410000 0x100>;
 192                 };
 193
 194                 /*
 195                  * The backup RAM is used for retention during sleep
 196                  * and various things like spin tables
 197                  */
 198                 backupram@80150000 {
 199                         compatible = "ste,dbx500-backupram";
 200                         reg = <0x80150000 0x2000>;
 201                 };
 202
 203                 L2: l2-cache {
 204                         compatible = "arm,pl310-cache";
 205                         reg = <0xa0412000 0x1000>;
 206                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 207                         cache-unified;
 208                         cache-level = <2>;
 209                 };
 210
 211                 pmu {
 212                         compatible = "arm,cortex-a9-pmu";
 213                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 214                 };
 215
 216                 pm_domains: pm_domains0 {
 217                         compatible = "stericsson,ux500-pm-domains";
 218                         #power-domain-cells = <1>;
 219                 };
 220
 221                 clocks {
 222                         compatible = "stericsson,u8500-clks";
 223                         /*
 224                          * Registers for the CLKRST block on peripheral
 225                          * groups 1, 2, 3, 5, 6,
 226                          */
 227                         reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
 228                             <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
 229                             <0xa03cf000 0x1000>;
 230
 231                         prcmu_clk: prcmu-clock {
 232                                 #clock-cells = <1>;
 233                         };
 234
 235                         prcc_pclk: prcc-periph-clock {
 236                                 #clock-cells = <2>;
 237                         };
 238
 239                         prcc_kclk: prcc-kernel-clock {
 240                                 #clock-cells = <2>;
 241                         };
 242
 243                         rtc_clk: rtc32k-clock {
 244                                 #clock-cells = <0>;
 245                         };
 246
 247                         smp_twd_clk: smp-twd-clock {
 248                                 #clock-cells = <0>;
 249                         };
 250                 };
 251
 252                 mtu@a03c6000 {
 253                         /* Nomadik System Timer */
 254                         compatible = "st,nomadik-mtu";
 255                         reg = <0xa03c6000 0x1000>;
 256                         interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 257
 258                         clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 259                         clock-names = "timclk", "apb_pclk";
 260                 };
 261
 262                 timer@a0410600 {
 263                         compatible = "arm,cortex-a9-twd-timer";
 264                         reg = <0xa0410600 0x20>;
 265                         interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
 266
 267                         clocks = <&smp_twd_clk>;
 268                 };
 269
 270                 watchdog@a0410620 {
 271                         compatible = "arm,cortex-a9-twd-wdt";
 272                         reg = <0xa0410620 0x20>;
 273                         interrupts = <1 14 0x304>;
 274                         clocks = <&smp_twd_clk>;
 275                 };
 276
 277                 rtc@80154000 {
 278                         compatible = "arm,rtc-pl031", "arm,primecell";
 279                         reg = <0x80154000 0x1000>;
 280                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 281
 282                         clocks = <&rtc_clk>;
 283                         clock-names = "apb_pclk";
 284                 };
 285
 286                 gpio0: gpio@8012e000 {
 287                         compatible = "stericsson,db8500-gpio",
 288                                 "st,nomadik-gpio";
 289                         reg =  <0x8012e000 0x80>;
 290                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 291                         interrupt-controller;
 292                         #interrupt-cells = <2>;
 293                         st,supports-sleepmode;
 294                         gpio-controller;
 295                         #gpio-cells = <2>;
 296                         gpio-bank = <0>;
 297                         gpio-ranges = <&pinctrl 0 0 32>;
 298                         clocks = <&prcc_pclk 1 9>;
 299                 };
 300
 301                 gpio1: gpio@8012e080 {
 302                         compatible = "stericsson,db8500-gpio",
 303                                 "st,nomadik-gpio";
 304                         reg =  <0x8012e080 0x80>;
 305                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 306                         interrupt-controller;
 307                         #interrupt-cells = <2>;
 308                         st,supports-sleepmode;
 309                         gpio-controller;
 310                         #gpio-cells = <2>;
 311                         gpio-bank = <1>;
 312                         gpio-ranges = <&pinctrl 0 32 5>;
 313                         clocks = <&prcc_pclk 1 9>;
 314                 };
 315
 316                 gpio2: gpio@8000e000 {
 317                         compatible = "stericsson,db8500-gpio",
 318                                 "st,nomadik-gpio";
 319                         reg =  <0x8000e000 0x80>;
 320                         interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
 321                         interrupt-controller;
 322                         #interrupt-cells = <2>;
 323                         st,supports-sleepmode;
 324                         gpio-controller;
 325                         #gpio-cells = <2>;
 326                         gpio-bank = <2>;
 327                         gpio-ranges = <&pinctrl 0 64 32>;
 328                         clocks = <&prcc_pclk 3 8>;
 329                 };
 330
 331                 gpio3: gpio@8000e080 {
 332                         compatible = "stericsson,db8500-gpio",
 333                                 "st,nomadik-gpio";
 334                         reg =  <0x8000e080 0x80>;
 335                         interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
 336                         interrupt-controller;
 337                         #interrupt-cells = <2>;
 338                         st,supports-sleepmode;
 339                         gpio-controller;
 340                         #gpio-cells = <2>;
 341                         gpio-bank = <3>;
 342                         gpio-ranges = <&pinctrl 0 96 2>;
 343                         clocks = <&prcc_pclk 3 8>;
 344                 };
 345
 346                 gpio4: gpio@8000e100 {
 347                         compatible = "stericsson,db8500-gpio",
 348                                 "st,nomadik-gpio";
 349                         reg =  <0x8000e100 0x80>;
 350                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 351                         interrupt-controller;
 352                         #interrupt-cells = <2>;
 353                         st,supports-sleepmode;
 354                         gpio-controller;
 355                         #gpio-cells = <2>;
 356                         gpio-bank = <4>;
 357                         gpio-ranges = <&pinctrl 0 128 32>;
 358                         clocks = <&prcc_pclk 3 8>;
 359                 };
 360
 361                 gpio5: gpio@8000e180 {
 362                         compatible = "stericsson,db8500-gpio",
 363                                 "st,nomadik-gpio";
 364                         reg =  <0x8000e180 0x80>;
 365                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 366                         interrupt-controller;
 367                         #interrupt-cells = <2>;
 368                         st,supports-sleepmode;
 369                         gpio-controller;
 370                         #gpio-cells = <2>;
 371                         gpio-bank = <5>;
 372                         gpio-ranges = <&pinctrl 0 160 12>;
 373                         clocks = <&prcc_pclk 3 8>;
 374                 };
 375
 376                 gpio6: gpio@8011e000 {
 377                         compatible = "stericsson,db8500-gpio",
 378                                 "st,nomadik-gpio";
 379                         reg =  <0x8011e000 0x80>;
 380                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 381                         interrupt-controller;
 382                         #interrupt-cells = <2>;
 383                         st,supports-sleepmode;
 384                         gpio-controller;
 385                         #gpio-cells = <2>;
 386                         gpio-bank = <6>;
 387                         gpio-ranges = <&pinctrl 0 192 32>;
 388                         clocks = <&prcc_pclk 2 11>;
 389                 };
 390
 391                 gpio7: gpio@8011e080 {
 392                         compatible = "stericsson,db8500-gpio",
 393                                 "st,nomadik-gpio";
 394                         reg =  <0x8011e080 0x80>;
 395                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 396                         interrupt-controller;
 397                         #interrupt-cells = <2>;
 398                         st,supports-sleepmode;
 399                         gpio-controller;
 400                         #gpio-cells = <2>;
 401                         gpio-bank = <7>;
 402                         gpio-ranges = <&pinctrl 0 224 7>;
 403                         clocks = <&prcc_pclk 2 11>;
 404                 };
 405
 406                 gpio8: gpio@a03fe000 {
 407                         compatible = "stericsson,db8500-gpio",
 408                                 "st,nomadik-gpio";
 409                         reg =  <0xa03fe000 0x80>;
 410                         interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
 411                         interrupt-controller;
 412                         #interrupt-cells = <2>;
 413                         st,supports-sleepmode;
 414                         gpio-controller;
 415                         #gpio-cells = <2>;
 416                         gpio-bank = <8>;
 417                         gpio-ranges = <&pinctrl 0 256 12>;
 418                         clocks = <&prcc_pclk 5 1>;
 419                 };
 420
 421                 pinctrl: pinctrl {
 422                         compatible = "stericsson,db8500-pinctrl";
 423                         nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
 424                                                 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
 425                                                 <&gpio8>;
 426                         prcm = <&prcmu>;
 427                 };
 428
 429                 usb_per5@a03e0000 {
 430                         compatible = "stericsson,db8500-musb";
 431                         reg = <0xa03e0000 0x10000>;
 432                         interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 433                         interrupt-names = "mc";
 434
 435                         dr_mode = "otg";
 436
 437                         dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
 438                                <&dma 38 0 0x0>, /* Logical - MemToDev */
 439                                <&dma 37 0 0x2>, /* Logical - DevToMem */
 440                                <&dma 37 0 0x0>, /* Logical - MemToDev */
 441                                <&dma 36 0 0x2>, /* Logical - DevToMem */
 442                                <&dma 36 0 0x0>, /* Logical - MemToDev */
 443                                <&dma 19 0 0x2>, /* Logical - DevToMem */
 444                                <&dma 19 0 0x0>, /* Logical - MemToDev */
 445                                <&dma 18 0 0x2>, /* Logical - DevToMem */
 446                                <&dma 18 0 0x0>, /* Logical - MemToDev */
 447                                <&dma 17 0 0x2>, /* Logical - DevToMem */
 448                                <&dma 17 0 0x0>, /* Logical - MemToDev */
 449                                <&dma 16 0 0x2>, /* Logical - DevToMem */
 450                                <&dma 16 0 0x0>, /* Logical - MemToDev */
 451                                <&dma 39 0 0x2>, /* Logical - DevToMem */
 452                                <&dma 39 0 0x0>; /* Logical - MemToDev */
 453
 454                         dma-names = "iep_1_9",  "oep_1_9",
 455                                     "iep_2_10", "oep_2_10",
 456                                     "iep_3_11", "oep_3_11",
 457                                     "iep_4_12", "oep_4_12",
 458                                     "iep_5_13", "oep_5_13",
 459                                     "iep_6_14", "oep_6_14",
 460                                     "iep_7_15", "oep_7_15",
 461                                     "iep_8",    "oep_8";
 462
 463                         clocks = <&prcc_pclk 5 0>;
 464                 };
 465
 466                 dma: dma-controller@801C0000 {
 467                         compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 468                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
 469                         reg-names = "base", "lcpa";
 470                         interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 471
 472                         #dma-cells = <3>;
 473                         memcpy-channels = <56 57 58 59 60>;
 474
 475                         clocks = <&prcmu_clk PRCMU_DMACLK>;
 476                 };
 477
 478                 prcmu: prcmu@80157000 {
 479                         compatible = "stericsson,db8500-prcmu";
 480                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 481                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 482                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 483                         #address-cells = <1>;
 484                         #size-cells = <1>;
 485                         interrupt-controller;
 486                         #interrupt-cells = <2>;
 487                         ranges;
 488
 489                         prcmu-timer-4@80157450 {
 490                                 compatible = "stericsson,db8500-prcmu-timer-4";
 491                                 reg = <0x80157450 0xC>;
 492                         };
 493
 494                         cpufreq {
 495                                 compatible = "stericsson,cpufreq-ux500";
 496                                 clocks = <&prcmu_clk PRCMU_ARMSS>;
 497                                 clock-names = "armss";
 498                                 status = "disabled";
 499                         };
 500
 501                         thermal@801573c0 {
 502                                 compatible = "stericsson,db8500-thermal";
 503                                 reg = <0x801573c0 0x40>;
 504                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
 505                                              <22 IRQ_TYPE_LEVEL_HIGH>;
 506                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 507                                 status = "disabled";
 508                         };
 509
 510                         db8500-prcmu-regulators {
 511                                 compatible = "stericsson,db8500-prcmu-regulator";
 512
 513                                 // DB8500_REGULATOR_VAPE
 514                                 db8500_vape_reg: db8500_vape {
 515                                         regulator-compatible = "db8500_vape";
 516                                         regulator-always-on;
 517                                 };
 518
 519                                 // DB8500_REGULATOR_VARM
 520                                 db8500_varm_reg: db8500_varm {
 521                                         regulator-compatible = "db8500_varm";
 522                                 };
 523
 524                                 // DB8500_REGULATOR_VMODEM
 525                                 db8500_vmodem_reg: db8500_vmodem {
 526                                         regulator-compatible = "db8500_vmodem";
 527                                 };
 528
 529                                 // DB8500_REGULATOR_VPLL
 530                                 db8500_vpll_reg: db8500_vpll {
 531                                         regulator-compatible = "db8500_vpll";
 532                                 };
 533
 534                                 // DB8500_REGULATOR_VSMPS1
 535                                 db8500_vsmps1_reg: db8500_vsmps1 {
 536                                         regulator-compatible = "db8500_vsmps1";
 537                                 };
 538
 539                                 // DB8500_REGULATOR_VSMPS2
 540                                 db8500_vsmps2_reg: db8500_vsmps2 {
 541                                         regulator-compatible = "db8500_vsmps2";
 542                                 };
 543
 544                                 // DB8500_REGULATOR_VSMPS3
 545                                 db8500_vsmps3_reg: db8500_vsmps3 {
 546                                         regulator-compatible = "db8500_vsmps3";
 547                                 };
 548
 549                                 // DB8500_REGULATOR_VRF1
 550                                 db8500_vrf1_reg: db8500_vrf1 {
 551                                         regulator-compatible = "db8500_vrf1";
 552                                 };
 553
 554                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
 555                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
 556                                         regulator-compatible = "db8500_sva_mmdsp";
 557                                 };
 558
 559                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
 560                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
 561                                         regulator-compatible = "db8500_sva_mmdsp_ret";
 562                                 };
 563
 564                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
 565                                 db8500_sva_pipe_reg: db8500_sva_pipe {
 566                                         regulator-compatible = "db8500_sva_pipe";
 567                                 };
 568
 569                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
 570                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
 571                                         regulator-compatible = "db8500_sia_mmdsp";
 572                                 };
 573
 574                                 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
 575                                 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
 576                                 };
 577
 578                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
 579                                 db8500_sia_pipe_reg: db8500_sia_pipe {
 580                                         regulator-compatible = "db8500_sia_pipe";
 581                                 };
 582
 583                                 // DB8500_REGULATOR_SWITCH_SGA
 584                                 db8500_sga_reg: db8500_sga {
 585                                         regulator-compatible = "db8500_sga";
 586                                         vin-supply = <&db8500_vape_reg>;
 587                                 };
 588
 589                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
 590                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
 591                                         regulator-compatible = "db8500_b2r2_mcde";
 592                                         vin-supply = <&db8500_vape_reg>;
 593                                 };
 594
 595                                 // DB8500_REGULATOR_SWITCH_ESRAM12
 596                                 db8500_esram12_reg: db8500_esram12 {
 597                                         regulator-compatible = "db8500_esram12";
 598                                 };
 599
 600                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
 601                                 db8500_esram12_ret_reg: db8500_esram12_ret {
 602                                         regulator-compatible = "db8500_esram12_ret";
 603                                 };
 604
 605                                 // DB8500_REGULATOR_SWITCH_ESRAM34
 606                                 db8500_esram34_reg: db8500_esram34 {
 607                                         regulator-compatible = "db8500_esram34";
 608                                 };
 609
 610                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
 611                                 db8500_esram34_ret_reg: db8500_esram34_ret {
 612                                         regulator-compatible = "db8500_esram34_ret";
 613                                 };
 614                         };
 615
 616                         ab8500 {
 617                                 compatible = "stericsson,ab8500";
 618                                 interrupt-parent = <&intc>;
 619                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 620                                 interrupt-controller;
 621                                 #interrupt-cells = <2>;
 622
 623                                 ab8500_gpio: ab8500-gpio {
 624                                         gpio-controller;
 625                                         #gpio-cells = <2>;
 626                                 };
 627
 628                                 ab8500-rtc {
 629                                         compatible = "stericsson,ab8500-rtc";
 630                                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH
 631                                                       18 IRQ_TYPE_LEVEL_HIGH>;
 632                                         interrupt-names = "60S", "ALARM";
 633                                 };
 634
 635                                 ab8500-gpadc {
 636                                         compatible = "stericsson,ab8500-gpadc";
 637                                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH
 638                                                       39 IRQ_TYPE_LEVEL_HIGH>;
 639                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
 640                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
 641                                 };
 642
 643                                 ab8500_battery: ab8500_battery {
 644                                         stericsson,battery-type = "LIPO";
 645                                         thermistor-on-batctrl;
 646                                 };
 647
 648                                 ab8500_fg {
 649                                         compatible = "stericsson,ab8500-fg";
 650                                         battery    = <&ab8500_battery>;
 651                                 };
 652
 653                                 ab8500_btemp {
 654                                         compatible = "stericsson,ab8500-btemp";
 655                                         battery    = <&ab8500_battery>;
 656                                 };
 657
 658                                 ab8500_charger {
 659                                         compatible      = "stericsson,ab8500-charger";
 660                                         battery         = <&ab8500_battery>;
 661                                         vddadc-supply   = <&ab8500_ldo_tvout_reg>;
 662                                 };
 663
 664                                 ab8500_chargalg {
 665                                         compatible      = "stericsson,ab8500-chargalg";
 666                                         battery         = <&ab8500_battery>;
 667                                 };
 668
 669                                 ab8500_usb {
 670                                         compatible = "stericsson,ab8500-usb";
 671                                         interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
 672                                                        96 IRQ_TYPE_LEVEL_HIGH
 673                                                        14 IRQ_TYPE_LEVEL_HIGH
 674                                                        15 IRQ_TYPE_LEVEL_HIGH
 675                                                        79 IRQ_TYPE_LEVEL_HIGH
 676                                                        74 IRQ_TYPE_LEVEL_HIGH
 677                                                        75 IRQ_TYPE_LEVEL_HIGH>;
 678                                         interrupt-names = "ID_WAKEUP_R",
 679                                                           "ID_WAKEUP_F",
 680                                                           "VBUS_DET_F",
 681                                                           "VBUS_DET_R",
 682                                                           "USB_LINK_STATUS",
 683                                                           "USB_ADP_PROBE_PLUG",
 684                                                           "USB_ADP_PROBE_UNPLUG";
 685                                         vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
 686                                         v-ape-supply = <&db8500_vape_reg>;
 687                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
 688                                 };
 689
 690                                 ab8500-ponkey {
 691                                         compatible = "stericsson,ab8500-poweron-key";
 692                                         interrupts = <6 IRQ_TYPE_LEVEL_HIGH
 693                                                       7 IRQ_TYPE_LEVEL_HIGH>;
 694                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
 695                                 };
 696
 697                                 ab8500-sysctrl {
 698                                         compatible = "stericsson,ab8500-sysctrl";
 699                                 };
 700
 701                                 ab8500-pwm {
 702                                         compatible = "stericsson,ab8500-pwm";
 703                                 };
 704
 705                                 ab8500-debugfs {
 706                                         compatible = "stericsson,ab8500-debug";
 707                                 };
 708
 709                                 codec: ab8500-codec {
 710                                         compatible = "stericsson,ab8500-codec";
 711
 712                                         V-AUD-supply = <&ab8500_ldo_audio_reg>;
 713                                         V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
 714                                         V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
 715                                         V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
 716
 717                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
 718                                 };
 719
 720                                 ext_regulators: ab8500-ext-regulators {
 721                                         compatible = "stericsson,ab8500-ext-regulator";
 722
 723                                         ab8500_ext1_reg: ab8500_ext1 {
 724                                                 regulator-compatible = "ab8500_ext1";
 725                                                 regulator-min-microvolt = <1800000>;
 726                                                 regulator-max-microvolt = <1800000>;
 727                                                 regulator-boot-on;
 728                                                 regulator-always-on;
 729                                         };
 730
 731                                         ab8500_ext2_reg: ab8500_ext2 {
 732                                                 regulator-compatible = "ab8500_ext2";
 733                                                 regulator-min-microvolt = <1360000>;
 734                                                 regulator-max-microvolt = <1360000>;
 735                                                 regulator-boot-on;
 736                                                 regulator-always-on;
 737                                         };
 738
 739                                         ab8500_ext3_reg: ab8500_ext3 {
 740                                                 regulator-compatible = "ab8500_ext3";
 741                                                 regulator-min-microvolt = <3400000>;
 742                                                 regulator-max-microvolt = <3400000>;
 743                                                 regulator-boot-on;
 744                                         };
 745                                 };
 746
 747                                 ab8500-regulators {
 748                                         compatible = "stericsson,ab8500-regulator";
 749                                         vin-supply = <&ab8500_ext3_reg>;
 750
 751                                         // supplies to the display/camera
 752                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
 753                                                 regulator-compatible = "ab8500_ldo_aux1";
 754                                                 regulator-min-microvolt = <2500000>;
 755                                                 regulator-max-microvolt = <2900000>;
 756                                                 regulator-boot-on;
 757                                                 /* BUG: If turned off MMC will be affected. */
 758                                                 regulator-always-on;
 759                                         };
 760
 761                                         // supplies to the on-board eMMC
 762                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
 763                                                 regulator-compatible = "ab8500_ldo_aux2";
 764                                                 regulator-min-microvolt = <1100000>;
 765                                                 regulator-max-microvolt = <3300000>;
 766                                         };
 767
 768                                         // supply for VAUX3; SDcard slots
 769                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
 770                                                 regulator-compatible = "ab8500_ldo_aux3";
 771                                                 regulator-min-microvolt = <1100000>;
 772                                                 regulator-max-microvolt = <3300000>;
 773                                         };
 774
 775                                         // supply for v-intcore12; VINTCORE12 LDO
 776                                         ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
 777                                                 regulator-compatible = "ab8500_ldo_intcore";
 778                                         };
 779
 780                                         // supply for tvout; gpadc; TVOUT LDO
 781                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
 782                                                 regulator-compatible = "ab8500_ldo_tvout";
 783                                         };
 784
 785                                         // supply for ab8500-usb; USB LDO
 786                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
 787                                                 regulator-compatible = "ab8500_ldo_usb";
 788                                         };
 789
 790                                         // supply for ab8500-vaudio; VAUDIO LDO
 791                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
 792                                                 regulator-compatible = "ab8500_ldo_audio";
 793                                         };
 794
 795                                         // supply for v-anamic1 VAMIC1 LDO
 796                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
 797                                                 regulator-compatible = "ab8500_ldo_anamic1";
 798                                         };
 799
 800                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
 801                                         ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 802                                                 regulator-compatible = "ab8500_ldo_anamic2";
 803                                         };
 804
 805                                         // supply for v-dmic; VDMIC LDO
 806                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
 807                                                 regulator-compatible = "ab8500_ldo_dmic";
 808                                         };
 809
 810                                         // supply for U8500 CSI/DSI; VANA LDO
 811                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
 812                                                 regulator-compatible = "ab8500_ldo_ana";
 813                                         };
 814                                 };
 815                         };
 816                 };
 817
 818                 i2c@80004000 {
 819                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 820                         reg = <0x80004000 0x1000>;
 821                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 822
 823                         #address-cells = <1>;
 824                         #size-cells = <0>;
 825                         v-i2c-supply = <&db8500_vape_reg>;
 826
 827                         clock-frequency = <400000>;
 828                         clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
 829                         clock-names = "i2cclk", "apb_pclk";
 830                         power-domains = <&pm_domains DOMAIN_VAPE>;
 831                 };
 832
 833                 i2c@80122000 {
 834                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 835                         reg = <0x80122000 0x1000>;
 836                         interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 837
 838                         #address-cells = <1>;
 839                         #size-cells = <0>;
 840                         v-i2c-supply = <&db8500_vape_reg>;
 841
 842                         clock-frequency = <400000>;
 843
 844                         clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
 845                         clock-names = "i2cclk", "apb_pclk";
 846                         power-domains = <&pm_domains DOMAIN_VAPE>;
 847                 };
 848
 849                 i2c@80128000 {
 850                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 851                         reg = <0x80128000 0x1000>;
 852                         interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 853
 854                         #address-cells = <1>;
 855                         #size-cells = <0>;
 856                         v-i2c-supply = <&db8500_vape_reg>;
 857
 858                         clock-frequency = <400000>;
 859
 860                         clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
 861                         clock-names = "i2cclk", "apb_pclk";
 862                         power-domains = <&pm_domains DOMAIN_VAPE>;
 863                 };
 864
 865                 i2c@80110000 {
 866                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 867                         reg = <0x80110000 0x1000>;
 868                         interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
 869
 870                         #address-cells = <1>;
 871                         #size-cells = <0>;
 872                         v-i2c-supply = <&db8500_vape_reg>;
 873
 874                         clock-frequency = <400000>;
 875
 876                         clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
 877                         clock-names = "i2cclk", "apb_pclk";
 878                         power-domains = <&pm_domains DOMAIN_VAPE>;
 879                 };
 880
 881                 i2c@8012a000 {
 882                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 883                         reg = <0x8012a000 0x1000>;
 884                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 885
 886                         #address-cells = <1>;
 887                         #size-cells = <0>;
 888                         v-i2c-supply = <&db8500_vape_reg>;
 889
 890                         clock-frequency = <400000>;
 891
 892                         clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
 893                         clock-names = "i2cclk", "apb_pclk";
 894                         power-domains = <&pm_domains DOMAIN_VAPE>;
 895                 };
 896
 897                 ssp@80002000 {
 898                         compatible = "arm,pl022", "arm,primecell";
 899                         reg = <0x80002000 0x1000>;
 900                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 901                         #address-cells = <1>;
 902                         #size-cells = <0>;
 903                         clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
 904                         clock-names = "SSPCLK", "apb_pclk";
 905                         dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
 906                                <&dma 8 0 0x0>; /* Logical - MemToDev */
 907                         dma-names = "rx", "tx";
 908                         power-domains = <&pm_domains DOMAIN_VAPE>;
 909                 };
 910
 911                 ssp@80003000 {
 912                         compatible = "arm,pl022", "arm,primecell";
 913                         reg = <0x80003000 0x1000>;
 914                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 915                         #address-cells = <1>;
 916                         #size-cells = <0>;
 917                         clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
 918                         clock-names = "SSPCLK", "apb_pclk";
 919                         dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
 920                                <&dma 9 0 0x0>; /* Logical - MemToDev */
 921                         dma-names = "rx", "tx";
 922                         power-domains = <&pm_domains DOMAIN_VAPE>;
 923                 };
 924
 925                 spi@8011a000 {
 926                         compatible = "arm,pl022", "arm,primecell";
 927                         reg = <0x8011a000 0x1000>;
 928                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 929                         #address-cells = <1>;
 930                         #size-cells = <0>;
 931                         /* Same clock wired to kernel and pclk */
 932                         clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
 933                         clock-names = "SSPCLK", "apb_pclk";
 934                         dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
 935                                <&dma 0 0 0x0>; /* Logical - MemToDev */
 936                         dma-names = "rx", "tx";
 937                         power-domains = <&pm_domains DOMAIN_VAPE>;
 938                 };
 939
 940                 spi@80112000 {
 941                         compatible = "arm,pl022", "arm,primecell";
 942                         reg = <0x80112000 0x1000>;
 943                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 944                         #address-cells = <1>;
 945                         #size-cells = <0>;
 946                         /* Same clock wired to kernel and pclk */
 947                         clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
 948                         clock-names = "SSPCLK", "apb_pclk";
 949                         dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
 950                                <&dma 35 0 0x0>; /* Logical - MemToDev */
 951                         dma-names = "rx", "tx";
 952                         power-domains = <&pm_domains DOMAIN_VAPE>;
 953                 };
 954
 955                 spi@80111000 {
 956                         compatible = "arm,pl022", "arm,primecell";
 957                         reg = <0x80111000 0x1000>;
 958                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 959                         #address-cells = <1>;
 960                         #size-cells = <0>;
 961                         /* Same clock wired to kernel and pclk */
 962                         clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
 963                         clock-names = "SSPCLK", "apb_pclk";
 964                         dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
 965                                <&dma 33 0 0x0>; /* Logical - MemToDev */
 966                         dma-names = "rx", "tx";
 967                         power-domains = <&pm_domains DOMAIN_VAPE>;
 968                 };
 969
 970                 spi@80129000 {
 971                         compatible = "arm,pl022", "arm,primecell";
 972                         reg = <0x80129000 0x1000>;
 973                         interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 974                         #address-cells = <1>;
 975                         #size-cells = <0>;
 976                         /* Same clock wired to kernel and pclk */
 977                         clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
 978                         clock-names = "SSPCLK", "apb_pclk";
 979                         dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
 980                                <&dma 40 0 0x0>; /* Logical - MemToDev */
 981                         dma-names = "rx", "tx";
 982                         power-domains = <&pm_domains DOMAIN_VAPE>;
 983                 };
 984
 985                 ux500_serial0: uart@80120000 {
 986                         compatible = "arm,pl011", "arm,primecell";
 987                         reg = <0x80120000 0x1000>;
 988                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 989
 990                         dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 991                                <&dma 13 0 0x0>; /* Logical - MemToDev */
 992                         dma-names = "rx", "tx";
 993
 994                         clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
 995                         clock-names = "uart", "apb_pclk";
 996
 997                         status = "disabled";
 998                 };
 999
1000                 ux500_serial1: uart@80121000 {
1001                         compatible = "arm,pl011", "arm,primecell";
1002                         reg = <0x80121000 0x1000>;
1003                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
1004
1005                         dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
1006                                <&dma 12 0 0x0>; /* Logical - MemToDev */
1007                         dma-names = "rx", "tx";
1008
1009                         clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
1010                         clock-names = "uart", "apb_pclk";
1011
1012                         status = "disabled";
1013                 };
1014
1015                 ux500_serial2: uart@80007000 {
1016                         compatible = "arm,pl011", "arm,primecell";
1017                         reg = <0x80007000 0x1000>;
1018                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
1019
1020                         dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1021                                <&dma 11 0 0x0>; /* Logical - MemToDev */
1022                         dma-names = "rx", "tx";
1023
1024                         clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1025                         clock-names = "uart", "apb_pclk";
1026
1027                         status = "disabled";
1028                 };
1029
1030                 sdi0_per1@80126000 {
1031                         compatible = "arm,pl18x", "arm,primecell";
1032                         reg = <0x80126000 0x1000>;
1033                         interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
1034
1035                         dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1036                                <&dma 29 0 0x0>; /* Logical - MemToDev */
1037                         dma-names = "rx", "tx";
1038
1039                         clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1040                         clock-names = "sdi", "apb_pclk";
1041                         power-domains = <&pm_domains DOMAIN_VAPE>;
1042
1043                         status = "disabled";
1044                 };
1045
1046                 sdi1_per2@80118000 {
1047                         compatible = "arm,pl18x", "arm,primecell";
1048                         reg = <0x80118000 0x1000>;
1049                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
1050
1051                         dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1052                                <&dma 32 0 0x0>; /* Logical - MemToDev */
1053                         dma-names = "rx", "tx";
1054
1055                         clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1056                         clock-names = "sdi", "apb_pclk";
1057                         power-domains = <&pm_domains DOMAIN_VAPE>;
1058
1059                         status = "disabled";
1060                 };
1061
1062                 sdi2_per3@80005000 {
1063                         compatible = "arm,pl18x", "arm,primecell";
1064                         reg = <0x80005000 0x1000>;
1065                         interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1066
1067                         dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1068                                <&dma 28 0 0x0>; /* Logical - MemToDev */
1069                         dma-names = "rx", "tx";
1070
1071                         clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1072                         clock-names = "sdi", "apb_pclk";
1073                         power-domains = <&pm_domains DOMAIN_VAPE>;
1074
1075                         status = "disabled";
1076                 };
1077
1078                 sdi3_per2@80119000 {
1079                         compatible = "arm,pl18x", "arm,primecell";
1080                         reg = <0x80119000 0x1000>;
1081                         interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
1082
1083                         dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1084                                <&dma 41 0 0x0>; /* Logical - MemToDev */
1085                         dma-names = "rx", "tx";
1086
1087                         clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1088                         clock-names = "sdi", "apb_pclk";
1089                         power-domains = <&pm_domains DOMAIN_VAPE>;
1090
1091                         status = "disabled";
1092                 };
1093
1094                 sdi4_per2@80114000 {
1095                         compatible = "arm,pl18x", "arm,primecell";
1096                         reg = <0x80114000 0x1000>;
1097                         interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1098
1099                         dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1100                                <&dma 42 0 0x0>; /* Logical - MemToDev */
1101                         dma-names = "rx", "tx";
1102
1103                         clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1104                         clock-names = "sdi", "apb_pclk";
1105                         power-domains = <&pm_domains DOMAIN_VAPE>;
1106
1107                         status = "disabled";
1108                 };
1109
1110                 sdi5_per3@80008000 {
1111                         compatible = "arm,pl18x", "arm,primecell";
1112                         reg = <0x80008000 0x1000>;
1113                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
1114
1115                         dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1116                                <&dma 43 0 0x0>; /* Logical - MemToDev */
1117                         dma-names = "rx", "tx";
1118
1119                         clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1120                         clock-names = "sdi", "apb_pclk";
1121                         power-domains = <&pm_domains DOMAIN_VAPE>;
1122
1123                         status = "disabled";
1124                 };
1125
1126                 msp0: msp@80123000 {
1127                         compatible = "stericsson,ux500-msp-i2s";
1128                         reg = <0x80123000 0x1000>;
1129                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
1130                         v-ape-supply = <&db8500_vape_reg>;
1131
1132                         dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1133                                <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1134                         dma-names = "rx", "tx";
1135
1136                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1137                         clock-names = "msp", "apb_pclk";
1138
1139                         status = "disabled";
1140                 };
1141
1142                 msp1: msp@80124000 {
1143                         compatible = "stericsson,ux500-msp-i2s";
1144                         reg = <0x80124000 0x1000>;
1145                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
1146                         v-ape-supply = <&db8500_vape_reg>;
1147
1148                         /* This DMA channel only exist on DB8500 v1 */
1149                         dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1150                         dma-names = "tx";
1151
1152                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1153                         clock-names = "msp", "apb_pclk";
1154
1155                         status = "disabled";
1156                 };
1157
1158                 // HDMI sound
1159                 msp2: msp@80117000 {
1160                         compatible = "stericsson,ux500-msp-i2s";
1161                         reg = <0x80117000 0x1000>;
1162                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1163                         v-ape-supply = <&db8500_vape_reg>;
1164
1165                         dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
1166                                <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1167                                                     HighPrio - Fixed */
1168                         dma-names = "rx", "tx";
1169
1170                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1171                         clock-names = "msp", "apb_pclk";
1172
1173                         status = "disabled";
1174                 };
1175
1176                 msp3: msp@80125000 {
1177                         compatible = "stericsson,ux500-msp-i2s";
1178                         reg = <0x80125000 0x1000>;
1179                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
1180                         v-ape-supply = <&db8500_vape_reg>;
1181
1182                         /* This DMA channel only exist on DB8500 v2 */
1183                         dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1184                         dma-names = "rx";
1185
1186                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1187                         clock-names = "msp", "apb_pclk";
1188
1189                         status = "disabled";
1190                 };
1191
1192                 external-bus@50000000 {
1193                         compatible = "simple-bus";
1194                         reg = <0x50000000 0x4000000>;
1195                         #address-cells = <1>;
1196                         #size-cells = <1>;
1197                         ranges = <0 0x50000000 0x4000000>;
1198                         status = "disabled";
1199                 };
1200
1201                 cpufreq-cooling {
1202                         compatible = "stericsson,db8500-cpufreq-cooling";
1203                         status = "disabled";
1204                 };
1205
1206                 mcde@a0350000 {
1207                         compatible = "stericsson,mcde";
1208                         reg = <0xa0350000 0x1000>, /* MCDE */
1209                               <0xa0351000 0x1000>, /* DSI link 1 */
1210                               <0xa0352000 0x1000>, /* DSI link 2 */
1211                               <0xa0353000 0x1000>; /* DSI link 3 */
1212                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
1213                         clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1214                                  <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1215                                  <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1216                                  <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1217                                  <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1218                                  <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1219                                  <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1220                                  <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1221                 };
1222
1223                 cryp@a03cb000 {
1224                         compatible = "stericsson,ux500-cryp";
1225                         reg = <0xa03cb000 0x1000>;
1226                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
1227
1228                         v-ape-supply = <&db8500_vape_reg>;
1229                         clocks = <&prcc_pclk 6 1>;
1230                 };
1231
1232                 hash@a03c2000 {
1233                         compatible = "stericsson,ux500-hash";
1234                         reg = <0xa03c2000 0x1000>;
1235
1236                         v-ape-supply = <&db8500_vape_reg>;
1237                         clocks = <&prcc_pclk 6 2>;
1238                 };
1239         };
1240 };