arch/arm/boot/dts/stih407-family.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih407-pinctrl.dtsi"
  10 #include <dt-bindings/mfd/st-lpc.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/reset/stih407-resets.h>
  13 #include <dt-bindings/interrupt-controller/irq-st.h>
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         reg = <0>;
  25                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  26                         cpu-release-addr = <0x94100A4>;
  27                 };
  28                 cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a9";
  31                         reg = <1>;
  32                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  33                         cpu-release-addr = <0x94100A4>;
  34                 };
  35         };
  36
  37         intc: interrupt-controller@08761000 {
  38                 compatible = "arm,cortex-a9-gic";
  39                 #interrupt-cells = <3>;
  40                 interrupt-controller;
  41                 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
  42         };
  43
  44         scu@08760000 {
  45                 compatible = "arm,cortex-a9-scu";
  46                 reg = <0x08760000 0x1000>;
  47         };
  48
  49         timer@08760200 {
  50                 interrupt-parent = <&intc>;
  51                 compatible = "arm,cortex-a9-global-timer";
  52                 reg = <0x08760200 0x100>;
  53                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  54                 clocks = <&arm_periph_clk>;
  55         };
  56
  57         l2: cache-controller {
  58                 compatible = "arm,pl310-cache";
  59                 reg = <0x08762000 0x1000>;
  60                 arm,data-latency = <3 3 3>;
  61                 arm,tag-latency = <2 2 2>;
  62                 cache-unified;
  63                 cache-level = <2>;
  64         };
  65
  66         arm-pmu {
  67                 interrupt-parent = <&intc>;
  68                 compatible = "arm,cortex-a9-pmu";
  69                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
  70         };
  71
  72         pwm_regulator: pwm-regulator {
  73                 compatible = "pwm-regulator";
  74                 pwms = <&pwm1 3 8448>;
  75                 regulator-name = "CPU_1V0_AVS";
  76                 regulator-min-microvolt = <784000>;
  77                 regulator-max-microvolt = <1299000>;
  78                 regulator-always-on;
  79                 max-duty-cycle = <255>;
  80                 status = "okay";
  81         };
  82
  83         soc {
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 interrupt-parent = <&intc>;
  87                 ranges;
  88                 compatible = "simple-bus";
  89
  90                 restart {
  91                         compatible = "st,stih407-restart";
  92                         st,syscfg = <&syscfg_sbc_reg>;
  93                         status = "okay";
  94                 };
  95
  96                 powerdown: powerdown-controller {
  97                         compatible = "st,stih407-powerdown";
  98                         #reset-cells = <1>;
  99                 };
 100
 101                 softreset: softreset-controller {
 102                         compatible = "st,stih407-softreset";
 103                         #reset-cells = <1>;
 104                 };
 105
 106                 picophyreset: picophyreset-controller {
 107                         compatible = "st,stih407-picophyreset";
 108                         #reset-cells = <1>;
 109                 };
 110
 111                 syscfg_sbc: sbc-syscfg@9620000 {
 112                         compatible = "st,stih407-sbc-syscfg", "syscon";
 113                         reg = <0x9620000 0x1000>;
 114                 };
 115
 116                 syscfg_front: front-syscfg@9280000 {
 117                         compatible = "st,stih407-front-syscfg", "syscon";
 118                         reg = <0x9280000 0x1000>;
 119                 };
 120
 121                 syscfg_rear: rear-syscfg@9290000 {
 122                         compatible = "st,stih407-rear-syscfg", "syscon";
 123                         reg = <0x9290000 0x1000>;
 124                 };
 125
 126                 syscfg_flash: flash-syscfg@92a0000 {
 127                         compatible = "st,stih407-flash-syscfg", "syscon";
 128                         reg = <0x92a0000 0x1000>;
 129                 };
 130
 131                 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
 132                         compatible = "st,stih407-sbc-reg-syscfg", "syscon";
 133                         reg = <0x9600000 0x1000>;
 134                 };
 135
 136                 syscfg_core: core-syscfg@92b0000 {
 137                         compatible = "st,stih407-core-syscfg", "syscon";
 138                         reg = <0x92b0000 0x1000>;
 139                 };
 140
 141                 syscfg_lpm: lpm-syscfg@94b5100 {
 142                         compatible = "st,stih407-lpm-syscfg", "syscon";
 143                         reg = <0x94b5100 0x1000>;
 144                 };
 145
 146                 irq-syscfg {
 147                         compatible    = "st,stih407-irq-syscfg";
 148                         st,syscfg     = <&syscfg_core>;
 149                         st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
 150                                         <ST_IRQ_SYSCFG_PMU_1>;
 151                         st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
 152                                         <ST_IRQ_SYSCFG_DISABLED>;
 153                 };
 154
 155                 /* Display */
 156                 vtg_main: sti-vtg-main@8d02800 {
 157                         compatible = "st,vtg";
 158                         reg = <0x8d02800 0x200>;
 159                         interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
 160                 };
 161
 162                 vtg_aux: sti-vtg-aux@8d00200 {
 163                         compatible = "st,vtg";
 164                         reg = <0x8d00200 0x100>;
 165                         interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
 166                 };
 167
 168                 serial@9830000 {
 169                         compatible = "st,asc";
 170                         reg = <0x9830000 0x2c>;
 171                         interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
 172                         pinctrl-names = "default";
 173                         pinctrl-0 = <&pinctrl_serial0>;
 174                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 175
 176                         status = "disabled";
 177                 };
 178
 179                 serial@9831000 {
 180                         compatible = "st,asc";
 181                         reg = <0x9831000 0x2c>;
 182                         interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_serial1>;
 185                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 186
 187                         status = "disabled";
 188                 };
 189
 190                 serial@9832000 {
 191                         compatible = "st,asc";
 192                         reg = <0x9832000 0x2c>;
 193                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&pinctrl_serial2>;
 196                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 197
 198                         status = "disabled";
 199                 };
 200
 201                 /* SBC_ASC0 - UART10 */
 202                 sbc_serial0: serial@9530000 {
 203                         compatible = "st,asc";
 204                         reg = <0x9530000 0x2c>;
 205                         interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
 206                         pinctrl-names = "default";
 207                         pinctrl-0 = <&pinctrl_sbc_serial0>;
 208                         clocks = <&clk_sysin>;
 209
 210                         status = "disabled";
 211                 };
 212
 213                 serial@9531000 {
 214                         compatible = "st,asc";
 215                         reg = <0x9531000 0x2c>;
 216                         interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
 217                         pinctrl-names = "default";
 218                         pinctrl-0 = <&pinctrl_sbc_serial1>;
 219                         clocks = <&clk_sysin>;
 220
 221                         status = "disabled";
 222                 };
 223
 224                 i2c@9840000 {
 225                         compatible = "st,comms-ssc4-i2c";
 226                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 227                         reg = <0x9840000 0x110>;
 228                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 229                         clock-names = "ssc";
 230                         clock-frequency = <400000>;
 231                         pinctrl-names = "default";
 232                         pinctrl-0 = <&pinctrl_i2c0_default>;
 233
 234                         status = "disabled";
 235                 };
 236
 237                 i2c@9841000 {
 238                         compatible = "st,comms-ssc4-i2c";
 239                         reg = <0x9841000 0x110>;
 240                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 242                         clock-names = "ssc";
 243                         clock-frequency = <400000>;
 244                         pinctrl-names = "default";
 245                         pinctrl-0 = <&pinctrl_i2c1_default>;
 246
 247                         status = "disabled";
 248                 };
 249
 250                 i2c@9842000 {
 251                         compatible = "st,comms-ssc4-i2c";
 252                         reg = <0x9842000 0x110>;
 253                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 254                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 255                         clock-names = "ssc";
 256                         clock-frequency = <400000>;
 257                         pinctrl-names = "default";
 258                         pinctrl-0 = <&pinctrl_i2c2_default>;
 259
 260                         status = "disabled";
 261                 };
 262
 263                 i2c@9843000 {
 264                         compatible = "st,comms-ssc4-i2c";
 265                         reg = <0x9843000 0x110>;
 266                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 267                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 268                         clock-names = "ssc";
 269                         clock-frequency = <400000>;
 270                         pinctrl-names = "default";
 271                         pinctrl-0 = <&pinctrl_i2c3_default>;
 272
 273                         status = "disabled";
 274                 };
 275
 276                 i2c@9844000 {
 277                         compatible = "st,comms-ssc4-i2c";
 278                         reg = <0x9844000 0x110>;
 279                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 281                         clock-names = "ssc";
 282                         clock-frequency = <400000>;
 283                         pinctrl-names = "default";
 284                         pinctrl-0 = <&pinctrl_i2c4_default>;
 285
 286                         status = "disabled";
 287                 };
 288
 289                 i2c@9845000 {
 290                         compatible = "st,comms-ssc4-i2c";
 291                         reg = <0x9845000 0x110>;
 292                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 293                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 294                         clock-names = "ssc";
 295                         clock-frequency = <400000>;
 296                         pinctrl-names = "default";
 297                         pinctrl-0 = <&pinctrl_i2c5_default>;
 298
 299                         status = "disabled";
 300                 };
 301
 302
 303                 /* SSCs on SBC */
 304                 i2c@9540000 {
 305                         compatible = "st,comms-ssc4-i2c";
 306                         reg = <0x9540000 0x110>;
 307                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 308                         clocks = <&clk_sysin>;
 309                         clock-names = "ssc";
 310                         clock-frequency = <400000>;
 311                         pinctrl-names = "default";
 312                         pinctrl-0 = <&pinctrl_i2c10_default>;
 313
 314                         status = "disabled";
 315                 };
 316
 317                 i2c@9541000 {
 318                         compatible = "st,comms-ssc4-i2c";
 319                         reg = <0x9541000 0x110>;
 320                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 321                         clocks = <&clk_sysin>;
 322                         clock-names = "ssc";
 323                         clock-frequency = <400000>;
 324                         pinctrl-names = "default";
 325                         pinctrl-0 = <&pinctrl_i2c11_default>;
 326
 327                         status = "disabled";
 328                 };
 329
 330                 usb2_picophy0: phy1 {
 331                         compatible = "st,stih407-usb2-phy";
 332                         #phy-cells = <0>;
 333                         st,syscfg = <&syscfg_core 0x100 0xf4>;
 334                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
 335                                  <&picophyreset STIH407_PICOPHY2_RESET>;
 336                         reset-names = "global", "port";
 337                 };
 338
 339                 miphy28lp_phy: miphy28lp@9b22000 {
 340                         compatible = "st,miphy28lp-phy";
 341                         st,syscfg = <&syscfg_core>;
 342                         #address-cells  = <1>;
 343                         #size-cells     = <1>;
 344                         ranges;
 345
 346                         phy_port0: port@9b22000 {
 347                                 reg = <0x9b22000 0xff>,
 348                                       <0x9b09000 0xff>,
 349                                       <0x9b04000 0xff>;
 350                                 reg-names = "sata-up",
 351                                             "pcie-up",
 352                                             "pipew";
 353
 354                                 st,syscfg = <0x114 0x818 0xe0 0xec>;
 355                                 #phy-cells = <1>;
 356
 357                                 reset-names = "miphy-sw-rst";
 358                                 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
 359                         };
 360
 361                         phy_port1: port@9b2a000 {
 362                                 reg = <0x9b2a000 0xff>,
 363                                       <0x9b19000 0xff>,
 364                                       <0x9b14000 0xff>;
 365                                 reg-names = "sata-up",
 366                                             "pcie-up",
 367                                             "pipew";
 368
 369                                 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
 370
 371                                 #phy-cells = <1>;
 372
 373                                 reset-names = "miphy-sw-rst";
 374                                 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
 375                         };
 376
 377                         phy_port2: port@8f95000 {
 378                                 reg = <0x8f95000 0xff>,
 379                                       <0x8f90000 0xff>;
 380                                 reg-names = "pipew",
 381                                             "usb3-up";
 382
 383                                 st,syscfg = <0x11c 0x820>;
 384
 385                                 #phy-cells = <1>;
 386
 387                                 reset-names = "miphy-sw-rst";
 388                                 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 389                         };
 390                 };
 391
 392                 spi@9840000 {
 393                         compatible = "st,comms-ssc4-spi";
 394                         reg = <0x9840000 0x110>;
 395                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 396                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 397                         clock-names = "ssc";
 398                         pinctrl-0 = <&pinctrl_spi0_default>;
 399                         pinctrl-names = "default";
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402
 403                         status = "disabled";
 404                 };
 405
 406                 spi@9841000 {
 407                         compatible = "st,comms-ssc4-spi";
 408                         reg = <0x9841000 0x110>;
 409                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 410                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 411                         clock-names = "ssc";
 412                         pinctrl-names = "default";
 413                         pinctrl-0 = <&pinctrl_spi1_default>;
 414
 415                         status = "disabled";
 416                 };
 417
 418                 spi@9842000 {
 419                         compatible = "st,comms-ssc4-spi";
 420                         reg = <0x9842000 0x110>;
 421                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 422                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 423                         clock-names = "ssc";
 424                         pinctrl-names = "default";
 425                         pinctrl-0 = <&pinctrl_spi2_default>;
 426
 427                         status = "disabled";
 428                 };
 429
 430                 spi@9843000 {
 431                         compatible = "st,comms-ssc4-spi";
 432                         reg = <0x9843000 0x110>;
 433                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 435                         clock-names = "ssc";
 436                         pinctrl-names = "default";
 437                         pinctrl-0 = <&pinctrl_spi3_default>;
 438
 439                         status = "disabled";
 440                 };
 441
 442                 spi@9844000 {
 443                         compatible = "st,comms-ssc4-spi";
 444                         reg = <0x9844000 0x110>;
 445                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 447                         clock-names = "ssc";
 448                         pinctrl-names = "default";
 449                         pinctrl-0 = <&pinctrl_spi4_default>;
 450
 451                         status = "disabled";
 452                 };
 453
 454                 /* SBC SSC */
 455                 spi@9540000 {
 456                         compatible = "st,comms-ssc4-spi";
 457                         reg = <0x9540000 0x110>;
 458                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 459                         clocks = <&clk_sysin>;
 460                         clock-names = "ssc";
 461                         pinctrl-names = "default";
 462                         pinctrl-0 = <&pinctrl_spi10_default>;
 463
 464                         status = "disabled";
 465                 };
 466
 467                 spi@9541000 {
 468                         compatible = "st,comms-ssc4-spi";
 469                         reg = <0x9541000 0x110>;
 470                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&clk_sysin>;
 472                         clock-names = "ssc";
 473                         pinctrl-names = "default";
 474                         pinctrl-0 = <&pinctrl_spi11_default>;
 475
 476                         status = "disabled";
 477                 };
 478
 479                 spi@9542000 {
 480                         compatible = "st,comms-ssc4-spi";
 481                         reg = <0x9542000 0x110>;
 482                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 483                         clocks = <&clk_sysin>;
 484                         clock-names = "ssc";
 485                         pinctrl-names = "default";
 486                         pinctrl-0 = <&pinctrl_spi12_default>;
 487
 488                         status = "disabled";
 489                 };
 490
 491                 mmc0: sdhci@09060000 {
 492                         compatible = "st,sdhci-stih407", "st,sdhci";
 493                         status = "disabled";
 494                         reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
 495                         reg-names = "mmc", "top-mmc-delay";
 496                         interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
 497                         interrupt-names = "mmcirq";
 498                         pinctrl-names = "default";
 499                         pinctrl-0 = <&pinctrl_mmc0>;
 500                         clock-names = "mmc";
 501                         clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
 502                         bus-width = <8>;
 503                         non-removable;
 504                 };
 505
 506                 mmc1: sdhci@09080000 {
 507                         compatible = "st,sdhci-stih407", "st,sdhci";
 508                         status = "disabled";
 509                         reg = <0x09080000 0x7ff>;
 510                         reg-names = "mmc";
 511                         interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
 512                         interrupt-names = "mmcirq";
 513                         pinctrl-names = "default";
 514                         pinctrl-0 = <&pinctrl_sd1>;
 515                         clock-names = "mmc";
 516                         clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
 517                         resets = <&softreset STIH407_MMC1_SOFTRESET>;
 518                         bus-width = <4>;
 519                 };
 520
 521                 /* Watchdog and Real-Time Clock */
 522                 lpc@8787000 {
 523                         compatible = "st,stih407-lpc";
 524                         reg = <0x8787000 0x1000>;
 525                         interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
 526                         clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
 527                         timeout-sec = <120>;
 528                         st,syscfg = <&syscfg_core>;
 529                         st,lpc-mode = <ST_LPC_MODE_WDT>;
 530                 };
 531
 532                 lpc@8788000 {
 533                         compatible = "st,stih407-lpc";
 534                         reg = <0x8788000 0x1000>;
 535                         interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
 536                         clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
 537                         st,lpc-mode = <ST_LPC_MODE_RTC>;
 538                 };
 539
 540                 sata0: sata@9b20000 {
 541                         compatible = "st,ahci";
 542                         reg = <0x9b20000 0x1000>;
 543
 544                         interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 545                         interrupt-names = "hostc";
 546
 547                         phys = <&phy_port0 PHY_TYPE_SATA>;
 548                         phy-names = "ahci_phy";
 549
 550                         resets = <&powerdown STIH407_SATA0_POWERDOWN>,
 551                                  <&softreset STIH407_SATA0_SOFTRESET>,
 552                                  <&softreset STIH407_SATA0_PWR_SOFTRESET>;
 553                         reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
 554
 555                         clock-names = "ahci_clk";
 556                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 557
 558                         status = "disabled";
 559                 };
 560
 561                 sata1: sata@9b28000 {
 562                         compatible = "st,ahci";
 563                         reg = <0x9b28000 0x1000>;
 564
 565                         interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
 566                         interrupt-names = "hostc";
 567
 568                         phys = <&phy_port1 PHY_TYPE_SATA>;
 569                         phy-names = "ahci_phy";
 570
 571                         resets = <&powerdown STIH407_SATA1_POWERDOWN>,
 572                                  <&softreset STIH407_SATA1_SOFTRESET>,
 573                                  <&softreset STIH407_SATA1_PWR_SOFTRESET>;
 574                         reset-names = "pwr-dwn",
 575                                       "sw-rst",
 576                                       "pwr-rst";
 577
 578                         clock-names = "ahci_clk";
 579                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 580
 581                         status = "disabled";
 582                 };
 583
 584
 585                 st_dwc3: dwc3@8f94000 {
 586                         compatible      = "st,stih407-dwc3";
 587                         reg             = <0x08f94000 0x1000>, <0x110 0x4>;
 588                         reg-names       = "reg-glue", "syscfg-reg";
 589                         st,syscfg       = <&syscfg_core>;
 590                         resets          = <&powerdown STIH407_USB3_POWERDOWN>,
 591                                           <&softreset STIH407_MIPHY2_SOFTRESET>;
 592                         reset-names     = "powerdown", "softreset";
 593                         #address-cells  = <1>;
 594                         #size-cells     = <1>;
 595                         pinctrl-names   = "default";
 596                         pinctrl-0       = <&pinctrl_usb3>;
 597                         ranges;
 598
 599                         status = "disabled";
 600
 601                         dwc3: dwc3@9900000 {
 602                                 compatible      = "snps,dwc3";
 603                                 reg             = <0x09900000 0x100000>;
 604                                 interrupts      = <GIC_SPI 155 IRQ_TYPE_NONE>;
 605                                 dr_mode         = "host";
 606                                 phy-names       = "usb2-phy", "usb3-phy";
 607                                 phys            = <&usb2_picophy0>,
 608                                                   <&phy_port2 PHY_TYPE_USB3>;
 609                         };
 610                 };
 611
 612                 /* COMMS PWM Module */
 613                 pwm0: pwm@9810000 {
 614                         compatible      = "st,sti-pwm";
 615                         #pwm-cells      = <2>;
 616                         reg             = <0x9810000 0x68>;
 617                         pinctrl-names   = "default";
 618                         pinctrl-0       = <&pinctrl_pwm0_chan0_default>;
 619                         clock-names     = "pwm";
 620                         clocks          = <&clk_sysin>;
 621                         st,pwm-num-chan = <1>;
 622
 623                         status          = "disabled";
 624                 };
 625
 626                 /* SBC PWM Module */
 627                 pwm1: pwm@9510000 {
 628                         compatible      = "st,sti-pwm";
 629                         #pwm-cells      = <2>;
 630                         reg             = <0x9510000 0x68>;
 631                         pinctrl-names   = "default";
 632                         pinctrl-0       = <&pinctrl_pwm1_chan0_default
 633                                         &pinctrl_pwm1_chan1_default
 634                                         &pinctrl_pwm1_chan2_default
 635                                         &pinctrl_pwm1_chan3_default>;
 636                         clock-names     = "pwm";
 637                         clocks          = <&clk_sysin>;
 638                         st,pwm-num-chan = <4>;
 639
 640                         status          = "disabled";
 641                 };
 642
 643                 rng10: rng@08a89000 {
 644                         compatible      = "st,rng";
 645                         reg             = <0x08a89000 0x1000>;
 646                         clocks          = <&clk_sysin>;
 647                         status          = "okay";
 648                 };
 649
 650                 rng11: rng@08a8a000 {
 651                         compatible      = "st,rng";
 652                         reg             = <0x08a8a000 0x1000>;
 653                         clocks          = <&clk_sysin>;
 654                         status          = "okay";
 655                 };
 656
 657                 ethernet0: dwmac@9630000 {
 658                         device_type = "network";
 659                         status = "disabled";
 660                         compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
 661                         reg = <0x9630000 0x8000>, <0x80 0x4>;
 662                         reg-names = "stmmaceth", "sti-ethconf";
 663
 664                         st,syscon = <&syscfg_sbc_reg 0x80>;
 665                         st,gmac_en;
 666                         resets = <&softreset STIH407_ETH1_SOFTRESET>;
 667                         reset-names = "stmmaceth";
 668
 669                         interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
 670                                      <GIC_SPI 99 IRQ_TYPE_NONE>;
 671                         interrupt-names = "macirq", "eth_wake_irq";
 672
 673                         /* DMA Bus Mode */
 674                         snps,pbl = <8>;
 675
 676                         pinctrl-names = "default";
 677                         pinctrl-0 = <&pinctrl_rgmii1>;
 678
 679                         clock-names = "stmmaceth", "sti-ethclk";
 680                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
 681                                  <&clk_s_c0_flexgen CLK_ETH_PHY>;
 682                 };
 683
 684                 rng10: rng@08a89000 {
 685                         compatible      = "st,rng";
 686                         reg             = <0x08a89000 0x1000>;
 687                         clocks          = <&clk_sysin>;
 688                         status          = "okay";
 689                 };
 690
 691                 rng11: rng@08a8a000 {
 692                         compatible      = "st,rng";
 693                         reg             = <0x08a8a000 0x1000>;
 694                         clocks          = <&clk_sysin>;
 695                         status          = "okay";
 696                 };
 697         };
 698 };