arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/dma/sun4i-a10.h>
  51 #include <dt-bindings/pinctrl/sun4i-a10.h>
  52
  53 / {
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 framebuffer@0 {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  70                                  <&ahb_gates 44>;
  71                         status = "disabled";
  72                 };
  73
  74                 framebuffer@1 {
  75                         compatible = "allwinner,simple-framebuffer",
  76                                      "simple-framebuffer";
  77                         allwinner,pipeline = "de_be0-lcd0";
  78                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
  79                         status = "disabled";
  80                 };
  81
  82                 framebuffer@2 {
  83                         compatible = "allwinner,simple-framebuffer",
  84                                      "simple-framebuffer";
  85                         allwinner,pipeline = "de_be0-lcd0-tve0";
  86                         clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  87                                  <&ahb_gates 44>;
  88                         status = "disabled";
  89                 };
  90         };
  91
  92         cpus {
  93                 #address-cells = <1>;
  94                 #size-cells = <0>;
  95
  96                 cpu0: cpu@0 {
  97                         compatible = "arm,cortex-a7";
  98                         device_type = "cpu";
  99                         reg = <0>;
 100                         clocks = <&cpu>;
 101                         clock-latency = <244144>; /* 8 32k periods */
 102                         operating-points = <
 103                                 /* kHz    uV */
 104                                 960000  1400000
 105                                 912000  1400000
 106                                 864000  1300000
 107                                 720000  1200000
 108                                 528000  1100000
 109                                 312000  1000000
 110                                 144000  1000000
 111                                 >;
 112                         #cooling-cells = <2>;
 113                         cooling-min-level = <0>;
 114                         cooling-max-level = <6>;
 115                 };
 116
 117                 cpu@1 {
 118                         compatible = "arm,cortex-a7";
 119                         device_type = "cpu";
 120                         reg = <1>;
 121                 };
 122         };
 123
 124         thermal-zones {
 125                 cpu_thermal {
 126                         /* milliseconds */
 127                         polling-delay-passive = <250>;
 128                         polling-delay = <1000>;
 129                         thermal-sensors = <&rtp>;
 130
 131                         cooling-maps {
 132                                 map0 {
 133                                         trip = <&cpu_alert0>;
 134                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 135                                 };
 136                         };
 137
 138                         trips {
 139                                 cpu_alert0: cpu_alert0 {
 140                                         /* milliCelsius */
 141                                         temperature = <75000>;
 142                                         hysteresis = <2000>;
 143                                         type = "passive";
 144                                 };
 145
 146                                 cpu_crit: cpu_crit {
 147                                         /* milliCelsius */
 148                                         temperature = <100000>;
 149                                         hysteresis = <2000>;
 150                                         type = "critical";
 151                                 };
 152                         };
 153                 };
 154         };
 155
 156         memory {
 157                 reg = <0x40000000 0x80000000>;
 158         };
 159
 160         timer {
 161                 compatible = "arm,armv7-timer";
 162                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 163                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 164                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 165                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 166         };
 167
 168         pmu {
 169                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 170                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 172         };
 173
 174         clocks {
 175                 #address-cells = <1>;
 176                 #size-cells = <1>;
 177                 ranges;
 178
 179                 osc24M: clk@01c20050 {
 180                         #clock-cells = <0>;
 181                         compatible = "allwinner,sun4i-a10-osc-clk";
 182                         reg = <0x01c20050 0x4>;
 183                         clock-frequency = <24000000>;
 184                         clock-output-names = "osc24M";
 185                 };
 186
 187                 osc32k: clk@0 {
 188                         #clock-cells = <0>;
 189                         compatible = "fixed-clock";
 190                         clock-frequency = <32768>;
 191                         clock-output-names = "osc32k";
 192                 };
 193
 194                 pll1: clk@01c20000 {
 195                         #clock-cells = <0>;
 196                         compatible = "allwinner,sun4i-a10-pll1-clk";
 197                         reg = <0x01c20000 0x4>;
 198                         clocks = <&osc24M>;
 199                         clock-output-names = "pll1";
 200                 };
 201
 202                 pll4: clk@01c20018 {
 203                         #clock-cells = <0>;
 204                         compatible = "allwinner,sun7i-a20-pll4-clk";
 205                         reg = <0x01c20018 0x4>;
 206                         clocks = <&osc24M>;
 207                         clock-output-names = "pll4";
 208                 };
 209
 210                 pll5: clk@01c20020 {
 211                         #clock-cells = <1>;
 212                         compatible = "allwinner,sun4i-a10-pll5-clk";
 213                         reg = <0x01c20020 0x4>;
 214                         clocks = <&osc24M>;
 215                         clock-output-names = "pll5_ddr", "pll5_other";
 216                 };
 217
 218                 pll6: clk@01c20028 {
 219                         #clock-cells = <1>;
 220                         compatible = "allwinner,sun4i-a10-pll6-clk";
 221                         reg = <0x01c20028 0x4>;
 222                         clocks = <&osc24M>;
 223                         clock-output-names = "pll6_sata", "pll6_other", "pll6",
 224                                              "pll6_div_4";
 225                 };
 226
 227                 pll8: clk@01c20040 {
 228                         #clock-cells = <0>;
 229                         compatible = "allwinner,sun7i-a20-pll4-clk";
 230                         reg = <0x01c20040 0x4>;
 231                         clocks = <&osc24M>;
 232                         clock-output-names = "pll8";
 233                 };
 234
 235                 cpu: cpu@01c20054 {
 236                         #clock-cells = <0>;
 237                         compatible = "allwinner,sun4i-a10-cpu-clk";
 238                         reg = <0x01c20054 0x4>;
 239                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 240                         clock-output-names = "cpu";
 241                 };
 242
 243                 axi: axi@01c20054 {
 244                         #clock-cells = <0>;
 245                         compatible = "allwinner,sun4i-a10-axi-clk";
 246                         reg = <0x01c20054 0x4>;
 247                         clocks = <&cpu>;
 248                         clock-output-names = "axi";
 249                 };
 250
 251                 ahb: ahb@01c20054 {
 252                         #clock-cells = <0>;
 253                         compatible = "allwinner,sun5i-a13-ahb-clk";
 254                         reg = <0x01c20054 0x4>;
 255                         clocks = <&axi>, <&pll6 3>, <&pll6 1>;
 256                         clock-output-names = "ahb";
 257                         /*
 258                          * Use PLL6 as parent, instead of CPU/AXI
 259                          * which has rate changes due to cpufreq
 260                          */
 261                         assigned-clocks = <&ahb>;
 262                         assigned-clock-parents = <&pll6 3>;
 263                 };
 264
 265                 ahb_gates: clk@01c20060 {
 266                         #clock-cells = <1>;
 267                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 268                         reg = <0x01c20060 0x8>;
 269                         clocks = <&ahb>;
 270                         clock-indices = <0>, <1>,
 271                                         <2>, <3>, <4>,
 272                                         <5>, <6>, <7>, <8>,
 273                                         <9>, <10>, <11>, <12>,
 274                                         <13>, <14>, <16>,
 275                                         <17>, <18>, <20>, <21>,
 276                                         <22>, <23>, <25>,
 277                                         <28>, <32>, <33>, <34>,
 278                                         <35>, <36>, <37>, <40>,
 279                                         <41>, <42>, <43>,
 280                                         <44>, <45>, <46>,
 281                                         <47>, <49>, <50>,
 282                                         <52>;
 283                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 284                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 285                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 286                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 287                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 288                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 289                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 290                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 291                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 292                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 293                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 294                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 295                                 "ahb_mali";
 296                 };
 297
 298                 apb0: apb0@01c20054 {
 299                         #clock-cells = <0>;
 300                         compatible = "allwinner,sun4i-a10-apb0-clk";
 301                         reg = <0x01c20054 0x4>;
 302                         clocks = <&ahb>;
 303                         clock-output-names = "apb0";
 304                 };
 305
 306                 apb0_gates: clk@01c20068 {
 307                         #clock-cells = <1>;
 308                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 309                         reg = <0x01c20068 0x4>;
 310                         clocks = <&apb0>;
 311                         clock-indices = <0>, <1>,
 312                                         <2>, <3>, <4>,
 313                                         <5>, <6>, <7>,
 314                                         <8>, <10>;
 315                         clock-output-names = "apb0_codec", "apb0_spdif",
 316                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 317                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 318                                 "apb0_iis2", "apb0_keypad";
 319                 };
 320
 321                 apb1: clk@01c20058 {
 322                         #clock-cells = <0>;
 323                         compatible = "allwinner,sun4i-a10-apb1-clk";
 324                         reg = <0x01c20058 0x4>;
 325                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 326                         clock-output-names = "apb1";
 327                 };
 328
 329                 apb1_gates: clk@01c2006c {
 330                         #clock-cells = <1>;
 331                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 332                         reg = <0x01c2006c 0x4>;
 333                         clocks = <&apb1>;
 334                         clock-indices = <0>, <1>,
 335                                         <2>, <3>, <4>,
 336                                         <5>, <6>, <7>,
 337                                         <15>, <16>, <17>,
 338                                         <18>, <19>, <20>,
 339                                         <21>, <22>, <23>;
 340                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 341                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 342                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 343                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 344                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 345                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 346                 };
 347
 348                 nand_clk: clk@01c20080 {
 349                         #clock-cells = <0>;
 350                         compatible = "allwinner,sun4i-a10-mod0-clk";
 351                         reg = <0x01c20080 0x4>;
 352                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 353                         clock-output-names = "nand";
 354                 };
 355
 356                 ms_clk: clk@01c20084 {
 357                         #clock-cells = <0>;
 358                         compatible = "allwinner,sun4i-a10-mod0-clk";
 359                         reg = <0x01c20084 0x4>;
 360                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 361                         clock-output-names = "ms";
 362                 };
 363
 364                 mmc0_clk: clk@01c20088 {
 365                         #clock-cells = <1>;
 366                         compatible = "allwinner,sun4i-a10-mmc-clk";
 367                         reg = <0x01c20088 0x4>;
 368                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 369                         clock-output-names = "mmc0",
 370                                              "mmc0_output",
 371                                              "mmc0_sample";
 372                 };
 373
 374                 mmc1_clk: clk@01c2008c {
 375                         #clock-cells = <1>;
 376                         compatible = "allwinner,sun4i-a10-mmc-clk";
 377                         reg = <0x01c2008c 0x4>;
 378                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 379                         clock-output-names = "mmc1",
 380                                              "mmc1_output",
 381                                              "mmc1_sample";
 382                 };
 383
 384                 mmc2_clk: clk@01c20090 {
 385                         #clock-cells = <1>;
 386                         compatible = "allwinner,sun4i-a10-mmc-clk";
 387                         reg = <0x01c20090 0x4>;
 388                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 389                         clock-output-names = "mmc2",
 390                                              "mmc2_output",
 391                                              "mmc2_sample";
 392                 };
 393
 394                 mmc3_clk: clk@01c20094 {
 395                         #clock-cells = <1>;
 396                         compatible = "allwinner,sun4i-a10-mmc-clk";
 397                         reg = <0x01c20094 0x4>;
 398                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 399                         clock-output-names = "mmc3",
 400                                              "mmc3_output",
 401                                              "mmc3_sample";
 402                 };
 403
 404                 ts_clk: clk@01c20098 {
 405                         #clock-cells = <0>;
 406                         compatible = "allwinner,sun4i-a10-mod0-clk";
 407                         reg = <0x01c20098 0x4>;
 408                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 409                         clock-output-names = "ts";
 410                 };
 411
 412                 ss_clk: clk@01c2009c {
 413                         #clock-cells = <0>;
 414                         compatible = "allwinner,sun4i-a10-mod0-clk";
 415                         reg = <0x01c2009c 0x4>;
 416                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 417                         clock-output-names = "ss";
 418                 };
 419
 420                 spi0_clk: clk@01c200a0 {
 421                         #clock-cells = <0>;
 422                         compatible = "allwinner,sun4i-a10-mod0-clk";
 423                         reg = <0x01c200a0 0x4>;
 424                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 425                         clock-output-names = "spi0";
 426                 };
 427
 428                 spi1_clk: clk@01c200a4 {
 429                         #clock-cells = <0>;
 430                         compatible = "allwinner,sun4i-a10-mod0-clk";
 431                         reg = <0x01c200a4 0x4>;
 432                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 433                         clock-output-names = "spi1";
 434                 };
 435
 436                 spi2_clk: clk@01c200a8 {
 437                         #clock-cells = <0>;
 438                         compatible = "allwinner,sun4i-a10-mod0-clk";
 439                         reg = <0x01c200a8 0x4>;
 440                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 441                         clock-output-names = "spi2";
 442                 };
 443
 444                 pata_clk: clk@01c200ac {
 445                         #clock-cells = <0>;
 446                         compatible = "allwinner,sun4i-a10-mod0-clk";
 447                         reg = <0x01c200ac 0x4>;
 448                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 449                         clock-output-names = "pata";
 450                 };
 451
 452                 ir0_clk: clk@01c200b0 {
 453                         #clock-cells = <0>;
 454                         compatible = "allwinner,sun4i-a10-mod0-clk";
 455                         reg = <0x01c200b0 0x4>;
 456                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 457                         clock-output-names = "ir0";
 458                 };
 459
 460                 ir1_clk: clk@01c200b4 {
 461                         #clock-cells = <0>;
 462                         compatible = "allwinner,sun4i-a10-mod0-clk";
 463                         reg = <0x01c200b4 0x4>;
 464                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 465                         clock-output-names = "ir1";
 466                 };
 467
 468                 usb_clk: clk@01c200cc {
 469                         #clock-cells = <1>;
 470                         #reset-cells = <1>;
 471                         compatible = "allwinner,sun4i-a10-usb-clk";
 472                         reg = <0x01c200cc 0x4>;
 473                         clocks = <&pll6 1>;
 474                         clock-output-names = "usb_ohci0", "usb_ohci1",
 475                                              "usb_phy";
 476                 };
 477
 478                 spi3_clk: clk@01c200d4 {
 479                         #clock-cells = <0>;
 480                         compatible = "allwinner,sun4i-a10-mod0-clk";
 481                         reg = <0x01c200d4 0x4>;
 482                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 483                         clock-output-names = "spi3";
 484                 };
 485
 486                 mbus_clk: clk@01c2015c {
 487                         #clock-cells = <0>;
 488                         compatible = "allwinner,sun5i-a13-mbus-clk";
 489                         reg = <0x01c2015c 0x4>;
 490                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 491                         clock-output-names = "mbus";
 492                 };
 493
 494                 /*
 495                  * The following two are dummy clocks, placeholders
 496                  * used in the gmac_tx clock. The gmac driver will
 497                  * choose one parent depending on the PHY interface
 498                  * mode, using clk_set_rate auto-reparenting.
 499                  *
 500                  * The actual TX clock rate is not controlled by the
 501                  * gmac_tx clock.
 502                  */
 503                 mii_phy_tx_clk: clk@2 {
 504                         #clock-cells = <0>;
 505                         compatible = "fixed-clock";
 506                         clock-frequency = <25000000>;
 507                         clock-output-names = "mii_phy_tx";
 508                 };
 509
 510                 gmac_int_tx_clk: clk@3 {
 511                         #clock-cells = <0>;
 512                         compatible = "fixed-clock";
 513                         clock-frequency = <125000000>;
 514                         clock-output-names = "gmac_int_tx";
 515                 };
 516
 517                 gmac_tx_clk: clk@01c20164 {
 518                         #clock-cells = <0>;
 519                         compatible = "allwinner,sun7i-a20-gmac-clk";
 520                         reg = <0x01c20164 0x4>;
 521                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 522                         clock-output-names = "gmac_tx";
 523                 };
 524
 525                 /*
 526                  * Dummy clock used by output clocks
 527                  */
 528                 osc24M_32k: clk@1 {
 529                         #clock-cells = <0>;
 530                         compatible = "fixed-factor-clock";
 531                         clock-div = <750>;
 532                         clock-mult = <1>;
 533                         clocks = <&osc24M>;
 534                         clock-output-names = "osc24M_32k";
 535                 };
 536
 537                 clk_out_a: clk@01c201f0 {
 538                         #clock-cells = <0>;
 539                         compatible = "allwinner,sun7i-a20-out-clk";
 540                         reg = <0x01c201f0 0x4>;
 541                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 542                         clock-output-names = "clk_out_a";
 543                 };
 544
 545                 clk_out_b: clk@01c201f4 {
 546                         #clock-cells = <0>;
 547                         compatible = "allwinner,sun7i-a20-out-clk";
 548                         reg = <0x01c201f4 0x4>;
 549                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 550                         clock-output-names = "clk_out_b";
 551                 };
 552         };
 553
 554         soc@01c00000 {
 555                 compatible = "simple-bus";
 556                 #address-cells = <1>;
 557                 #size-cells = <1>;
 558                 ranges;
 559
 560                 sram-controller@01c00000 {
 561                         compatible = "allwinner,sun4i-a10-sram-controller";
 562                         reg = <0x01c00000 0x30>;
 563                         #address-cells = <1>;
 564                         #size-cells = <1>;
 565                         ranges;
 566
 567                         sram_a: sram@00000000 {
 568                                 compatible = "mmio-sram";
 569                                 reg = <0x00000000 0xc000>;
 570                                 #address-cells = <1>;
 571                                 #size-cells = <1>;
 572                                 ranges = <0 0x00000000 0xc000>;
 573
 574                                 emac_sram: sram-section@8000 {
 575                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 576                                         reg = <0x8000 0x4000>;
 577                                         status = "disabled";
 578                                 };
 579                         };
 580
 581                         sram_d: sram@00010000 {
 582                                 compatible = "mmio-sram";
 583                                 reg = <0x00010000 0x1000>;
 584                                 #address-cells = <1>;
 585                                 #size-cells = <1>;
 586                                 ranges = <0 0x00010000 0x1000>;
 587
 588                                 otg_sram: sram-section@0000 {
 589                                         compatible = "allwinner,sun4i-a10-sram-d";
 590                                         reg = <0x0000 0x1000>;
 591                                         status = "disabled";
 592                                 };
 593                         };
 594                 };
 595
 596                 nmi_intc: interrupt-controller@01c00030 {
 597                         compatible = "allwinner,sun7i-a20-sc-nmi";
 598                         interrupt-controller;
 599                         #interrupt-cells = <2>;
 600                         reg = <0x01c00030 0x0c>;
 601                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 602                 };
 603
 604                 dma: dma-controller@01c02000 {
 605                         compatible = "allwinner,sun4i-a10-dma";
 606                         reg = <0x01c02000 0x1000>;
 607                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 608                         clocks = <&ahb_gates 6>;
 609                         #dma-cells = <2>;
 610                 };
 611
 612                 spi0: spi@01c05000 {
 613                         compatible = "allwinner,sun4i-a10-spi";
 614                         reg = <0x01c05000 0x1000>;
 615                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 616                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 617                         clock-names = "ahb", "mod";
 618                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 619                                <&dma SUN4I_DMA_DEDICATED 26>;
 620                         dma-names = "rx", "tx";
 621                         status = "disabled";
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                 };
 625
 626                 spi1: spi@01c06000 {
 627                         compatible = "allwinner,sun4i-a10-spi";
 628                         reg = <0x01c06000 0x1000>;
 629                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 630                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 631                         clock-names = "ahb", "mod";
 632                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 633                                <&dma SUN4I_DMA_DEDICATED 8>;
 634                         dma-names = "rx", "tx";
 635                         status = "disabled";
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638                 };
 639
 640                 emac: ethernet@01c0b000 {
 641                         compatible = "allwinner,sun4i-a10-emac";
 642                         reg = <0x01c0b000 0x1000>;
 643                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 644                         clocks = <&ahb_gates 17>;
 645                         allwinner,sram = <&emac_sram 1>;
 646                         status = "disabled";
 647                 };
 648
 649                 mdio: mdio@01c0b080 {
 650                         compatible = "allwinner,sun4i-a10-mdio";
 651                         reg = <0x01c0b080 0x14>;
 652                         status = "disabled";
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655                 };
 656
 657                 mmc0: mmc@01c0f000 {
 658                         compatible = "allwinner,sun5i-a13-mmc";
 659                         reg = <0x01c0f000 0x1000>;
 660                         clocks = <&ahb_gates 8>,
 661                                  <&mmc0_clk 0>,
 662                                  <&mmc0_clk 1>,
 663                                  <&mmc0_clk 2>;
 664                         clock-names = "ahb",
 665                                       "mmc",
 666                                       "output",
 667                                       "sample";
 668                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 669                         status = "disabled";
 670                         #address-cells = <1>;
 671                         #size-cells = <0>;
 672                 };
 673
 674                 mmc1: mmc@01c10000 {
 675                         compatible = "allwinner,sun5i-a13-mmc";
 676                         reg = <0x01c10000 0x1000>;
 677                         clocks = <&ahb_gates 9>,
 678                                  <&mmc1_clk 0>,
 679                                  <&mmc1_clk 1>,
 680                                  <&mmc1_clk 2>;
 681                         clock-names = "ahb",
 682                                       "mmc",
 683                                       "output",
 684                                       "sample";
 685                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 686                         status = "disabled";
 687                         #address-cells = <1>;
 688                         #size-cells = <0>;
 689                 };
 690
 691                 mmc2: mmc@01c11000 {
 692                         compatible = "allwinner,sun5i-a13-mmc";
 693                         reg = <0x01c11000 0x1000>;
 694                         clocks = <&ahb_gates 10>,
 695                                  <&mmc2_clk 0>,
 696                                  <&mmc2_clk 1>,
 697                                  <&mmc2_clk 2>;
 698                         clock-names = "ahb",
 699                                       "mmc",
 700                                       "output",
 701                                       "sample";
 702                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 703                         status = "disabled";
 704                         #address-cells = <1>;
 705                         #size-cells = <0>;
 706                 };
 707
 708                 mmc3: mmc@01c12000 {
 709                         compatible = "allwinner,sun5i-a13-mmc";
 710                         reg = <0x01c12000 0x1000>;
 711                         clocks = <&ahb_gates 11>,
 712                                  <&mmc3_clk 0>,
 713                                  <&mmc3_clk 1>,
 714                                  <&mmc3_clk 2>;
 715                         clock-names = "ahb",
 716                                       "mmc",
 717                                       "output",
 718                                       "sample";
 719                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 720                         status = "disabled";
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                 };
 724
 725                 usb_otg: usb@01c13000 {
 726                         compatible = "allwinner,sun4i-a10-musb";
 727                         reg = <0x01c13000 0x0400>;
 728                         clocks = <&ahb_gates 0>;
 729                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 730                         interrupt-names = "mc";
 731                         phys = <&usbphy 0>;
 732                         phy-names = "usb";
 733                         extcon = <&usbphy 0>;
 734                         allwinner,sram = <&otg_sram 1>;
 735                         status = "disabled";
 736                 };
 737
 738                 usbphy: phy@01c13400 {
 739                         #phy-cells = <1>;
 740                         compatible = "allwinner,sun7i-a20-usb-phy";
 741                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 742                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 743                         clocks = <&usb_clk 8>;
 744                         clock-names = "usb_phy";
 745                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 746                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 747                         status = "disabled";
 748                 };
 749
 750                 ehci0: usb@01c14000 {
 751                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 752                         reg = <0x01c14000 0x100>;
 753                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 754                         clocks = <&ahb_gates 1>;
 755                         phys = <&usbphy 1>;
 756                         phy-names = "usb";
 757                         status = "disabled";
 758                 };
 759
 760                 ohci0: usb@01c14400 {
 761                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 762                         reg = <0x01c14400 0x100>;
 763                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 764                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 765                         phys = <&usbphy 1>;
 766                         phy-names = "usb";
 767                         status = "disabled";
 768                 };
 769
 770                 crypto: crypto-engine@01c15000 {
 771                         compatible = "allwinner,sun4i-a10-crypto";
 772                         reg = <0x01c15000 0x1000>;
 773                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 774                         clocks = <&ahb_gates 5>, <&ss_clk>;
 775                         clock-names = "ahb", "mod";
 776                 };
 777
 778                 spi2: spi@01c17000 {
 779                         compatible = "allwinner,sun4i-a10-spi";
 780                         reg = <0x01c17000 0x1000>;
 781                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 782                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 783                         clock-names = "ahb", "mod";
 784                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 785                                <&dma SUN4I_DMA_DEDICATED 28>;
 786                         dma-names = "rx", "tx";
 787                         status = "disabled";
 788                         #address-cells = <1>;
 789                         #size-cells = <0>;
 790                 };
 791
 792                 ahci: sata@01c18000 {
 793                         compatible = "allwinner,sun4i-a10-ahci";
 794                         reg = <0x01c18000 0x1000>;
 795                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 796                         clocks = <&pll6 0>, <&ahb_gates 25>;
 797                         status = "disabled";
 798                 };
 799
 800                 ehci1: usb@01c1c000 {
 801                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 802                         reg = <0x01c1c000 0x100>;
 803                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 804                         clocks = <&ahb_gates 3>;
 805                         phys = <&usbphy 2>;
 806                         phy-names = "usb";
 807                         status = "disabled";
 808                 };
 809
 810                 ohci1: usb@01c1c400 {
 811                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 812                         reg = <0x01c1c400 0x100>;
 813                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 814                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 815                         phys = <&usbphy 2>;
 816                         phy-names = "usb";
 817                         status = "disabled";
 818                 };
 819
 820                 spi3: spi@01c1f000 {
 821                         compatible = "allwinner,sun4i-a10-spi";
 822                         reg = <0x01c1f000 0x1000>;
 823                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 824                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 825                         clock-names = "ahb", "mod";
 826                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 827                                <&dma SUN4I_DMA_DEDICATED 30>;
 828                         dma-names = "rx", "tx";
 829                         status = "disabled";
 830                         #address-cells = <1>;
 831                         #size-cells = <0>;
 832                 };
 833
 834                 pio: pinctrl@01c20800 {
 835                         compatible = "allwinner,sun7i-a20-pinctrl";
 836                         reg = <0x01c20800 0x400>;
 837                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 838                         clocks = <&apb0_gates 5>;
 839                         gpio-controller;
 840                         interrupt-controller;
 841                         #interrupt-cells = <3>;
 842                         #gpio-cells = <3>;
 843
 844                         pwm0_pins_a: pwm0@0 {
 845                                 allwinner,pins = "PB2";
 846                                 allwinner,function = "pwm";
 847                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 848                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 849                         };
 850
 851                         pwm1_pins_a: pwm1@0 {
 852                                 allwinner,pins = "PI3";
 853                                 allwinner,function = "pwm";
 854                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 855                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 856                         };
 857
 858                         uart0_pins_a: uart0@0 {
 859                                 allwinner,pins = "PB22", "PB23";
 860                                 allwinner,function = "uart0";
 861                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 862                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 863                         };
 864
 865                         uart2_pins_a: uart2@0 {
 866                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 867                                 allwinner,function = "uart2";
 868                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 869                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 870                         };
 871
 872                         uart3_pins_a: uart3@0 {
 873                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 874                                 allwinner,function = "uart3";
 875                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 876                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 877                         };
 878
 879                         uart3_pins_b: uart3@1 {
 880                                 allwinner,pins = "PH0", "PH1";
 881                                 allwinner,function = "uart3";
 882                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 883                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 884                         };
 885
 886                         uart4_pins_a: uart4@0 {
 887                                 allwinner,pins = "PG10", "PG11";
 888                                 allwinner,function = "uart4";
 889                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 890                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 891                         };
 892
 893                         uart4_pins_b: uart4@1 {
 894                                 allwinner,pins = "PH4", "PH5";
 895                                 allwinner,function = "uart4";
 896                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 897                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 898                         };
 899
 900                         uart5_pins_a: uart5@0 {
 901                                 allwinner,pins = "PI10", "PI11";
 902                                 allwinner,function = "uart5";
 903                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 904                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 905                         };
 906
 907                         uart6_pins_a: uart6@0 {
 908                                 allwinner,pins = "PI12", "PI13";
 909                                 allwinner,function = "uart6";
 910                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 911                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 912                         };
 913
 914                         uart7_pins_a: uart7@0 {
 915                                 allwinner,pins = "PI20", "PI21";
 916                                 allwinner,function = "uart7";
 917                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 918                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 919                         };
 920
 921                         i2c0_pins_a: i2c0@0 {
 922                                 allwinner,pins = "PB0", "PB1";
 923                                 allwinner,function = "i2c0";
 924                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 925                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 926                         };
 927
 928                         i2c1_pins_a: i2c1@0 {
 929                                 allwinner,pins = "PB18", "PB19";
 930                                 allwinner,function = "i2c1";
 931                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 932                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 933                         };
 934
 935                         i2c2_pins_a: i2c2@0 {
 936                                 allwinner,pins = "PB20", "PB21";
 937                                 allwinner,function = "i2c2";
 938                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 939                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 940                         };
 941
 942                         i2c3_pins_a: i2c3@0 {
 943                                 allwinner,pins = "PI0", "PI1";
 944                                 allwinner,function = "i2c3";
 945                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 946                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 947                         };
 948
 949                         emac_pins_a: emac0@0 {
 950                                 allwinner,pins = "PA0", "PA1", "PA2",
 951                                                 "PA3", "PA4", "PA5", "PA6",
 952                                                 "PA7", "PA8", "PA9", "PA10",
 953                                                 "PA11", "PA12", "PA13", "PA14",
 954                                                 "PA15", "PA16";
 955                                 allwinner,function = "emac";
 956                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 957                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 958                         };
 959
 960                         clk_out_a_pins_a: clk_out_a@0 {
 961                                 allwinner,pins = "PI12";
 962                                 allwinner,function = "clk_out_a";
 963                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 964                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 965                         };
 966
 967                         clk_out_b_pins_a: clk_out_b@0 {
 968                                 allwinner,pins = "PI13";
 969                                 allwinner,function = "clk_out_b";
 970                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 971                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 972                         };
 973
 974                         gmac_pins_mii_a: gmac_mii@0 {
 975                                 allwinner,pins = "PA0", "PA1", "PA2",
 976                                                 "PA3", "PA4", "PA5", "PA6",
 977                                                 "PA7", "PA8", "PA9", "PA10",
 978                                                 "PA11", "PA12", "PA13", "PA14",
 979                                                 "PA15", "PA16";
 980                                 allwinner,function = "gmac";
 981                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 982                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 983                         };
 984
 985                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 986                                 allwinner,pins = "PA0", "PA1", "PA2",
 987                                                 "PA3", "PA4", "PA5", "PA6",
 988                                                 "PA7", "PA8", "PA10",
 989                                                 "PA11", "PA12", "PA13",
 990                                                 "PA15", "PA16";
 991                                 allwinner,function = "gmac";
 992                                 /*
 993                                  * data lines in RGMII mode use DDR mode
 994                                  * and need a higher signal drive strength
 995                                  */
 996                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 997                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 998                         };
 999
1000                         spi0_pins_a: spi0@0 {
1001                                 allwinner,pins = "PI11", "PI12", "PI13";
1002                                 allwinner,function = "spi0";
1003                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1004                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1005                         };
1006
1007                         spi0_cs0_pins_a: spi0_cs0@0 {
1008                                 allwinner,pins = "PI10";
1009                                 allwinner,function = "spi0";
1010                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1011                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1012                         };
1013
1014                         spi0_cs1_pins_a: spi0_cs1@0 {
1015                                 allwinner,pins = "PI14";
1016                                 allwinner,function = "spi0";
1017                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1018                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1019                         };
1020
1021                         spi1_pins_a: spi1@0 {
1022                                 allwinner,pins = "PI17", "PI18", "PI19";
1023                                 allwinner,function = "spi1";
1024                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1025                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1026                         };
1027
1028                         spi1_cs0_pins_a: spi1_cs0@0 {
1029                                 allwinner,pins = "PI16";
1030                                 allwinner,function = "spi1";
1031                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1032                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1033                         };
1034
1035                         spi2_pins_a: spi2@0 {
1036                                 allwinner,pins = "PC20", "PC21", "PC22";
1037                                 allwinner,function = "spi2";
1038                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1039                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1040                         };
1041
1042                         spi2_pins_b: spi2@1 {
1043                                 allwinner,pins = "PB15", "PB16", "PB17";
1044                                 allwinner,function = "spi2";
1045                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1046                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1047                         };
1048
1049                         spi2_cs0_pins_a: spi2_cs0@0 {
1050                                 allwinner,pins = "PC19";
1051                                 allwinner,function = "spi2";
1052                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1053                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1054                         };
1055
1056                         spi2_cs0_pins_b: spi2_cs0@1 {
1057                                 allwinner,pins = "PB14";
1058                                 allwinner,function = "spi2";
1059                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1060                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1061                         };
1062
1063                         mmc0_pins_a: mmc0@0 {
1064                                 allwinner,pins = "PF0", "PF1", "PF2",
1065                                                  "PF3", "PF4", "PF5";
1066                                 allwinner,function = "mmc0";
1067                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1068                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1069                         };
1070
1071                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1072                                 allwinner,pins = "PH1";
1073                                 allwinner,function = "gpio_in";
1074                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1075                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1076                         };
1077
1078                         mmc2_pins_a: mmc2@0 {
1079                                 allwinner,pins = "PC6", "PC7", "PC8",
1080                                                  "PC9", "PC10", "PC11";
1081                                 allwinner,function = "mmc2";
1082                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1083                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1084                         };
1085
1086                         mmc3_pins_a: mmc3@0 {
1087                                 allwinner,pins = "PI4", "PI5", "PI6",
1088                                                  "PI7", "PI8", "PI9";
1089                                 allwinner,function = "mmc3";
1090                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1091                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1092                         };
1093
1094                         ir0_rx_pins_a: ir0@0 {
1095                                     allwinner,pins = "PB4";
1096                                     allwinner,function = "ir0";
1097                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1098                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1099                         };
1100
1101                         ir0_tx_pins_a: ir0@1 {
1102                                     allwinner,pins = "PB3";
1103                                     allwinner,function = "ir0";
1104                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1105                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1106                         };
1107
1108                         ir1_rx_pins_a: ir1@0 {
1109                                     allwinner,pins = "PB23";
1110                                     allwinner,function = "ir1";
1111                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1112                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1113                         };
1114
1115                         ir1_tx_pins_a: ir1@1 {
1116                                     allwinner,pins = "PB22";
1117                                     allwinner,function = "ir1";
1118                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1119                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1120                         };
1121
1122                         ps20_pins_a: ps20@0 {
1123                                 allwinner,pins = "PI20", "PI21";
1124                                 allwinner,function = "ps2";
1125                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1126                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1127                         };
1128
1129                         ps21_pins_a: ps21@0 {
1130                                 allwinner,pins = "PH12", "PH13";
1131                                 allwinner,function = "ps2";
1132                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1133                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1134                         };
1135                 };
1136
1137                 timer@01c20c00 {
1138                         compatible = "allwinner,sun4i-a10-timer";
1139                         reg = <0x01c20c00 0x90>;
1140                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1141                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1142                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1143                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1144                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1145                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1146                         clocks = <&osc24M>;
1147                 };
1148
1149                 wdt: watchdog@01c20c90 {
1150                         compatible = "allwinner,sun4i-a10-wdt";
1151                         reg = <0x01c20c90 0x10>;
1152                 };
1153
1154                 rtc: rtc@01c20d00 {
1155                         compatible = "allwinner,sun7i-a20-rtc";
1156                         reg = <0x01c20d00 0x20>;
1157                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1158                 };
1159
1160                 pwm: pwm@01c20e00 {
1161                         compatible = "allwinner,sun7i-a20-pwm";
1162                         reg = <0x01c20e00 0xc>;
1163                         clocks = <&osc24M>;
1164                         #pwm-cells = <3>;
1165                         status = "disabled";
1166                 };
1167
1168                 ir0: ir@01c21800 {
1169                         compatible = "allwinner,sun4i-a10-ir";
1170                         clocks = <&apb0_gates 6>, <&ir0_clk>;
1171                         clock-names = "apb", "ir";
1172                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1173                         reg = <0x01c21800 0x40>;
1174                         status = "disabled";
1175                 };
1176
1177                 ir1: ir@01c21c00 {
1178                         compatible = "allwinner,sun4i-a10-ir";
1179                         clocks = <&apb0_gates 7>, <&ir1_clk>;
1180                         clock-names = "apb", "ir";
1181                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1182                         reg = <0x01c21c00 0x40>;
1183                         status = "disabled";
1184                 };
1185
1186                 lradc: lradc@01c22800 {
1187                         compatible = "allwinner,sun4i-a10-lradc-keys";
1188                         reg = <0x01c22800 0x100>;
1189                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1190                         status = "disabled";
1191                 };
1192
1193                 sid: eeprom@01c23800 {
1194                         compatible = "allwinner,sun7i-a20-sid";
1195                         reg = <0x01c23800 0x200>;
1196                 };
1197
1198                 rtp: rtp@01c25000 {
1199                         compatible = "allwinner,sun5i-a13-ts";
1200                         reg = <0x01c25000 0x100>;
1201                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1202                         #thermal-sensor-cells = <0>;
1203                 };
1204
1205                 uart0: serial@01c28000 {
1206                         compatible = "snps,dw-apb-uart";
1207                         reg = <0x01c28000 0x400>;
1208                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1209                         reg-shift = <2>;
1210                         reg-io-width = <4>;
1211                         clocks = <&apb1_gates 16>;
1212                         status = "disabled";
1213                 };
1214
1215                 uart1: serial@01c28400 {
1216                         compatible = "snps,dw-apb-uart";
1217                         reg = <0x01c28400 0x400>;
1218                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1219                         reg-shift = <2>;
1220                         reg-io-width = <4>;
1221                         clocks = <&apb1_gates 17>;
1222                         status = "disabled";
1223                 };
1224
1225                 uart2: serial@01c28800 {
1226                         compatible = "snps,dw-apb-uart";
1227                         reg = <0x01c28800 0x400>;
1228                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1229                         reg-shift = <2>;
1230                         reg-io-width = <4>;
1231                         clocks = <&apb1_gates 18>;
1232                         status = "disabled";
1233                 };
1234
1235                 uart3: serial@01c28c00 {
1236                         compatible = "snps,dw-apb-uart";
1237                         reg = <0x01c28c00 0x400>;
1238                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1239                         reg-shift = <2>;
1240                         reg-io-width = <4>;
1241                         clocks = <&apb1_gates 19>;
1242                         status = "disabled";
1243                 };
1244
1245                 uart4: serial@01c29000 {
1246                         compatible = "snps,dw-apb-uart";
1247                         reg = <0x01c29000 0x400>;
1248                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1249                         reg-shift = <2>;
1250                         reg-io-width = <4>;
1251                         clocks = <&apb1_gates 20>;
1252                         status = "disabled";
1253                 };
1254
1255                 uart5: serial@01c29400 {
1256                         compatible = "snps,dw-apb-uart";
1257                         reg = <0x01c29400 0x400>;
1258                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1259                         reg-shift = <2>;
1260                         reg-io-width = <4>;
1261                         clocks = <&apb1_gates 21>;
1262                         status = "disabled";
1263                 };
1264
1265                 uart6: serial@01c29800 {
1266                         compatible = "snps,dw-apb-uart";
1267                         reg = <0x01c29800 0x400>;
1268                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1269                         reg-shift = <2>;
1270                         reg-io-width = <4>;
1271                         clocks = <&apb1_gates 22>;
1272                         status = "disabled";
1273                 };
1274
1275                 uart7: serial@01c29c00 {
1276                         compatible = "snps,dw-apb-uart";
1277                         reg = <0x01c29c00 0x400>;
1278                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1279                         reg-shift = <2>;
1280                         reg-io-width = <4>;
1281                         clocks = <&apb1_gates 23>;
1282                         status = "disabled";
1283                 };
1284
1285                 i2c0: i2c@01c2ac00 {
1286                         compatible = "allwinner,sun7i-a20-i2c",
1287                                      "allwinner,sun4i-a10-i2c";
1288                         reg = <0x01c2ac00 0x400>;
1289                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1290                         clocks = <&apb1_gates 0>;
1291                         status = "disabled";
1292                         #address-cells = <1>;
1293                         #size-cells = <0>;
1294                 };
1295
1296                 i2c1: i2c@01c2b000 {
1297                         compatible = "allwinner,sun7i-a20-i2c",
1298                                      "allwinner,sun4i-a10-i2c";
1299                         reg = <0x01c2b000 0x400>;
1300                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1301                         clocks = <&apb1_gates 1>;
1302                         status = "disabled";
1303                         #address-cells = <1>;
1304                         #size-cells = <0>;
1305                 };
1306
1307                 i2c2: i2c@01c2b400 {
1308                         compatible = "allwinner,sun7i-a20-i2c",
1309                                      "allwinner,sun4i-a10-i2c";
1310                         reg = <0x01c2b400 0x400>;
1311                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1312                         clocks = <&apb1_gates 2>;
1313                         status = "disabled";
1314                         #address-cells = <1>;
1315                         #size-cells = <0>;
1316                 };
1317
1318                 i2c3: i2c@01c2b800 {
1319                         compatible = "allwinner,sun7i-a20-i2c",
1320                                      "allwinner,sun4i-a10-i2c";
1321                         reg = <0x01c2b800 0x400>;
1322                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1323                         clocks = <&apb1_gates 3>;
1324                         status = "disabled";
1325                         #address-cells = <1>;
1326                         #size-cells = <0>;
1327                 };
1328
1329                 i2c4: i2c@01c2c000 {
1330                         compatible = "allwinner,sun7i-a20-i2c",
1331                                      "allwinner,sun4i-a10-i2c";
1332                         reg = <0x01c2c000 0x400>;
1333                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1334                         clocks = <&apb1_gates 15>;
1335                         status = "disabled";
1336                         #address-cells = <1>;
1337                         #size-cells = <0>;
1338                 };
1339
1340                 gmac: ethernet@01c50000 {
1341                         compatible = "allwinner,sun7i-a20-gmac";
1342                         reg = <0x01c50000 0x10000>;
1343                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1344                         interrupt-names = "macirq";
1345                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1346                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1347                         snps,pbl = <2>;
1348                         snps,fixed-burst;
1349                         snps,force_sf_dma_mode;
1350                         status = "disabled";
1351                         #address-cells = <1>;
1352                         #size-cells = <0>;
1353                 };
1354
1355                 hstimer@01c60000 {
1356                         compatible = "allwinner,sun7i-a20-hstimer";
1357                         reg = <0x01c60000 0x1000>;
1358                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1359                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1360                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1361                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1362                         clocks = <&ahb_gates 28>;
1363                 };
1364
1365                 gic: interrupt-controller@01c81000 {
1366                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1367                         reg = <0x01c81000 0x1000>,
1368                               <0x01c82000 0x1000>,
1369                               <0x01c84000 0x2000>,
1370                               <0x01c86000 0x2000>;
1371                         interrupt-controller;
1372                         #interrupt-cells = <3>;
1373                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1374                 };
1375
1376                 ps20: ps2@01c2a000 {
1377                         compatible = "allwinner,sun4i-a10-ps2";
1378                         reg = <0x01c2a000 0x400>;
1379                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1380                         clocks = <&apb1_gates 6>;
1381                         status = "disabled";
1382                 };
1383
1384                 ps21: ps2@01c2a400 {
1385                         compatible = "allwinner,sun4i-a10-ps2";
1386                         reg = <0x01c2a400 0x400>;
1387                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1388                         clocks = <&apb1_gates 7>;
1389                         status = "disabled";
1390                 };
1391         };
1392 };