arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/clk.h>
  13 #include <linux/serial_8250.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/platform_data/edma.h>
  18 #include <linux/platform_data/gpio-davinci.h>
  19 #include <linux/platform_data/spi-davinci.h>
  20
  21 #include <asm/mach/map.h>
  22
  23 #include <mach/cputype.h>
  24 #include <mach/psc.h>
  25 #include <mach/mux.h>
  26 #include <mach/irqs.h>
  27 #include <mach/time.h>
  28 #include <mach/serial.h>
  29 #include <mach/common.h>
  30
  31 #include "davinci.h"
  32 #include "clock.h"
  33 #include "mux.h"
  34 #include "asp.h"
  35
  36 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
  37 #define DM355_OSD_BASE          (IO_PHYS + 0x70200)
  38 #define DM355_VENC_BASE         (IO_PHYS + 0x70400)
  39
  40 /*
  41  * Device specific clocks
  42  */
  43 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  44
  45 static struct pll_data pll1_data = {
  46         .num       = 1,
  47         .phys_base = DAVINCI_PLL1_BASE,
  48         .flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  49 };
  50
  51 static struct pll_data pll2_data = {
  52         .num       = 2,
  53         .phys_base = DAVINCI_PLL2_BASE,
  54         .flags     = PLL_HAS_PREDIV,
  55 };
  56
  57 static struct clk ref_clk = {
  58         .name = "ref_clk",
  59         /* FIXME -- crystal rate is board-specific */
  60         .rate = DM355_REF_FREQ,
  61 };
  62
  63 static struct clk pll1_clk = {
  64         .name = "pll1",
  65         .parent = &ref_clk,
  66         .flags = CLK_PLL,
  67         .pll_data = &pll1_data,
  68 };
  69
  70 static struct clk pll1_aux_clk = {
  71         .name = "pll1_aux_clk",
  72         .parent = &pll1_clk,
  73         .flags = CLK_PLL | PRE_PLL,
  74 };
  75
  76 static struct clk pll1_sysclk1 = {
  77         .name = "pll1_sysclk1",
  78         .parent = &pll1_clk,
  79         .flags = CLK_PLL,
  80         .div_reg = PLLDIV1,
  81 };
  82
  83 static struct clk pll1_sysclk2 = {
  84         .name = "pll1_sysclk2",
  85         .parent = &pll1_clk,
  86         .flags = CLK_PLL,
  87         .div_reg = PLLDIV2,
  88 };
  89
  90 static struct clk pll1_sysclk3 = {
  91         .name = "pll1_sysclk3",
  92         .parent = &pll1_clk,
  93         .flags = CLK_PLL,
  94         .div_reg = PLLDIV3,
  95 };
  96
  97 static struct clk pll1_sysclk4 = {
  98         .name = "pll1_sysclk4",
  99         .parent = &pll1_clk,
 100         .flags = CLK_PLL,
 101         .div_reg = PLLDIV4,
 102 };
 103
 104 static struct clk pll1_sysclkbp = {
 105         .name = "pll1_sysclkbp",
 106         .parent = &pll1_clk,
 107         .flags = CLK_PLL | PRE_PLL,
 108         .div_reg = BPDIV
 109 };
 110
 111 static struct clk vpss_dac_clk = {
 112         .name = "vpss_dac",
 113         .parent = &pll1_sysclk3,
 114         .lpsc = DM355_LPSC_VPSS_DAC,
 115 };
 116
 117 static struct clk vpss_master_clk = {
 118         .name = "vpss_master",
 119         .parent = &pll1_sysclk4,
 120         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 121         .flags = CLK_PSC,
 122 };
 123
 124 static struct clk vpss_slave_clk = {
 125         .name = "vpss_slave",
 126         .parent = &pll1_sysclk4,
 127         .lpsc = DAVINCI_LPSC_VPSSSLV,
 128 };
 129
 130 static struct clk clkout1_clk = {
 131         .name = "clkout1",
 132         .parent = &pll1_aux_clk,
 133         /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
 134 };
 135
 136 static struct clk clkout2_clk = {
 137         .name = "clkout2",
 138         .parent = &pll1_sysclkbp,
 139 };
 140
 141 static struct clk pll2_clk = {
 142         .name = "pll2",
 143         .parent = &ref_clk,
 144         .flags = CLK_PLL,
 145         .pll_data = &pll2_data,
 146 };
 147
 148 static struct clk pll2_sysclk1 = {
 149         .name = "pll2_sysclk1",
 150         .parent = &pll2_clk,
 151         .flags = CLK_PLL,
 152         .div_reg = PLLDIV1,
 153 };
 154
 155 static struct clk pll2_sysclkbp = {
 156         .name = "pll2_sysclkbp",
 157         .parent = &pll2_clk,
 158         .flags = CLK_PLL | PRE_PLL,
 159         .div_reg = BPDIV
 160 };
 161
 162 static struct clk clkout3_clk = {
 163         .name = "clkout3",
 164         .parent = &pll2_sysclkbp,
 165         /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
 166 };
 167
 168 static struct clk arm_clk = {
 169         .name = "arm_clk",
 170         .parent = &pll1_sysclk1,
 171         .lpsc = DAVINCI_LPSC_ARM,
 172         .flags = ALWAYS_ENABLED,
 173 };
 174
 175 /*
 176  * NOT LISTED below, and not touched by Linux
 177  *   - in SyncReset state by default
 178  *      .lpsc = DAVINCI_LPSC_TPCC,
 179  *      .lpsc = DAVINCI_LPSC_TPTC0,
 180  *      .lpsc = DAVINCI_LPSC_TPTC1,
 181  *      .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 182  *      .lpsc = DAVINCI_LPSC_MEMSTICK,
 183  *   - in Enabled state by default
 184  *      .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 185  *      .lpsc = DAVINCI_LPSC_SCR2,      // "bus"
 186  *      .lpsc = DAVINCI_LPSC_SCR3,      // "bus"
 187  *      .lpsc = DAVINCI_LPSC_SCR4,      // "bus"
 188  *      .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
 189  *      .lpsc = DAVINCI_LPSC_CFG27,     // "test"
 190  *      .lpsc = DAVINCI_LPSC_CFG3,      // "test"
 191  *      .lpsc = DAVINCI_LPSC_CFG5,      // "test"
 192  */
 193
 194 static struct clk mjcp_clk = {
 195         .name = "mjcp",
 196         .parent = &pll1_sysclk1,
 197         .lpsc = DAVINCI_LPSC_IMCOP,
 198 };
 199
 200 static struct clk uart0_clk = {
 201         .name = "uart0",
 202         .parent = &pll1_aux_clk,
 203         .lpsc = DAVINCI_LPSC_UART0,
 204 };
 205
 206 static struct clk uart1_clk = {
 207         .name = "uart1",
 208         .parent = &pll1_aux_clk,
 209         .lpsc = DAVINCI_LPSC_UART1,
 210 };
 211
 212 static struct clk uart2_clk = {
 213         .name = "uart2",
 214         .parent = &pll1_sysclk2,
 215         .lpsc = DAVINCI_LPSC_UART2,
 216 };
 217
 218 static struct clk i2c_clk = {
 219         .name = "i2c",
 220         .parent = &pll1_aux_clk,
 221         .lpsc = DAVINCI_LPSC_I2C,
 222 };
 223
 224 static struct clk asp0_clk = {
 225         .name = "asp0",
 226         .parent = &pll1_sysclk2,
 227         .lpsc = DAVINCI_LPSC_McBSP,
 228 };
 229
 230 static struct clk asp1_clk = {
 231         .name = "asp1",
 232         .parent = &pll1_sysclk2,
 233         .lpsc = DM355_LPSC_McBSP1,
 234 };
 235
 236 static struct clk mmcsd0_clk = {
 237         .name = "mmcsd0",
 238         .parent = &pll1_sysclk2,
 239         .lpsc = DAVINCI_LPSC_MMC_SD,
 240 };
 241
 242 static struct clk mmcsd1_clk = {
 243         .name = "mmcsd1",
 244         .parent = &pll1_sysclk2,
 245         .lpsc = DM355_LPSC_MMC_SD1,
 246 };
 247
 248 static struct clk spi0_clk = {
 249         .name = "spi0",
 250         .parent = &pll1_sysclk2,
 251         .lpsc = DAVINCI_LPSC_SPI,
 252 };
 253
 254 static struct clk spi1_clk = {
 255         .name = "spi1",
 256         .parent = &pll1_sysclk2,
 257         .lpsc = DM355_LPSC_SPI1,
 258 };
 259
 260 static struct clk spi2_clk = {
 261         .name = "spi2",
 262         .parent = &pll1_sysclk2,
 263         .lpsc = DM355_LPSC_SPI2,
 264 };
 265
 266 static struct clk gpio_clk = {
 267         .name = "gpio",
 268         .parent = &pll1_sysclk2,
 269         .lpsc = DAVINCI_LPSC_GPIO,
 270 };
 271
 272 static struct clk aemif_clk = {
 273         .name = "aemif",
 274         .parent = &pll1_sysclk2,
 275         .lpsc = DAVINCI_LPSC_AEMIF,
 276 };
 277
 278 static struct clk pwm0_clk = {
 279         .name = "pwm0",
 280         .parent = &pll1_aux_clk,
 281         .lpsc = DAVINCI_LPSC_PWM0,
 282 };
 283
 284 static struct clk pwm1_clk = {
 285         .name = "pwm1",
 286         .parent = &pll1_aux_clk,
 287         .lpsc = DAVINCI_LPSC_PWM1,
 288 };
 289
 290 static struct clk pwm2_clk = {
 291         .name = "pwm2",
 292         .parent = &pll1_aux_clk,
 293         .lpsc = DAVINCI_LPSC_PWM2,
 294 };
 295
 296 static struct clk pwm3_clk = {
 297         .name = "pwm3",
 298         .parent = &pll1_aux_clk,
 299         .lpsc = DM355_LPSC_PWM3,
 300 };
 301
 302 static struct clk timer0_clk = {
 303         .name = "timer0",
 304         .parent = &pll1_aux_clk,
 305         .lpsc = DAVINCI_LPSC_TIMER0,
 306 };
 307
 308 static struct clk timer1_clk = {
 309         .name = "timer1",
 310         .parent = &pll1_aux_clk,
 311         .lpsc = DAVINCI_LPSC_TIMER1,
 312 };
 313
 314 static struct clk timer2_clk = {
 315         .name = "timer2",
 316         .parent = &pll1_aux_clk,
 317         .lpsc = DAVINCI_LPSC_TIMER2,
 318         .usecount = 1,              /* REVISIT: why can't this be disabled? */
 319 };
 320
 321 static struct clk timer3_clk = {
 322         .name = "timer3",
 323         .parent = &pll1_aux_clk,
 324         .lpsc = DM355_LPSC_TIMER3,
 325 };
 326
 327 static struct clk rto_clk = {
 328         .name = "rto",
 329         .parent = &pll1_aux_clk,
 330         .lpsc = DM355_LPSC_RTO,
 331 };
 332
 333 static struct clk usb_clk = {
 334         .name = "usb",
 335         .parent = &pll1_sysclk2,
 336         .lpsc = DAVINCI_LPSC_USB,
 337 };
 338
 339 static struct clk_lookup dm355_clks[] = {
 340         CLK(NULL, "ref", &ref_clk),
 341         CLK(NULL, "pll1", &pll1_clk),
 342         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 343         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 344         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 345         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 346         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 347         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 348         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 349         CLK("vpss", "master", &vpss_master_clk),
 350         CLK("vpss", "slave", &vpss_slave_clk),
 351         CLK(NULL, "clkout1", &clkout1_clk),
 352         CLK(NULL, "clkout2", &clkout2_clk),
 353         CLK(NULL, "pll2", &pll2_clk),
 354         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 355         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 356         CLK(NULL, "clkout3", &clkout3_clk),
 357         CLK(NULL, "arm", &arm_clk),
 358         CLK(NULL, "mjcp", &mjcp_clk),
 359         CLK("serial8250.0", NULL, &uart0_clk),
 360         CLK("serial8250.1", NULL, &uart1_clk),
 361         CLK("serial8250.2", NULL, &uart2_clk),
 362         CLK("i2c_davinci.1", NULL, &i2c_clk),
 363         CLK("davinci-mcbsp.0", NULL, &asp0_clk),
 364         CLK("davinci-mcbsp.1", NULL, &asp1_clk),
 365         CLK("dm6441-mmc.0", NULL, &mmcsd0_clk),
 366         CLK("dm6441-mmc.1", NULL, &mmcsd1_clk),
 367         CLK("spi_davinci.0", NULL, &spi0_clk),
 368         CLK("spi_davinci.1", NULL, &spi1_clk),
 369         CLK("spi_davinci.2", NULL, &spi2_clk),
 370         CLK(NULL, "gpio", &gpio_clk),
 371         CLK(NULL, "aemif", &aemif_clk),
 372         CLK(NULL, "pwm0", &pwm0_clk),
 373         CLK(NULL, "pwm1", &pwm1_clk),
 374         CLK(NULL, "pwm2", &pwm2_clk),
 375         CLK(NULL, "pwm3", &pwm3_clk),
 376         CLK(NULL, "timer0", &timer0_clk),
 377         CLK(NULL, "timer1", &timer1_clk),
 378         CLK("davinci-wdt", NULL, &timer2_clk),
 379         CLK(NULL, "timer3", &timer3_clk),
 380         CLK(NULL, "rto", &rto_clk),
 381         CLK(NULL, "usb", &usb_clk),
 382         CLK(NULL, NULL, NULL),
 383 };
 384
 385 /*----------------------------------------------------------------------*/
 386
 387 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
 388
 389 static struct resource dm355_spi0_resources[] = {
 390         {
 391                 .start = 0x01c66000,
 392                 .end   = 0x01c667ff,
 393                 .flags = IORESOURCE_MEM,
 394         },
 395         {
 396                 .start = IRQ_DM355_SPINT0_0,
 397                 .flags = IORESOURCE_IRQ,
 398         },
 399         {
 400                 .start = 17,
 401                 .flags = IORESOURCE_DMA,
 402         },
 403         {
 404                 .start = 16,
 405                 .flags = IORESOURCE_DMA,
 406         },
 407 };
 408
 409 static struct davinci_spi_platform_data dm355_spi0_pdata = {
 410         .version        = SPI_VERSION_1,
 411         .num_chipselect = 2,
 412         .cshold_bug     = true,
 413         .dma_event_q    = EVENTQ_1,
 414         .prescaler_limit = 1,
 415 };
 416 static struct platform_device dm355_spi0_device = {
 417         .name = "spi_davinci",
 418         .id = 0,
 419         .dev = {
 420                 .dma_mask = &dm355_spi0_dma_mask,
 421                 .coherent_dma_mask = DMA_BIT_MASK(32),
 422                 .platform_data = &dm355_spi0_pdata,
 423         },
 424         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
 425         .resource = dm355_spi0_resources,
 426 };
 427
 428 void __init dm355_init_spi0(unsigned chipselect_mask,
 429                 const struct spi_board_info *info, unsigned len)
 430 {
 431         /* for now, assume we need MISO */
 432         davinci_cfg_reg(DM355_SPI0_SDI);
 433
 434         /* not all slaves will be wired up */
 435         if (chipselect_mask & BIT(0))
 436                 davinci_cfg_reg(DM355_SPI0_SDENA0);
 437         if (chipselect_mask & BIT(1))
 438                 davinci_cfg_reg(DM355_SPI0_SDENA1);
 439
 440         spi_register_board_info(info, len);
 441
 442         platform_device_register(&dm355_spi0_device);
 443 }
 444
 445 /*----------------------------------------------------------------------*/
 446
 447 #define INTMUX          0x18
 448 #define EVTMUX          0x1c
 449
 450 /*
 451  * Device specific mux setup
 452  *
 453  *      soc     description     mux  mode   mode  mux    dbg
 454  *                              reg  offset mask  mode
 455  */
 456 static const struct mux_config dm355_pins[] = {
 457 #ifdef CONFIG_DAVINCI_MUX
 458 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 459
 460 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 461 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 462 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 463 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 464 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 465 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 466
 467 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 468 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 469
 470 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 471 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 472 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 473 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 474 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 475 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 476
 477 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 478 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 479 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 480
 481 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 482 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 483 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 484
 485 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 486 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 487 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 488
 489 MUX_CFG(DM355,  VOUT_FIELD,     1,   18,    3,    1,     false)
 490 MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
 491 MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 492 MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 493 MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 494
 495 MUX_CFG(DM355,  VIN_PCLK,       0,   14,    1,    1,     false)
 496 MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
 497 MUX_CFG(DM355,  VIN_CAM_VD,     0,   12,    1,    1,     false)
 498 MUX_CFG(DM355,  VIN_CAM_HD,     0,   11,    1,    1,     false)
 499 MUX_CFG(DM355,  VIN_YIN_EN,     0,   10,    1,    1,     false)
 500 MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
 501 MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
 502 #endif
 503 };
 504
 505 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 506         [IRQ_DM355_CCDC_VDINT0]         = 2,
 507         [IRQ_DM355_CCDC_VDINT1]         = 6,
 508         [IRQ_DM355_CCDC_VDINT2]         = 6,
 509         [IRQ_DM355_IPIPE_HST]           = 6,
 510         [IRQ_DM355_H3AINT]              = 6,
 511         [IRQ_DM355_IPIPE_SDR]           = 6,
 512         [IRQ_DM355_IPIPEIFINT]          = 6,
 513         [IRQ_DM355_OSDINT]              = 7,
 514         [IRQ_DM355_VENCINT]             = 6,
 515         [IRQ_ASQINT]                    = 6,
 516         [IRQ_IMXINT]                    = 6,
 517         [IRQ_USBINT]                    = 4,
 518         [IRQ_DM355_RTOINT]              = 4,
 519         [IRQ_DM355_UARTINT2]            = 7,
 520         [IRQ_DM355_TINT6]               = 7,
 521         [IRQ_CCINT0]                    = 5,    /* dma */
 522         [IRQ_CCERRINT]                  = 5,    /* dma */
 523         [IRQ_TCERRINT0]                 = 5,    /* dma */
 524         [IRQ_TCERRINT]                  = 5,    /* dma */
 525         [IRQ_DM355_SPINT2_1]            = 7,
 526         [IRQ_DM355_TINT7]               = 4,
 527         [IRQ_DM355_SDIOINT0]            = 7,
 528         [IRQ_MBXINT]                    = 7,
 529         [IRQ_MBRINT]                    = 7,
 530         [IRQ_MMCINT]                    = 7,
 531         [IRQ_DM355_MMCINT1]             = 7,
 532         [IRQ_DM355_PWMINT3]             = 7,
 533         [IRQ_DDRINT]                    = 7,
 534         [IRQ_AEMIFINT]                  = 7,
 535         [IRQ_DM355_SDIOINT1]            = 4,
 536         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 537         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 538         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 539         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 540         [IRQ_PWMINT0]                   = 7,
 541         [IRQ_PWMINT1]                   = 7,
 542         [IRQ_PWMINT2]                   = 7,
 543         [IRQ_I2C]                       = 3,
 544         [IRQ_UARTINT0]                  = 3,
 545         [IRQ_UARTINT1]                  = 3,
 546         [IRQ_DM355_SPINT0_0]            = 3,
 547         [IRQ_DM355_SPINT0_1]            = 3,
 548         [IRQ_DM355_GPIO0]               = 3,
 549         [IRQ_DM355_GPIO1]               = 7,
 550         [IRQ_DM355_GPIO2]               = 4,
 551         [IRQ_DM355_GPIO3]               = 4,
 552         [IRQ_DM355_GPIO4]               = 7,
 553         [IRQ_DM355_GPIO5]               = 7,
 554         [IRQ_DM355_GPIO6]               = 7,
 555         [IRQ_DM355_GPIO7]               = 7,
 556         [IRQ_DM355_GPIO8]               = 7,
 557         [IRQ_DM355_GPIO9]               = 7,
 558         [IRQ_DM355_GPIOBNK0]            = 7,
 559         [IRQ_DM355_GPIOBNK1]            = 7,
 560         [IRQ_DM355_GPIOBNK2]            = 7,
 561         [IRQ_DM355_GPIOBNK3]            = 7,
 562         [IRQ_DM355_GPIOBNK4]            = 7,
 563         [IRQ_DM355_GPIOBNK5]            = 7,
 564         [IRQ_DM355_GPIOBNK6]            = 7,
 565         [IRQ_COMMTX]                    = 7,
 566         [IRQ_COMMRX]                    = 7,
 567         [IRQ_EMUINT]                    = 7,
 568 };
 569
 570 /*----------------------------------------------------------------------*/
 571
 572 static s8 queue_priority_mapping[][2] = {
 573         /* {event queue no, Priority} */
 574         {0, 3},
 575         {1, 7},
 576         {-1, -1},
 577 };
 578
 579 static struct edma_soc_info dm355_edma_pdata = {
 580         .queue_priority_mapping = queue_priority_mapping,
 581         .default_queue          = EVENTQ_1,
 582 };
 583
 584 static struct resource edma_resources[] = {
 585         {
 586                 .name   = "edma3_cc",
 587                 .start  = 0x01c00000,
 588                 .end    = 0x01c00000 + SZ_64K - 1,
 589                 .flags  = IORESOURCE_MEM,
 590         },
 591         {
 592                 .name   = "edma3_tc0",
 593                 .start  = 0x01c10000,
 594                 .end    = 0x01c10000 + SZ_1K - 1,
 595                 .flags  = IORESOURCE_MEM,
 596         },
 597         {
 598                 .name   = "edma3_tc1",
 599                 .start  = 0x01c10400,
 600                 .end    = 0x01c10400 + SZ_1K - 1,
 601                 .flags  = IORESOURCE_MEM,
 602         },
 603         {
 604                 .name   = "edma3_ccint",
 605                 .start  = IRQ_CCINT0,
 606                 .flags  = IORESOURCE_IRQ,
 607         },
 608         {
 609                 .name   = "edma3_ccerrint",
 610                 .start  = IRQ_CCERRINT,
 611                 .flags  = IORESOURCE_IRQ,
 612         },
 613         /* not using (or muxing) TC*_ERR */
 614 };
 615
 616 static const struct platform_device_info dm355_edma_device __initconst = {
 617         .name           = "edma",
 618         .id             = 0,
 619         .dma_mask       = DMA_BIT_MASK(32),
 620         .res            = edma_resources,
 621         .num_res        = ARRAY_SIZE(edma_resources),
 622         .data           = &dm355_edma_pdata,
 623         .size_data      = sizeof(dm355_edma_pdata),
 624 };
 625
 626 static struct resource dm355_asp1_resources[] = {
 627         {
 628                 .name   = "mpu",
 629                 .start  = DAVINCI_ASP1_BASE,
 630                 .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
 631                 .flags  = IORESOURCE_MEM,
 632         },
 633         {
 634                 .start  = DAVINCI_DMA_ASP1_TX,
 635                 .end    = DAVINCI_DMA_ASP1_TX,
 636                 .flags  = IORESOURCE_DMA,
 637         },
 638         {
 639                 .start  = DAVINCI_DMA_ASP1_RX,
 640                 .end    = DAVINCI_DMA_ASP1_RX,
 641                 .flags  = IORESOURCE_DMA,
 642         },
 643 };
 644
 645 static struct platform_device dm355_asp1_device = {
 646         .name           = "davinci-mcbsp",
 647         .id             = 1,
 648         .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
 649         .resource       = dm355_asp1_resources,
 650 };
 651
 652 static void dm355_ccdc_setup_pinmux(void)
 653 {
 654         davinci_cfg_reg(DM355_VIN_PCLK);
 655         davinci_cfg_reg(DM355_VIN_CAM_WEN);
 656         davinci_cfg_reg(DM355_VIN_CAM_VD);
 657         davinci_cfg_reg(DM355_VIN_CAM_HD);
 658         davinci_cfg_reg(DM355_VIN_YIN_EN);
 659         davinci_cfg_reg(DM355_VIN_CINL_EN);
 660         davinci_cfg_reg(DM355_VIN_CINH_EN);
 661 }
 662
 663 static struct resource dm355_vpss_resources[] = {
 664         {
 665                 /* VPSS BL Base address */
 666                 .name           = "vpss",
 667                 .start          = 0x01c70800,
 668                 .end            = 0x01c70800 + 0xff,
 669                 .flags          = IORESOURCE_MEM,
 670         },
 671         {
 672                 /* VPSS CLK Base address */
 673                 .name           = "vpss",
 674                 .start          = 0x01c70000,
 675                 .end            = 0x01c70000 + 0xf,
 676                 .flags          = IORESOURCE_MEM,
 677         },
 678 };
 679
 680 static struct platform_device dm355_vpss_device = {
 681         .name                   = "vpss",
 682         .id                     = -1,
 683         .dev.platform_data      = "dm355_vpss",
 684         .num_resources          = ARRAY_SIZE(dm355_vpss_resources),
 685         .resource               = dm355_vpss_resources,
 686 };
 687
 688 static struct resource vpfe_resources[] = {
 689         {
 690                 .start          = IRQ_VDINT0,
 691                 .end            = IRQ_VDINT0,
 692                 .flags          = IORESOURCE_IRQ,
 693         },
 694         {
 695                 .start          = IRQ_VDINT1,
 696                 .end            = IRQ_VDINT1,
 697                 .flags          = IORESOURCE_IRQ,
 698         },
 699 };
 700
 701 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 702 static struct resource dm355_ccdc_resource[] = {
 703         /* CCDC Base address */
 704         {
 705                 .flags          = IORESOURCE_MEM,
 706                 .start          = 0x01c70600,
 707                 .end            = 0x01c70600 + 0x1ff,
 708         },
 709 };
 710 static struct platform_device dm355_ccdc_dev = {
 711         .name           = "dm355_ccdc",
 712         .id             = -1,
 713         .num_resources  = ARRAY_SIZE(dm355_ccdc_resource),
 714         .resource       = dm355_ccdc_resource,
 715         .dev = {
 716                 .dma_mask               = &vpfe_capture_dma_mask,
 717                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 718                 .platform_data          = dm355_ccdc_setup_pinmux,
 719         },
 720 };
 721
 722 static struct platform_device vpfe_capture_dev = {
 723         .name           = CAPTURE_DRV_NAME,
 724         .id             = -1,
 725         .num_resources  = ARRAY_SIZE(vpfe_resources),
 726         .resource       = vpfe_resources,
 727         .dev = {
 728                 .dma_mask               = &vpfe_capture_dma_mask,
 729                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 730         },
 731 };
 732
 733 static struct resource dm355_osd_resources[] = {
 734         {
 735                 .start  = DM355_OSD_BASE,
 736                 .end    = DM355_OSD_BASE + 0x17f,
 737                 .flags  = IORESOURCE_MEM,
 738         },
 739 };
 740
 741 static struct platform_device dm355_osd_dev = {
 742         .name           = DM355_VPBE_OSD_SUBDEV_NAME,
 743         .id             = -1,
 744         .num_resources  = ARRAY_SIZE(dm355_osd_resources),
 745         .resource       = dm355_osd_resources,
 746         .dev            = {
 747                 .dma_mask               = &vpfe_capture_dma_mask,
 748                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 749         },
 750 };
 751
 752 static struct resource dm355_venc_resources[] = {
 753         {
 754                 .start  = IRQ_VENCINT,
 755                 .end    = IRQ_VENCINT,
 756                 .flags  = IORESOURCE_IRQ,
 757         },
 758         /* venc registers io space */
 759         {
 760                 .start  = DM355_VENC_BASE,
 761                 .end    = DM355_VENC_BASE + 0x17f,
 762                 .flags  = IORESOURCE_MEM,
 763         },
 764         /* VDAC config register io space */
 765         {
 766                 .start  = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
 767                 .end    = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
 768                 .flags  = IORESOURCE_MEM,
 769         },
 770 };
 771
 772 static struct resource dm355_v4l2_disp_resources[] = {
 773         {
 774                 .start  = IRQ_VENCINT,
 775                 .end    = IRQ_VENCINT,
 776                 .flags  = IORESOURCE_IRQ,
 777         },
 778         /* venc registers io space */
 779         {
 780                 .start  = DM355_VENC_BASE,
 781                 .end    = DM355_VENC_BASE + 0x17f,
 782                 .flags  = IORESOURCE_MEM,
 783         },
 784 };
 785
 786 static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
 787 {
 788         switch (if_type) {
 789         case MEDIA_BUS_FMT_SGRBG8_1X8:
 790                 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
 791                 break;
 792         case MEDIA_BUS_FMT_YUYV10_1X20:
 793                 if (field)
 794                         davinci_cfg_reg(DM355_VOUT_FIELD);
 795                 else
 796                         davinci_cfg_reg(DM355_VOUT_FIELD_G70);
 797                 break;
 798         default:
 799                 return -EINVAL;
 800         }
 801
 802         davinci_cfg_reg(DM355_VOUT_COUTL_EN);
 803         davinci_cfg_reg(DM355_VOUT_COUTH_EN);
 804
 805         return 0;
 806 }
 807
 808 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
 809                                    unsigned int pclock)
 810 {
 811         void __iomem *vpss_clk_ctrl_reg;
 812
 813         vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
 814
 815         switch (type) {
 816         case VPBE_ENC_STD:
 817                 writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
 818                        vpss_clk_ctrl_reg);
 819                 break;
 820         case VPBE_ENC_DV_TIMINGS:
 821                 if (pclock > 27000000)
 822                         /*
 823                          * For HD, use external clock source since we cannot
 824                          * support HD mode with internal clocks.
 825                          */
 826                         writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
 827                 break;
 828         default:
 829                 return -EINVAL;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static struct platform_device dm355_vpbe_display = {
 836         .name           = "vpbe-v4l2",
 837         .id             = -1,
 838         .num_resources  = ARRAY_SIZE(dm355_v4l2_disp_resources),
 839         .resource       = dm355_v4l2_disp_resources,
 840         .dev            = {
 841                 .dma_mask               = &vpfe_capture_dma_mask,
 842                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 843         },
 844 };
 845
 846 static struct venc_platform_data dm355_venc_pdata = {
 847         .setup_pinmux   = dm355_vpbe_setup_pinmux,
 848         .setup_clock    = dm355_venc_setup_clock,
 849 };
 850
 851 static struct platform_device dm355_venc_dev = {
 852         .name           = DM355_VPBE_VENC_SUBDEV_NAME,
 853         .id             = -1,
 854         .num_resources  = ARRAY_SIZE(dm355_venc_resources),
 855         .resource       = dm355_venc_resources,
 856         .dev            = {
 857                 .dma_mask               = &vpfe_capture_dma_mask,
 858                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 859                 .platform_data          = (void *)&dm355_venc_pdata,
 860         },
 861 };
 862
 863 static struct platform_device dm355_vpbe_dev = {
 864         .name           = "vpbe_controller",
 865         .id             = -1,
 866         .dev            = {
 867                 .dma_mask               = &vpfe_capture_dma_mask,
 868                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 869         },
 870 };
 871
 872 static struct resource dm355_gpio_resources[] = {
 873         {       /* registers */
 874                 .start  = DAVINCI_GPIO_BASE,
 875                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 876                 .flags  = IORESOURCE_MEM,
 877         },
 878         {       /* interrupt */
 879                 .start  = IRQ_DM355_GPIOBNK0,
 880                 .end    = IRQ_DM355_GPIOBNK6,
 881                 .flags  = IORESOURCE_IRQ,
 882         },
 883 };
 884
 885 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
 886         .ngpio          = 104,
 887 };
 888
 889 int __init dm355_gpio_register(void)
 890 {
 891         return davinci_gpio_register(dm355_gpio_resources,
 892                                      ARRAY_SIZE(dm355_gpio_resources),
 893                                      &dm355_gpio_platform_data);
 894 }
 895 /*----------------------------------------------------------------------*/
 896
 897 static struct map_desc dm355_io_desc[] = {
 898         {
 899                 .virtual        = IO_VIRT,
 900                 .pfn            = __phys_to_pfn(IO_PHYS),
 901                 .length         = IO_SIZE,
 902                 .type           = MT_DEVICE
 903         },
 904 };
 905
 906 /* Contents of JTAG ID register used to identify exact cpu type */
 907 static struct davinci_id dm355_ids[] = {
 908         {
 909                 .variant        = 0x0,
 910                 .part_no        = 0xb73b,
 911                 .manufacturer   = 0x00f,
 912                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 913                 .name           = "dm355",
 914         },
 915 };
 916
 917 static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 918
 919 /*
 920  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 921  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 922  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 923  * T1_TOP: Timer 1, top   :  <unused>
 924  */
 925 static struct davinci_timer_info dm355_timer_info = {
 926         .timers         = davinci_timer_instance,
 927         .clockevent_id  = T0_BOT,
 928         .clocksource_id = T0_TOP,
 929 };
 930
 931 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
 932         {
 933                 .mapbase        = DAVINCI_UART0_BASE,
 934                 .irq            = IRQ_UARTINT0,
 935                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 936                                   UPF_IOREMAP,
 937                 .iotype         = UPIO_MEM,
 938                 .regshift       = 2,
 939         },
 940         {
 941                 .flags  = 0,
 942         }
 943 };
 944 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
 945         {
 946                 .mapbase        = DAVINCI_UART1_BASE,
 947                 .irq            = IRQ_UARTINT1,
 948                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 949                                   UPF_IOREMAP,
 950                 .iotype         = UPIO_MEM,
 951                 .regshift       = 2,
 952         },
 953         {
 954                 .flags  = 0,
 955         }
 956 };
 957 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
 958         {
 959                 .mapbase        = DM355_UART2_BASE,
 960                 .irq            = IRQ_DM355_UARTINT2,
 961                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 962                                   UPF_IOREMAP,
 963                 .iotype         = UPIO_MEM,
 964                 .regshift       = 2,
 965         },
 966         {
 967                 .flags  = 0,
 968         }
 969 };
 970
 971 struct platform_device dm355_serial_device[] = {
 972         {
 973                 .name                   = "serial8250",
 974                 .id                     = PLAT8250_DEV_PLATFORM,
 975                 .dev                    = {
 976                         .platform_data  = dm355_serial0_platform_data,
 977                 }
 978         },
 979         {
 980                 .name                   = "serial8250",
 981                 .id                     = PLAT8250_DEV_PLATFORM1,
 982                 .dev                    = {
 983                         .platform_data  = dm355_serial1_platform_data,
 984                 }
 985         },
 986         {
 987                 .name                   = "serial8250",
 988                 .id                     = PLAT8250_DEV_PLATFORM2,
 989                 .dev                    = {
 990                         .platform_data  = dm355_serial2_platform_data,
 991                 }
 992         },
 993         {
 994         }
 995 };
 996
 997 static struct davinci_soc_info davinci_soc_info_dm355 = {
 998         .io_desc                = dm355_io_desc,
 999         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
1000         .jtag_id_reg            = 0x01c40028,
1001         .ids                    = dm355_ids,
1002         .ids_num                = ARRAY_SIZE(dm355_ids),
1003         .cpu_clks               = dm355_clks,
1004         .psc_bases              = dm355_psc_bases,
1005         .psc_bases_num          = ARRAY_SIZE(dm355_psc_bases),
1006         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
1007         .pinmux_pins            = dm355_pins,
1008         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
1009         .intc_base              = DAVINCI_ARM_INTC_BASE,
1010         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
1011         .intc_irq_prios         = dm355_default_priorities,
1012         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
1013         .timer_info             = &dm355_timer_info,
1014         .sram_dma               = 0x00010000,
1015         .sram_len               = SZ_32K,
1016 };
1017
1018 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
1019 {
1020         /* we don't use ASP1 IRQs, or we'd need to mux them ... */
1021         if (evt_enable & ASP1_TX_EVT_EN)
1022                 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
1023
1024         if (evt_enable & ASP1_RX_EVT_EN)
1025                 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
1026
1027         dm355_asp1_device.dev.platform_data = pdata;
1028         platform_device_register(&dm355_asp1_device);
1029 }
1030
1031 void __init dm355_init(void)
1032 {
1033         davinci_common_init(&davinci_soc_info_dm355);
1034         davinci_map_sysmod();
1035 }
1036
1037 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
1038                                 struct vpbe_config *vpbe_cfg)
1039 {
1040         if (vpfe_cfg || vpbe_cfg)
1041                 platform_device_register(&dm355_vpss_device);
1042
1043         if (vpfe_cfg) {
1044                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1045                 platform_device_register(&dm355_ccdc_dev);
1046                 platform_device_register(&vpfe_capture_dev);
1047         }
1048
1049         if (vpbe_cfg) {
1050                 dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
1051                 platform_device_register(&dm355_osd_dev);
1052                 platform_device_register(&dm355_venc_dev);
1053                 platform_device_register(&dm355_vpbe_dev);
1054                 platform_device_register(&dm355_vpbe_display);
1055         }
1056
1057         return 0;
1058 }
1059
1060 static int __init dm355_init_devices(void)
1061 {
1062         struct platform_device *edma_pdev;
1063         int ret = 0;
1064
1065         if (!cpu_is_davinci_dm355())
1066                 return 0;
1067
1068         davinci_cfg_reg(DM355_INT_EDMA_CC);
1069         edma_pdev = platform_device_register_full(&dm355_edma_device);
1070         if (IS_ERR(edma_pdev)) {
1071                 pr_warn("%s: Failed to register eDMA\n", __func__);
1072                 return PTR_ERR(edma_pdev);
1073         }
1074
1075         ret = davinci_init_wdt();
1076         if (ret)
1077                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1078
1079         return ret;
1080 }
1081 postcore_initcall(dm355_init_devices);