arch/arm/mach-exynos/pmu.c

   1 /*
   2  * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com/
   4  *
   5  * EXYNOS - CPU PMU(Power Management Unit) support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/io.h>
  13 #include <linux/of.h>
  14 #include <linux/of_address.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/notifier.h>
  18 #include <linux/reboot.h>
  19
  20
  21 #include "exynos-pmu.h"
  22 #include "regs-pmu.h"
  23
  24 #define PMU_TABLE_END   (-1U)
  25
  26 struct exynos_pmu_conf {
  27         unsigned int offset;
  28         u8 val[NUM_SYS_POWERDOWN];
  29 };
  30
  31 struct exynos_pmu_data {
  32         const struct exynos_pmu_conf *pmu_config;
  33         const struct exynos_pmu_conf *pmu_config_extra;
  34
  35         void (*pmu_init)(void);
  36         void (*powerdown_conf)(enum sys_powerdown);
  37         void (*powerdown_conf_extra)(enum sys_powerdown);
  38 };
  39
  40 struct exynos_pmu_context {
  41         struct device *dev;
  42         const struct exynos_pmu_data *pmu_data;
  43 };
  44
  45 static void __iomem *pmu_base_addr;
  46 static struct exynos_pmu_context *pmu_context;
  47
  48 static inline void pmu_raw_writel(u32 val, u32 offset)
  49 {
  50         writel_relaxed(val, pmu_base_addr + offset);
  51 }
  52
  53 static inline u32 pmu_raw_readl(u32 offset)
  54 {
  55         return readl_relaxed(pmu_base_addr + offset);
  56 }
  57
  58 static struct exynos_pmu_conf exynos3250_pmu_config[] = {
  59         /* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */
  60         { EXYNOS3_ARM_CORE0_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
  61         { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
  62         { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  63         { EXYNOS3_ARM_CORE1_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
  64         { EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
  65         { EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
  66         { EXYNOS3_ISP_ARM_SYS_PWR_REG,                  { 0x1, 0x0, 0x0} },
  67         { EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0} },
  68         { EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
  69         { EXYNOS3_ARM_COMMON_SYS_PWR_REG,               { 0x0, 0x0, 0x2} },
  70         { EXYNOS3_ARM_L2_SYS_PWR_REG,                   { 0x0, 0x0, 0x3} },
  71         { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG,             { 0x1, 0x1, 0x0} },
  72         { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG,             { 0x1, 0x1, 0x0} },
  73         { EXYNOS3_CMU_RESET_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
  74         { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG,           { 0x1, 0x1, 0x1} },
  75         { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
  76         { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG,       { 0x1, 0x1, 0x1} },
  77         { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
  78         { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
  79         { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
  80         { EXYNOS3_APLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
  81         { EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
  82         { EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
  83         { EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
  84         { EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
  85         { EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x1, 0x1} },
  86         { EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
  87         { EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
  88         { EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
  89         { EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
  90         { EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
  91         { EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
  92         { EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
  93         { EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
  94         { EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
  95         { EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
  96         { EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
  97         { EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
  98         { EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
  99         { EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 100         { EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
 101         { EXYNOS3_TOP_BUS_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
 102         { EXYNOS3_TOP_RETENTION_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
 103         { EXYNOS3_TOP_PWR_SYS_PWR_REG,                  { 0x3, 0x3, 0x3} },
 104         { EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG,          { 0x3, 0x0, 0x0} },
 105         { EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x1} },
 106         { EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG,          { 0x3, 0x3, 0x3} },
 107         { EXYNOS3_LOGIC_RESET_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
 108         { EXYNOS3_OSCCLK_GATE_SYS_PWR_REG,              { 0x1, 0x1, 0x1} },
 109         { EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },
 110         { EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG,      { 0x1, 0x0, 0x1} },
 111         { EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 112         { EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG,     { 0x1, 0x1, 0x0} },
 113         { EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 114         { EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 115         { EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 116         { EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 117         { EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 118         { EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
 119         { EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 120         { EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 121         { EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 122         { EXYNOS3_PAD_ISOLATION_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 123         { EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
 124         { EXYNOS3_XUSBXTI_SYS_PWR_REG,                  { 0x1, 0x1, 0x0} },
 125         { EXYNOS3_XXTI_SYS_PWR_REG,                     { 0x1, 0x1, 0x0} },
 126         { EXYNOS3_EXT_REGULATOR_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 127         { EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
 128         { EXYNOS3_GPIO_MODE_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
 129         { EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG,         { 0x1, 0x1, 0x0} },
 130         { EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 131         { EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
 132         { EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
 133         { EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
 134         { EXYNOS3_CAM_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 135         { EXYNOS3_MFC_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 136         { EXYNOS3_G3D_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 137         { EXYNOS3_LCD0_SYS_PWR_REG,                     { 0x7, 0x0, 0x0} },
 138         { EXYNOS3_ISP_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 139         { EXYNOS3_MAUDIO_SYS_PWR_REG,                   { 0x7, 0x0, 0x0} },
 140         { EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
 141         { PMU_TABLE_END,},
 142 };
 143
 144 static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
 145         /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
 146         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
 147         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
 148         { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
 149         { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
 150         { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
 151         { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
 152         { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
 153         { S5P_L2_0_LOWPWR,                      { 0x2, 0x2, 0x3 } },
 154         { S5P_L2_1_LOWPWR,                      { 0x2, 0x2, 0x3 } },
 155         { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
 156         { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
 157         { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
 158         { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
 159         { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
 160         { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
 161         { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
 162         { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x1, 0x0 } },
 163         { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x1, 0x0 } },
 164         { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x1, 0x0 } },
 165         { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x1, 0x0 } },
 166         { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x1, 0x0 } },
 167         { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x1, 0x0 } },
 168         { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x1, 0x0 } },
 169         { S5P_CMU_CLKSTOP_LCD1_LOWPWR,          { 0x1, 0x1, 0x0 } },
 170         { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x1, 0x0 } },
 171         { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x1, 0x0 } },
 172         { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x1, 0x0 } },
 173         { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x1, 0x0 } },
 174         { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x1, 0x0 } },
 175         { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x1, 0x0 } },
 176         { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x1, 0x0 } },
 177         { S5P_CMU_RESET_LCD1_LOWPWR,            { 0x1, 0x1, 0x0 } },
 178         { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
 179         { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x1, 0x0 } },
 180         { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
 181         { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
 182         { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
 183         { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
 184         { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
 185         { S5P_MODIMIF_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
 186         { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
 187         { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
 188         { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
 189         { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
 190         { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
 191         { S5P_PCIE_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
 192         { S5P_SATA_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
 193         { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
 194         { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
 195         { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
 196         { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
 197         { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
 198         { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
 199         { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
 200         { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
 201         { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
 202         { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
 203         { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
 204         { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
 205         { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
 206         { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
 207         { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
 208         { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
 209         { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
 210         { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
 211         { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
 212         { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
 213         { S5P_LCD1_LOWPWR,                      { 0x7, 0x0, 0x0 } },
 214         { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
 215         { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
 216         { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
 217         { PMU_TABLE_END,},
 218 };
 219
 220 static const struct exynos_pmu_conf exynos4x12_pmu_config[] = {
 221         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
 222         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
 223         { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
 224         { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
 225         { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
 226         { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
 227         { S5P_ISP_ARM_LOWPWR,                   { 0x1, 0x0, 0x0 } },
 228         { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR,     { 0x0, 0x0, 0x0 } },
 229         { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR,   { 0x0, 0x0, 0x0 } },
 230         { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
 231         { S5P_L2_0_LOWPWR,                      { 0x0, 0x0, 0x3 } },
 232         /* XXX_OPTION register should be set other field */
 233         { S5P_ARM_L2_0_OPTION,                  { 0x10, 0x10, 0x0 } },
 234         { S5P_L2_1_LOWPWR,                      { 0x0, 0x0, 0x3 } },
 235         { S5P_ARM_L2_1_OPTION,                  { 0x10, 0x10, 0x0 } },
 236         { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
 237         { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
 238         { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
 239         { S5P_DRAM_FREQ_DOWN_LOWPWR,            { 0x1, 0x1, 0x1 } },
 240         { S5P_DDRPHY_DLLOFF_LOWPWR,             { 0x1, 0x1, 0x1 } },
 241         { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR,        { 0x1, 0x1, 0x1 } },
 242         { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
 243         { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
 244         { S5P_CMU_RESET_COREBLK_LOWPWR,         { 0x1, 0x1, 0x0 } },
 245         { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
 246         { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
 247         { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
 248         { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
 249         { S5P_MPLLUSER_SYSCLK_LOWPWR,           { 0x1, 0x0, 0x0 } },
 250         { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x0, 0x0 } },
 251         { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x0, 0x0 } },
 252         { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x0, 0x0 } },
 253         { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x0, 0x0 } },
 254         { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x0, 0x0 } },
 255         { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x0, 0x0 } },
 256         { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x0, 0x0 } },
 257         { S5P_CMU_CLKSTOP_ISP_LOWPWR,           { 0x1, 0x0, 0x0 } },
 258         { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
 259         { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x0, 0x0 } },
 260         { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x0, 0x0 } },
 261         { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x0, 0x0 } },
 262         { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x0, 0x0 } },
 263         { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x0, 0x0 } },
 264         { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x0, 0x0 } },
 265         { S5P_CMU_RESET_ISP_LOWPWR,             { 0x1, 0x0, 0x0 } },
 266         { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
 267         { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x0, 0x0 } },
 268         { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
 269         { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
 270         { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
 271         { S5P_TOP_BUS_COREBLK_LOWPWR,           { 0x3, 0x0, 0x0 } },
 272         { S5P_TOP_RETENTION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x1 } },
 273         { S5P_TOP_PWR_COREBLK_LOWPWR,           { 0x3, 0x0, 0x3 } },
 274         { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
 275         { S5P_OSCCLK_GATE_LOWPWR,               { 0x1, 0x0, 0x1 } },
 276         { S5P_LOGIC_RESET_COREBLK_LOWPWR,       { 0x1, 0x1, 0x0 } },
 277         { S5P_OSCCLK_GATE_COREBLK_LOWPWR,       { 0x1, 0x0, 0x1 } },
 278         { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
 279         { S5P_ONENAND_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
 280         { S5P_HSI_MEM_LOWPWR,                   { 0x3, 0x0, 0x0 } },
 281         { S5P_HSI_MEM_OPTION,                   { 0x10, 0x10, 0x0 } },
 282         { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
 283         { S5P_G2D_ACP_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
 284         { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
 285         { S5P_USBOTG_MEM_OPTION,                { 0x10, 0x10, 0x0 } },
 286         { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
 287         { S5P_HSMMC_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
 288         { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
 289         { S5P_CSSYS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
 290         { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
 291         { S5P_SECSS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
 292         { S5P_ROTATOR_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
 293         { S5P_ROTATOR_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
 294         { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
 295         { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
 296         { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
 297         { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
 298         { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
 299         { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
 300         { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
 301         { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
 302         { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
 303         { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
 304         { S5P_PAD_ISOLATION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x0 } },
 305         { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
 306         { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
 307         { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
 308         { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
 309         { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
 310         { S5P_GPIO_MODE_COREBLK_LOWPWR,         { 0x1, 0x0, 0x0 } },
 311         { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
 312         { S5P_TOP_ASB_RESET_LOWPWR,             { 0x1, 0x1, 0x1 } },
 313         { S5P_TOP_ASB_ISOLATION_LOWPWR,         { 0x1, 0x0, 0x1 } },
 314         { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
 315         { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
 316         { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
 317         { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
 318         { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
 319         { S5P_ISP_LOWPWR,                       { 0x7, 0x0, 0x0 } },
 320         { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
 321         { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
 322         { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
 323         { S5P_CMU_SYSCLK_ISP_LOWPWR,            { 0x1, 0x0, 0x0 } },
 324         { S5P_CMU_SYSCLK_GPS_LOWPWR,            { 0x1, 0x0, 0x0 } },
 325         { PMU_TABLE_END,},
 326 };
 327
 328 static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
 329         { S5P_ARM_CORE2_LOWPWR,                 { 0x0, 0x0, 0x2 } },
 330         { S5P_DIS_IRQ_CORE2,                    { 0x0, 0x0, 0x0 } },
 331         { S5P_DIS_IRQ_CENTRAL2,                 { 0x0, 0x0, 0x0 } },
 332         { S5P_ARM_CORE3_LOWPWR,                 { 0x0, 0x0, 0x2 } },
 333         { S5P_DIS_IRQ_CORE3,                    { 0x0, 0x0, 0x0 } },
 334         { S5P_DIS_IRQ_CENTRAL3,                 { 0x0, 0x0, 0x0 } },
 335         { PMU_TABLE_END,},
 336 };
 337
 338 static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
 339         /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
 340         { EXYNOS5_ARM_CORE0_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
 341         { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
 342         { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
 343         { EXYNOS5_ARM_CORE1_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
 344         { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
 345         { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
 346         { EXYNOS5_FSYS_ARM_SYS_PWR_REG,                 { 0x1, 0x0, 0x0} },
 347         { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
 348         { EXYNOS5_ISP_ARM_SYS_PWR_REG,                  { 0x1, 0x0, 0x0} },
 349         { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0} },
 350         { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
 351         { EXYNOS5_ARM_COMMON_SYS_PWR_REG,               { 0x0, 0x0, 0x2} },
 352         { EXYNOS5_ARM_L2_SYS_PWR_REG,                   { 0x3, 0x3, 0x3} },
 353         { EXYNOS5_ARM_L2_OPTION,                        { 0x10, 0x10, 0x0 } },
 354         { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
 355         { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
 356         { EXYNOS5_CMU_RESET_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
 357         { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,      { 0x1, 0x0, 0x1} },
 358         { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,      { 0x1, 0x0, 0x1} },
 359         { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,         { 0x1, 0x1, 0x0} },
 360         { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,           { 0x1, 0x1, 0x1} },
 361         { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
 362         { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,           { 0x1, 0x1, 0x1} },
 363         { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
 364         { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
 365         { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
 366         { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
 367         { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
 368         { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
 369         { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
 370         { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
 371         { EXYNOS5_TOP_BUS_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
 372         { EXYNOS5_TOP_RETENTION_SYS_PWR_REG,            { 0x1, 0x0, 0x1} },
 373         { EXYNOS5_TOP_PWR_SYS_PWR_REG,                  { 0x3, 0x0, 0x3} },
 374         { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,           { 0x3, 0x0, 0x0} },
 375         { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,     { 0x1, 0x0, 0x1} },
 376         { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,           { 0x3, 0x0, 0x3} },
 377         { EXYNOS5_LOGIC_RESET_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
 378         { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,              { 0x1, 0x0, 0x1} },
 379         { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
 380         { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,       { 0x1, 0x0, 0x1} },
 381         { EXYNOS5_USBOTG_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
 382         { EXYNOS5_G2D_MEM_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
 383         { EXYNOS5_USBDRD_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
 384         { EXYNOS5_SDMMC_MEM_SYS_PWR_REG,                { 0x3, 0x0, 0x0} },
 385         { EXYNOS5_CSSYS_MEM_SYS_PWR_REG,                { 0x3, 0x0, 0x0} },
 386         { EXYNOS5_SECSS_MEM_SYS_PWR_REG,                { 0x3, 0x0, 0x0} },
 387         { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG,              { 0x3, 0x0, 0x0} },
 388         { EXYNOS5_INTRAM_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
 389         { EXYNOS5_INTROM_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
 390         { EXYNOS5_JPEG_MEM_SYS_PWR_REG,                 { 0x3, 0x0, 0x0} },
 391         { EXYNOS5_JPEG_MEM_OPTION,                      { 0x10, 0x10, 0x0} },
 392         { EXYNOS5_HSI_MEM_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
 393         { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
 394         { EXYNOS5_SATA_MEM_SYS_PWR_REG,                 { 0x3, 0x0, 0x0} },
 395         { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
 396         { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
 397         { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
 398         { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
 399         { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
 400         { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
 401         { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
 402         { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
 403         { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
 404         { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
 405         { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 406         { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
 407         { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
 408         { EXYNOS5_XUSBXTI_SYS_PWR_REG,                  { 0x1, 0x1, 0x1} },
 409         { EXYNOS5_XXTI_SYS_PWR_REG,                     { 0x1, 0x1, 0x0} },
 410         { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 411         { EXYNOS5_GPIO_MODE_SYS_PWR_REG,                { 0x1, 0x0, 0x0} },
 412         { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
 413         { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 414         { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
 415         { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,        { 0x1, 0x0, 0x1} },
 416         { EXYNOS5_GSCL_SYS_PWR_REG,                     { 0x7, 0x0, 0x0} },
 417         { EXYNOS5_ISP_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 418         { EXYNOS5_MFC_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 419         { EXYNOS5_G3D_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
 420         { EXYNOS5_DISP1_SYS_PWR_REG,                    { 0x7, 0x0, 0x0} },
 421         { EXYNOS5_MAU_SYS_PWR_REG,                      { 0x7, 0x7, 0x0} },
 422         { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
 423         { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
 424         { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
 425         { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
 426         { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
 427         { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,          { 0x1, 0x1, 0x0} },
 428         { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
 429         { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
 430         { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
 431         { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
 432         { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
 433         { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,           { 0x1, 0x1, 0x0} },
 434         { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
 435         { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 436         { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 437         { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 438         { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
 439         { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 440         { PMU_TABLE_END,},
 441 };
 442
 443 static struct exynos_pmu_conf exynos5420_pmu_config[] = {
 444         /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
 445         { EXYNOS5_ARM_CORE0_SYS_PWR_REG,                        { 0x0, 0x0, 0x0} },
 446         { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
 447         { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
 448         { EXYNOS5_ARM_CORE1_SYS_PWR_REG,                        { 0x0, 0x0, 0x0} },
 449         { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
 450         { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
 451         { EXYNOS5420_ARM_CORE2_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
 452         { EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 453         { EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 454         { EXYNOS5420_ARM_CORE3_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
 455         { EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 456         { EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 457         { EXYNOS5420_KFC_CORE0_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
 458         { EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 459         { EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 460         { EXYNOS5420_KFC_CORE1_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
 461         { EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 462         { EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 463         { EXYNOS5420_KFC_CORE2_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
 464         { EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 465         { EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 466         { EXYNOS5420_KFC_CORE3_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
 467         { EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
 468         { EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
 469         { EXYNOS5_ISP_ARM_SYS_PWR_REG,                          { 0x1, 0x0, 0x0} },
 470         { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 471         { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
 472         { EXYNOS5420_ARM_COMMON_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
 473         { EXYNOS5420_KFC_COMMON_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
 474         { EXYNOS5_ARM_L2_SYS_PWR_REG,                           { 0x0, 0x0, 0x0} },
 475         { EXYNOS5420_KFC_L2_SYS_PWR_REG,                        { 0x0, 0x0, 0x0} },
 476         { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,                     { 0x1, 0x0, 0x0} },
 477         { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,                     { 0x1, 0x0, 0x1} },
 478         { EXYNOS5_CMU_RESET_SYS_PWR_REG,                        { 0x1, 0x1, 0x0} },
 479         { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
 480         { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,              { 0x1, 0x0, 0x1} },
 481         { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,                 { 0x1, 0x1, 0x0} },
 482         { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,                   { 0x1, 0x0, 0x1} },
 483         { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,                    { 0x1, 0x1, 0x1} },
 484         { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,                   { 0x1, 0x0, 0x1} },
 485         { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
 486         { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
 487         { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
 488         { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x1, 0x0} },
 489         { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
 490         { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
 491         { EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
 492         { EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
 493         { EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
 494         { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,                  { 0x1, 0x0, 0x0} },
 495         { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,                  { 0x1, 0x0, 0x0} },
 496         { EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
 497         { EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
 498         { EXYNOS5_TOP_BUS_SYS_PWR_REG,                          { 0x3, 0x0, 0x0} },
 499         { EXYNOS5_TOP_RETENTION_SYS_PWR_REG,                    { 0x1, 0x1, 0x1} },
 500         { EXYNOS5_TOP_PWR_SYS_PWR_REG,                          { 0x3, 0x3, 0x0} },
 501         { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,                   { 0x3, 0x0, 0x0} },
 502         { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
 503         { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,                   { 0x3, 0x0, 0x0} },
 504         { EXYNOS5_LOGIC_RESET_SYS_PWR_REG,                      { 0x1, 0x1, 0x0} },
 505         { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,                      { 0x1, 0x0, 0x1} },
 506         { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,               { 0x1, 0x0, 0x0} },
 507         { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,               { 0x1, 0x0, 0x0} },
 508         { EXYNOS5420_INTRAM_MEM_SYS_PWR_REG,                    { 0x3, 0x0, 0x3} },
 509         { EXYNOS5420_INTROM_MEM_SYS_PWR_REG,                    { 0x3, 0x0, 0x3} },
 510         { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,               { 0x1, 0x0, 0x0} },
 511         { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
 512         { EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
 513         { EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 514         { EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 515         { EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 516         { EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 517         { EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 518         { EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG,             { 0x1, 0x0, 0x0} },
 519         { EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 520         { EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
 521         { EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG,             { 0x1, 0x0, 0x0} },
 522         { EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
 523         { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,                    { 0x1, 0x1, 0x0} },
 524         { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG,             { 0x1, 0x0, 0x0} },
 525         { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
 526         { EXYNOS5_XUSBXTI_SYS_PWR_REG,                          { 0x1, 0x1, 0x0} },
 527         { EXYNOS5_XXTI_SYS_PWR_REG,                             { 0x1, 0x1, 0x0} },
 528         { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,                    { 0x1, 0x1, 0x0} },
 529         { EXYNOS5_GPIO_MODE_SYS_PWR_REG,                        { 0x1, 0x0, 0x0} },
 530         { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,                 { 0x1, 0x1, 0x0} },
 531         { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,                    { 0x1, 0x1, 0x0} },
 532         { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,                    { 0x1, 0x1, 0x0} },
 533         { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,                { 0x1, 0x0, 0x0} },
 534         { EXYNOS5_GSCL_SYS_PWR_REG,                             { 0x7, 0x0, 0x0} },
 535         { EXYNOS5_ISP_SYS_PWR_REG,                              { 0x7, 0x0, 0x0} },
 536         { EXYNOS5_MFC_SYS_PWR_REG,                              { 0x7, 0x0, 0x0} },
 537         { EXYNOS5_G3D_SYS_PWR_REG,                              { 0x7, 0x0, 0x0} },
 538         { EXYNOS5420_DISP1_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
 539         { EXYNOS5420_MAU_SYS_PWR_REG,                           { 0x7, 0x7, 0x0} },
 540         { EXYNOS5420_G2D_SYS_PWR_REG,                           { 0x7, 0x0, 0x0} },
 541         { EXYNOS5420_MSC_SYS_PWR_REG,                           { 0x7, 0x0, 0x0} },
 542         { EXYNOS5420_FSYS_SYS_PWR_REG,                          { 0x7, 0x0, 0x0} },
 543         { EXYNOS5420_FSYS2_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
 544         { EXYNOS5420_PSGEN_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
 545         { EXYNOS5420_PERIC_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
 546         { EXYNOS5420_WCORE_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
 547         { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,                 { 0x0, 0x0, 0x0} },
 548         { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,                  { 0x0, 0x0, 0x0} },
 549         { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,                  { 0x0, 0x0, 0x0} },
 550         { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,                  { 0x0, 0x0, 0x0} },
 551         { EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
 552         { EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
 553         { EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
 554         { EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
 555         { EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
 556         { EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
 557         { EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
 558         { EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
 559         { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,                  { 0x0, 0x0, 0x0} },
 560         { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,                   { 0x0, 0x0, 0x0} },
 561         { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,                   { 0x0, 0x0, 0x0} },
 562         { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,                   { 0x0, 0x0, 0x0} },
 563         { EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
 564         { EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
 565         { EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
 566         { EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
 567         { EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
 568         { EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
 569         { EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
 570         { EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
 571         { EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
 572         { EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
 573         { EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
 574         { EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
 575         { EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
 576         { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,                   { 0x0, 0x0, 0x0} },
 577         { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
 578         { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
 579         { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
 580         { EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
 581         { EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,                 { 0x0, 0x0, 0x0} },
 582         { EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,                 { 0x0, 0x0, 0x0} },
 583         { EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,                 { 0x0, 0x0, 0x0} },
 584         { EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
 585         { PMU_TABLE_END,},
 586 };
 587
 588 static unsigned int const exynos3250_list_feed[] = {
 589         EXYNOS3_ARM_CORE_OPTION(0),
 590         EXYNOS3_ARM_CORE_OPTION(1),
 591         EXYNOS3_ARM_CORE_OPTION(2),
 592         EXYNOS3_ARM_CORE_OPTION(3),
 593         EXYNOS3_ARM_COMMON_OPTION,
 594         EXYNOS3_TOP_PWR_OPTION,
 595         EXYNOS3_CORE_TOP_PWR_OPTION,
 596         S5P_CAM_OPTION,
 597         S5P_MFC_OPTION,
 598         S5P_G3D_OPTION,
 599         S5P_LCD0_OPTION,
 600         S5P_ISP_OPTION,
 601 };
 602
 603 static void exynos3250_powerdown_conf_extra(enum sys_powerdown mode)
 604 {
 605         unsigned int i;
 606         unsigned int tmp;
 607
 608         /* Enable only SC_FEEDBACK */
 609         for (i = 0; i < ARRAY_SIZE(exynos3250_list_feed); i++) {
 610                 tmp = pmu_raw_readl(exynos3250_list_feed[i]);
 611                 tmp &= ~(EXYNOS3_OPTION_USE_SC_COUNTER);
 612                 tmp |= EXYNOS3_OPTION_USE_SC_FEEDBACK;
 613                 pmu_raw_writel(tmp, exynos3250_list_feed[i]);
 614         }
 615
 616         if (mode != SYS_SLEEP)
 617                 return;
 618
 619         pmu_raw_writel(XUSBXTI_DURATION, EXYNOS3_XUSBXTI_DURATION);
 620         pmu_raw_writel(XXTI_DURATION, EXYNOS3_XXTI_DURATION);
 621         pmu_raw_writel(EXT_REGULATOR_DURATION, EXYNOS3_EXT_REGULATOR_DURATION);
 622         pmu_raw_writel(EXT_REGULATOR_COREBLK_DURATION,
 623                        EXYNOS3_EXT_REGULATOR_COREBLK_DURATION);
 624 }
 625
 626 static unsigned int const exynos5_list_both_cnt_feed[] = {
 627         EXYNOS5_ARM_CORE0_OPTION,
 628         EXYNOS5_ARM_CORE1_OPTION,
 629         EXYNOS5_ARM_COMMON_OPTION,
 630         EXYNOS5_GSCL_OPTION,
 631         EXYNOS5_ISP_OPTION,
 632         EXYNOS5_MFC_OPTION,
 633         EXYNOS5_G3D_OPTION,
 634         EXYNOS5_DISP1_OPTION,
 635         EXYNOS5_MAU_OPTION,
 636         EXYNOS5_TOP_PWR_OPTION,
 637         EXYNOS5_TOP_PWR_SYSMEM_OPTION,
 638 };
 639
 640 static unsigned int const exynos5_list_disable_wfi_wfe[] = {
 641         EXYNOS5_ARM_CORE1_OPTION,
 642         EXYNOS5_FSYS_ARM_OPTION,
 643         EXYNOS5_ISP_ARM_OPTION,
 644 };
 645
 646 static unsigned int const exynos5420_list_disable_pmu_reg[] = {
 647         EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
 648         EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
 649         EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
 650         EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
 651         EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,
 652         EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,
 653         EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,
 654         EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,
 655         EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,
 656         EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,
 657         EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,
 658         EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
 659         EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
 660         EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
 661         EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,
 662         EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,
 663         EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,
 664         EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,
 665         EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,
 666         EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,
 667         EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,
 668         EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,
 669         EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,
 670         EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,
 671         EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,
 672         EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,
 673         EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,
 674         EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
 675         EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
 676         EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
 677         EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,
 678         EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,
 679         EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,
 680         EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,
 681         EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
 682 };
 683
 684 static void exynos_power_off(void)
 685 {
 686         unsigned int tmp;
 687
 688         pr_info("Power down.\n");
 689         tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
 690         tmp ^= (1 << 8);
 691         pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
 692
 693         /* Wait a little so we don't give a false warning below */
 694         mdelay(100);
 695
 696         pr_err("Power down failed, please power off system manually.\n");
 697         while (1)
 698                 ;
 699 }
 700
 701 static void exynos5420_powerdown_conf(enum sys_powerdown mode)
 702 {
 703         u32 this_cluster;
 704
 705         this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
 706
 707         /*
 708          * set the cluster id to IROM register to ensure that we wake
 709          * up with the current cluster.
 710          */
 711         pmu_raw_writel(this_cluster, EXYNOS_IROM_DATA2);
 712 }
 713
 714
 715 static void exynos5_powerdown_conf(enum sys_powerdown mode)
 716 {
 717         unsigned int i;
 718         unsigned int tmp;
 719
 720         /*
 721          * Enable both SC_FEEDBACK and SC_COUNTER
 722          */
 723         for (i = 0; i < ARRAY_SIZE(exynos5_list_both_cnt_feed); i++) {
 724                 tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
 725                 tmp |= (EXYNOS5_USE_SC_FEEDBACK |
 726                         EXYNOS5_USE_SC_COUNTER);
 727                 pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
 728         }
 729
 730         /*
 731          * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
 732          */
 733         tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
 734         tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
 735         pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
 736
 737         /*
 738          * Disable WFI/WFE on XXX_OPTION
 739          */
 740         for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_wfi_wfe); i++) {
 741                 tmp = pmu_raw_readl(exynos5_list_disable_wfi_wfe[i]);
 742                 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
 743                          EXYNOS5_OPTION_USE_STANDBYWFI);
 744                 pmu_raw_writel(tmp, exynos5_list_disable_wfi_wfe[i]);
 745         }
 746 }
 747
 748 void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 749 {
 750         unsigned int i;
 751
 752         const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
 753
 754         if (pmu_data->powerdown_conf)
 755                 pmu_data->powerdown_conf(mode);
 756
 757         if (pmu_data->pmu_config) {
 758                 for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END); i++)
 759                         pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
 760                                         pmu_data->pmu_config[i].offset);
 761         }
 762
 763         if (pmu_data->powerdown_conf_extra)
 764                 pmu_data->powerdown_conf_extra(mode);
 765
 766         if (pmu_data->pmu_config_extra) {
 767                 for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
 768                         pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
 769                                         pmu_data->pmu_config_extra[i].offset);
 770         }
 771 }
 772
 773 static void exynos3250_pmu_init(void)
 774 {
 775         unsigned int value;
 776
 777         /*
 778          * To prevent from issuing new bus request form L2 memory system
 779          * If core status is power down, should be set '1' to L2 power down
 780          */
 781         value = pmu_raw_readl(EXYNOS3_ARM_COMMON_OPTION);
 782         value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
 783         pmu_raw_writel(value, EXYNOS3_ARM_COMMON_OPTION);
 784
 785         /* Enable USE_STANDBY_WFI for all CORE */
 786         pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 787
 788         /*
 789          * Set PSHOLD port for output high
 790          */
 791         value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
 792         value |= S5P_PS_HOLD_OUTPUT_HIGH;
 793         pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
 794
 795         /*
 796          * Enable signal for PSHOLD port
 797          */
 798         value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
 799         value |= S5P_PS_HOLD_EN;
 800         pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
 801 }
 802
 803 static void exynos5250_pmu_init(void)
 804 {
 805         unsigned int value;
 806         /*
 807          * When SYS_WDTRESET is set, watchdog timer reset request
 808          * is ignored by power management unit.
 809          */
 810         value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
 811         value &= ~EXYNOS5_SYS_WDTRESET;
 812         pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
 813
 814         value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
 815         value &= ~EXYNOS5_SYS_WDTRESET;
 816         pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
 817 }
 818
 819 static void exynos5420_pmu_init(void)
 820 {
 821         unsigned int value;
 822         int i;
 823
 824         /*
 825          * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers
 826          * for local power blocks to Low initially as per Table 8-4:
 827          * "System-Level Power-Down Configuration Registers".
 828          */
 829         for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++)
 830                 pmu_raw_writel(0, exynos5420_list_disable_pmu_reg[i]);
 831
 832         /* Enable USE_STANDBY_WFI for all CORE */
 833         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 834
 835         value  = pmu_raw_readl(EXYNOS_L2_OPTION(0));
 836         value &= ~EXYNOS5_USE_RETENTION;
 837         pmu_raw_writel(value, EXYNOS_L2_OPTION(0));
 838
 839         value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
 840         value &= ~EXYNOS5_USE_RETENTION;
 841         pmu_raw_writel(value, EXYNOS_L2_OPTION(1));
 842
 843         /*
 844          * If L2_COMMON is turned off, clocks related to ATB async
 845          * bridge are gated. Thus, when ISP power is gated, LPI
 846          * may get stuck.
 847          */
 848         value = pmu_raw_readl(EXYNOS5420_LPI_MASK);
 849         value |= EXYNOS5420_ATB_ISP_ARM;
 850         pmu_raw_writel(value, EXYNOS5420_LPI_MASK);
 851
 852         value  = pmu_raw_readl(EXYNOS5420_LPI_MASK1);
 853         value |= EXYNOS5420_ATB_KFC;
 854         pmu_raw_writel(value, EXYNOS5420_LPI_MASK1);
 855
 856         /* Prevent issue of new bus request from L2 memory */
 857         value = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
 858         value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
 859         pmu_raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION);
 860
 861         value = pmu_raw_readl(EXYNOS5420_KFC_COMMON_OPTION);
 862         value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
 863         pmu_raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION);
 864
 865         /* This setting is to reduce suspend/resume time */
 866         pmu_raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3);
 867
 868         /* Serialized CPU wakeup of Eagle */
 869         pmu_raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE);
 870
 871         pmu_raw_writel(SPREAD_USE_STANDWFI,
 872                         EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI);
 873
 874         pmu_raw_writel(0x1, EXYNOS5420_UP_SCHEDULER);
 875         pr_info("EXYNOS5420 PMU initialized\n");
 876 }
 877
 878 static int pmu_restart_notify(struct notifier_block *this,
 879                 unsigned long code, void *unused)
 880 {
 881         pmu_raw_writel(0x1, EXYNOS_SWRESET);
 882
 883         return NOTIFY_DONE;
 884 }
 885
 886 static const struct exynos_pmu_data exynos3250_pmu_data = {
 887         .pmu_config     = exynos3250_pmu_config,
 888         .pmu_init       = exynos3250_pmu_init,
 889         .powerdown_conf_extra   = exynos3250_powerdown_conf_extra,
 890 };
 891
 892 static const struct exynos_pmu_data exynos4210_pmu_data = {
 893         .pmu_config     = exynos4210_pmu_config,
 894 };
 895
 896 static const struct exynos_pmu_data exynos4212_pmu_data = {
 897         .pmu_config     = exynos4x12_pmu_config,
 898 };
 899
 900 static const struct exynos_pmu_data exynos4412_pmu_data = {
 901         .pmu_config             = exynos4x12_pmu_config,
 902         .pmu_config_extra       = exynos4412_pmu_config,
 903 };
 904
 905 static const struct exynos_pmu_data exynos5250_pmu_data = {
 906         .pmu_config     = exynos5250_pmu_config,
 907         .pmu_init       = exynos5250_pmu_init,
 908         .powerdown_conf = exynos5_powerdown_conf,
 909 };
 910
 911 static struct exynos_pmu_data exynos5420_pmu_data = {
 912         .pmu_config     = exynos5420_pmu_config,
 913         .pmu_init       = exynos5420_pmu_init,
 914         .powerdown_conf = exynos5420_powerdown_conf,
 915 };
 916
 917 /*
 918  * PMU platform driver and devicetree bindings.
 919  */
 920 static const struct of_device_id exynos_pmu_of_device_ids[] = {
 921         {
 922                 .compatible = "samsung,exynos3250-pmu",
 923                 .data = &exynos3250_pmu_data,
 924         }, {
 925                 .compatible = "samsung,exynos4210-pmu",
 926                 .data = &exynos4210_pmu_data,
 927         }, {
 928                 .compatible = "samsung,exynos4212-pmu",
 929                 .data = &exynos4212_pmu_data,
 930         }, {
 931                 .compatible = "samsung,exynos4412-pmu",
 932                 .data = &exynos4412_pmu_data,
 933         }, {
 934                 .compatible = "samsung,exynos5250-pmu",
 935                 .data = &exynos5250_pmu_data,
 936         }, {
 937                 .compatible = "samsung,exynos5420-pmu",
 938                 .data = &exynos5420_pmu_data,
 939         },
 940         { /*sentinel*/ },
 941 };
 942
 943 /*
 944  * Exynos PMU restart notifier, handles restart functionality
 945  */
 946 static struct notifier_block pmu_restart_handler = {
 947         .notifier_call = pmu_restart_notify,
 948         .priority = 128,
 949 };
 950
 951 static int exynos_pmu_probe(struct platform_device *pdev)
 952 {
 953         const struct of_device_id *match;
 954         struct device *dev = &pdev->dev;
 955         struct resource *res;
 956         int ret;
 957
 958         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 959         pmu_base_addr = devm_ioremap_resource(dev, res);
 960         if (IS_ERR(pmu_base_addr))
 961                 return PTR_ERR(pmu_base_addr);
 962
 963         pmu_context = devm_kzalloc(&pdev->dev,
 964                         sizeof(struct exynos_pmu_context),
 965                         GFP_KERNEL);
 966         if (!pmu_context) {
 967                 dev_err(dev, "Cannot allocate memory.\n");
 968                 return -ENOMEM;
 969         }
 970         pmu_context->dev = dev;
 971
 972         match = of_match_node(exynos_pmu_of_device_ids, dev->of_node);
 973
 974         pmu_context->pmu_data = match->data;
 975
 976         if (pmu_context->pmu_data->pmu_init)
 977                 pmu_context->pmu_data->pmu_init();
 978
 979         platform_set_drvdata(pdev, pmu_context);
 980
 981         ret = register_restart_handler(&pmu_restart_handler);
 982         if (ret)
 983                 dev_warn(dev, "can't register restart handler err=%d\n", ret);
 984
 985         pm_power_off = exynos_power_off;
 986
 987         dev_dbg(dev, "Exynos PMU Driver probe done\n");
 988         return 0;
 989 }
 990
 991 static struct platform_driver exynos_pmu_driver = {
 992         .driver  = {
 993                 .name   = "exynos-pmu",
 994                 .of_match_table = exynos_pmu_of_device_ids,
 995         },
 996         .probe = exynos_pmu_probe,
 997 };
 998
 999 static int __init exynos_pmu_init(void)
1000 {
1001         return platform_driver_register(&exynos_pmu_driver);
1002
1003 }
1004 postcore_initcall(exynos_pmu_init);