2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Suspend support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/cpu_pm.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/of_address.h>
24 #include <linux/err.h>
25 #include <linux/regulator/machine.h>
27 #include <asm/cacheflush.h>
28 #include <asm/hardware/cache-l2x0.h>
29 #include <asm/firmware.h>
31 #include <asm/smp_scu.h>
32 #include <asm/suspend.h>
36 #include <plat/pm-common.h>
39 #include "exynos-pmu.h"
42 #define REG_TABLE_END (-1U)
44 #define EXYNOS5420_CPU_STATE 0x28
47 * struct exynos_wkup_irq - PMU IRQ to mask mapping
48 * @hwirq: Hardware IRQ signal of the PMU
49 * @mask: Mask in PMU wake-up mask register
51 struct exynos_wkup_irq {
56 struct exynos_pm_data {
57 const struct exynos_wkup_irq *wkup_irq;
58 unsigned int wake_disable_mask;
59 unsigned int *release_ret_regs;
61 void (*pm_prepare)(void);
62 void (*pm_resume_prepare)(void);
63 void (*pm_resume)(void);
64 int (*pm_suspend)(void);
65 int (*cpu_suspend)(unsigned long);
68 static const struct exynos_pm_data *pm_data;
70 static int exynos5420_cpu_state;
71 static unsigned int exynos_pmu_spare3;
77 static u32 exynos_irqwake_intmask = 0xffffffff;
79 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
80 { 73, BIT(1) }, /* RTC alarm */
81 { 74, BIT(2) }, /* RTC tick */
85 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
86 { 44, BIT(1) }, /* RTC alarm */
87 { 45, BIT(2) }, /* RTC tick */
91 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
92 { 43, BIT(1) }, /* RTC alarm */
93 { 44, BIT(2) }, /* RTC tick */
97 static unsigned int exynos_release_ret_regs[] = {
98 S5P_PAD_RET_MAUDIO_OPTION,
99 S5P_PAD_RET_GPIO_OPTION,
100 S5P_PAD_RET_UART_OPTION,
101 S5P_PAD_RET_MMCA_OPTION,
102 S5P_PAD_RET_MMCB_OPTION,
103 S5P_PAD_RET_EBIA_OPTION,
104 S5P_PAD_RET_EBIB_OPTION,
108 static unsigned int exynos3250_release_ret_regs[] = {
109 S5P_PAD_RET_MAUDIO_OPTION,
110 S5P_PAD_RET_GPIO_OPTION,
111 S5P_PAD_RET_UART_OPTION,
112 S5P_PAD_RET_MMCA_OPTION,
113 S5P_PAD_RET_MMCB_OPTION,
114 S5P_PAD_RET_EBIA_OPTION,
115 S5P_PAD_RET_EBIB_OPTION,
116 S5P_PAD_RET_MMC2_OPTION,
117 S5P_PAD_RET_SPI_OPTION,
121 static unsigned int exynos5420_release_ret_regs[] = {
122 EXYNOS_PAD_RET_DRAM_OPTION,
123 EXYNOS_PAD_RET_MAUDIO_OPTION,
124 EXYNOS_PAD_RET_JTAG_OPTION,
125 EXYNOS5420_PAD_RET_GPIO_OPTION,
126 EXYNOS5420_PAD_RET_UART_OPTION,
127 EXYNOS5420_PAD_RET_MMCA_OPTION,
128 EXYNOS5420_PAD_RET_MMCB_OPTION,
129 EXYNOS5420_PAD_RET_MMCC_OPTION,
130 EXYNOS5420_PAD_RET_HSI_OPTION,
131 EXYNOS_PAD_RET_EBIA_OPTION,
132 EXYNOS_PAD_RET_EBIB_OPTION,
133 EXYNOS5420_PAD_RET_SPI_OPTION,
134 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
138 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
140 const struct exynos_wkup_irq *wkup_irq;
142 if (!pm_data->wkup_irq)
144 wkup_irq = pm_data->wkup_irq;
146 while (wkup_irq->mask) {
147 if (wkup_irq->hwirq == data->hwirq) {
149 exynos_irqwake_intmask |= wkup_irq->mask;
151 exynos_irqwake_intmask &= ~wkup_irq->mask;
160 static struct irq_chip exynos_pmu_chip = {
162 .irq_eoi = irq_chip_eoi_parent,
163 .irq_mask = irq_chip_mask_parent,
164 .irq_unmask = irq_chip_unmask_parent,
165 .irq_retrigger = irq_chip_retrigger_hierarchy,
166 .irq_set_wake = exynos_irq_set_wake,
168 .irq_set_affinity = irq_chip_set_affinity_parent,
172 static int exynos_pmu_domain_xlate(struct irq_domain *domain,
173 struct device_node *controller,
175 unsigned int intsize,
176 unsigned long *out_hwirq,
177 unsigned int *out_type)
179 if (domain->of_node != controller)
180 return -EINVAL; /* Shouldn't happen, really... */
182 return -EINVAL; /* Not GIC compliant */
184 return -EINVAL; /* No PPI should point to this domain */
186 *out_hwirq = intspec[1];
187 *out_type = intspec[2];
191 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
193 unsigned int nr_irqs, void *data)
195 struct of_phandle_args *args = data;
196 struct of_phandle_args parent_args;
197 irq_hw_number_t hwirq;
200 if (args->args_count != 3)
201 return -EINVAL; /* Not GIC compliant */
202 if (args->args[0] != 0)
203 return -EINVAL; /* No PPI should point to this domain */
205 hwirq = args->args[1];
207 for (i = 0; i < nr_irqs; i++)
208 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
209 &exynos_pmu_chip, NULL);
212 parent_args.np = domain->parent->of_node;
213 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
216 static const struct irq_domain_ops exynos_pmu_domain_ops = {
217 .xlate = exynos_pmu_domain_xlate,
218 .alloc = exynos_pmu_domain_alloc,
219 .free = irq_domain_free_irqs_common,
222 static int __init exynos_pmu_irq_init(struct device_node *node,
223 struct device_node *parent)
225 struct irq_domain *parent_domain, *domain;
228 pr_err("%s: no parent, giving up\n", node->full_name);
232 parent_domain = irq_find_host(parent);
233 if (!parent_domain) {
234 pr_err("%s: unable to obtain parent domain\n", node->full_name);
238 pmu_base_addr = of_iomap(node, 0);
240 if (!pmu_base_addr) {
241 pr_err("%s: failed to find exynos pmu register\n",
246 domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
247 node, &exynos_pmu_domain_ops,
250 iounmap(pmu_base_addr);
257 #define EXYNOS_PMU_IRQ(symbol, name) OF_DECLARE_2(irqchip, symbol, name, exynos_pmu_irq_init)
259 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
260 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
261 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
262 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
263 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu");
264 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
265 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
267 static int exynos_cpu_do_idle(void)
269 /* issue the standby signal into the pm unit. */
272 pr_info("Failed to suspend the system\n");
273 return 1; /* Aborting suspend */
275 static void exynos_flush_cache_all(void)
281 static int exynos_cpu_suspend(unsigned long arg)
283 exynos_flush_cache_all();
284 return exynos_cpu_do_idle();
287 static int exynos3250_cpu_suspend(unsigned long arg)
290 return exynos_cpu_do_idle();
293 static int exynos5420_cpu_suspend(unsigned long arg)
295 /* MCPM works with HW CPU identifiers */
296 unsigned int mpidr = read_cpuid_mpidr();
297 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
298 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
300 __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
302 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
303 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
307 pr_info("Failed to suspend the system\n");
309 /* return value != 0 means failure */
313 static void exynos_pm_set_wakeup_mask(void)
315 /* Set wake-up mask registers */
316 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
317 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
320 static void exynos_pm_enter_sleep_mode(void)
322 /* Set value of power down register for sleep mode */
323 exynos_sys_powerdown_conf(SYS_SLEEP);
324 pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
327 static void exynos_pm_prepare(void)
329 exynos_set_delayed_reset_assertion(false);
331 /* Set wake-up mask registers */
332 exynos_pm_set_wakeup_mask();
334 exynos_pm_enter_sleep_mode();
336 /* ensure at least INFORM0 has the resume address */
337 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
340 static void exynos3250_pm_prepare(void)
344 /* Set wake-up mask registers */
345 exynos_pm_set_wakeup_mask();
347 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
348 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
349 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
351 exynos_pm_enter_sleep_mode();
353 /* ensure at least INFORM0 has the resume address */
354 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
357 static void exynos5420_pm_prepare(void)
361 /* Set wake-up mask registers */
362 exynos_pm_set_wakeup_mask();
364 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
366 * The cpu state needs to be saved and restored so that the
367 * secondary CPUs will enter low power start. Though the U-Boot
368 * is setting the cpu state with low power flag, the kernel
369 * needs to restore it back in case, the primary cpu fails to
370 * suspend for any reason.
372 exynos5420_cpu_state = __raw_readl(sysram_base_addr +
373 EXYNOS5420_CPU_STATE);
375 exynos_pm_enter_sleep_mode();
377 /* ensure at least INFORM0 has the resume address */
378 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
379 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
381 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
382 tmp &= ~EXYNOS5_USE_RETENTION;
383 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
385 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
386 tmp |= EXYNOS5420_UFS;
387 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
389 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
390 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
391 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
393 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
394 tmp |= EXYNOS5420_EMULATION;
395 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
397 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
398 tmp |= EXYNOS5420_EMULATION;
399 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
403 static int exynos_pm_suspend(void)
405 exynos_pm_central_suspend();
407 /* Setting SEQ_OPTION register */
408 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
409 S5P_CENTRAL_SEQ_OPTION);
411 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
412 exynos_cpu_save_register();
417 static int exynos5420_pm_suspend(void)
421 exynos_pm_central_suspend();
423 /* Setting SEQ_OPTION register */
425 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
427 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
428 S5P_CENTRAL_SEQ_OPTION);
430 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
431 S5P_CENTRAL_SEQ_OPTION);
435 static void exynos_pm_release_retention(void)
439 for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
440 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
441 pm_data->release_ret_regs[i]);
444 static void exynos_pm_resume(void)
446 u32 cpuid = read_cpuid_part();
448 if (exynos_pm_central_resume())
451 /* For release retention */
452 exynos_pm_release_retention();
454 if (cpuid == ARM_CPU_PART_CORTEX_A9)
455 scu_enable(S5P_VA_SCU);
457 if (call_firmware_op(resume) == -ENOSYS
458 && cpuid == ARM_CPU_PART_CORTEX_A9)
459 exynos_cpu_restore_register();
463 /* Clear SLEEP mode set in INFORM1 */
464 pmu_raw_writel(0x0, S5P_INFORM1);
465 exynos_set_delayed_reset_assertion(true);
468 static void exynos3250_pm_resume(void)
470 u32 cpuid = read_cpuid_part();
472 if (exynos_pm_central_resume())
475 /* For release retention */
476 exynos_pm_release_retention();
478 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
480 if (call_firmware_op(resume) == -ENOSYS
481 && cpuid == ARM_CPU_PART_CORTEX_A9)
482 exynos_cpu_restore_register();
486 /* Clear SLEEP mode set in INFORM1 */
487 pmu_raw_writel(0x0, S5P_INFORM1);
490 static void exynos5420_prepare_pm_resume(void)
492 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
493 WARN_ON(mcpm_cpu_powered_up());
496 static void exynos5420_pm_resume(void)
500 /* Restore the CPU0 low power state register */
501 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
502 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
503 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
505 /* Restore the sysram cpu state register */
506 __raw_writel(exynos5420_cpu_state,
507 sysram_base_addr + EXYNOS5420_CPU_STATE);
509 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
510 S5P_CENTRAL_SEQ_OPTION);
512 if (exynos_pm_central_resume())
515 /* For release retention */
516 exynos_pm_release_retention();
518 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
522 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
523 tmp &= ~EXYNOS5420_UFS;
524 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
526 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
527 tmp &= ~EXYNOS5420_EMULATION;
528 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
530 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
531 tmp &= ~EXYNOS5420_EMULATION;
532 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
534 /* Clear SLEEP mode set in INFORM1 */
535 pmu_raw_writel(0x0, S5P_INFORM1);
542 static int exynos_suspend_enter(suspend_state_t state)
548 S3C_PMDBG("%s: suspending the system...\n", __func__);
550 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
551 exynos_irqwake_intmask, exynos_get_eint_wake_mask());
553 if (exynos_irqwake_intmask == -1U
554 && exynos_get_eint_wake_mask() == -1U) {
555 pr_err("%s: No wake-up sources!\n", __func__);
556 pr_err("%s: Aborting sleep\n", __func__);
561 if (pm_data->pm_prepare)
562 pm_data->pm_prepare();
564 s3c_pm_check_store();
566 ret = call_firmware_op(suspend);
568 ret = cpu_suspend(0, pm_data->cpu_suspend);
572 if (pm_data->pm_resume_prepare)
573 pm_data->pm_resume_prepare();
574 s3c_pm_restore_uarts();
576 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
577 pmu_raw_readl(S5P_WAKEUP_STAT));
579 s3c_pm_check_restore();
581 S3C_PMDBG("%s: resuming the system...\n", __func__);
586 static int exynos_suspend_prepare(void)
591 * REVISIT: It would be better if struct platform_suspend_ops
592 * .prepare handler get the suspend_state_t as a parameter to
593 * avoid hard-coding the suspend to mem state. It's safe to do
594 * it now only because the suspend_valid_only_mem function is
595 * used as the .valid callback used to check if a given state
596 * is supported by the platform anyways.
598 ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
600 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
604 s3c_pm_check_prepare();
609 static void exynos_suspend_finish(void)
613 s3c_pm_check_cleanup();
615 ret = regulator_suspend_finish();
617 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
620 static const struct platform_suspend_ops exynos_suspend_ops = {
621 .enter = exynos_suspend_enter,
622 .prepare = exynos_suspend_prepare,
623 .finish = exynos_suspend_finish,
624 .valid = suspend_valid_only_mem,
627 static const struct exynos_pm_data exynos3250_pm_data = {
628 .wkup_irq = exynos3250_wkup_irq,
629 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
630 .release_ret_regs = exynos3250_release_ret_regs,
631 .pm_suspend = exynos_pm_suspend,
632 .pm_resume = exynos3250_pm_resume,
633 .pm_prepare = exynos3250_pm_prepare,
634 .cpu_suspend = exynos3250_cpu_suspend,
637 static const struct exynos_pm_data exynos4_pm_data = {
638 .wkup_irq = exynos4_wkup_irq,
639 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
640 .release_ret_regs = exynos_release_ret_regs,
641 .pm_suspend = exynos_pm_suspend,
642 .pm_resume = exynos_pm_resume,
643 .pm_prepare = exynos_pm_prepare,
644 .cpu_suspend = exynos_cpu_suspend,
647 static const struct exynos_pm_data exynos5250_pm_data = {
648 .wkup_irq = exynos5250_wkup_irq,
649 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
650 .release_ret_regs = exynos_release_ret_regs,
651 .pm_suspend = exynos_pm_suspend,
652 .pm_resume = exynos_pm_resume,
653 .pm_prepare = exynos_pm_prepare,
654 .cpu_suspend = exynos_cpu_suspend,
657 static const struct exynos_pm_data exynos5420_pm_data = {
658 .wkup_irq = exynos5250_wkup_irq,
659 .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
660 .release_ret_regs = exynos5420_release_ret_regs,
661 .pm_resume_prepare = exynos5420_prepare_pm_resume,
662 .pm_resume = exynos5420_pm_resume,
663 .pm_suspend = exynos5420_pm_suspend,
664 .pm_prepare = exynos5420_pm_prepare,
665 .cpu_suspend = exynos5420_cpu_suspend,
668 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
670 .compatible = "samsung,exynos3250-pmu",
671 .data = &exynos3250_pm_data,
673 .compatible = "samsung,exynos4210-pmu",
674 .data = &exynos4_pm_data,
676 .compatible = "samsung,exynos4212-pmu",
677 .data = &exynos4_pm_data,
679 .compatible = "samsung,exynos4412-pmu",
680 .data = &exynos4_pm_data,
682 .compatible = "samsung,exynos5250-pmu",
683 .data = &exynos5250_pm_data,
685 .compatible = "samsung,exynos5420-pmu",
686 .data = &exynos5420_pm_data,
691 static struct syscore_ops exynos_pm_syscore_ops;
693 void __init exynos_pm_init(void)
695 const struct of_device_id *match;
696 struct device_node *np;
699 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
701 pr_err("Failed to find PMU node\n");
705 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
706 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
710 pm_data = (const struct exynos_pm_data *) match->data;
712 /* All wakeup disable */
713 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
714 tmp |= pm_data->wake_disable_mask;
715 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
717 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
718 exynos_pm_syscore_ops.resume = pm_data->pm_resume;
720 register_syscore_ops(&exynos_pm_syscore_ops);
721 suspend_set_ops(&exynos_suspend_ops);