arch/arm/mach-imx/gpc.c

   1 /*
   2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/irqchip/arm-gic.h>
  24 #include "common.h"
  25 #include "hardware.h"
  26
  27 #define GPC_CNTR                0x000
  28 #define GPC_IMR1                0x008
  29 #define GPC_PGC_GPU_PDN         0x260
  30 #define GPC_PGC_GPU_PUPSCR      0x264
  31 #define GPC_PGC_GPU_PDNSCR      0x268
  32 #define GPC_PGC_CPU_PDN         0x2a0
  33 #define GPC_PGC_CPU_PUPSCR      0x2a4
  34 #define GPC_PGC_CPU_PDNSCR      0x2a8
  35 #define GPC_PGC_SW2ISO_SHIFT    0x8
  36 #define GPC_PGC_SW_SHIFT        0x0
  37
  38 #define IMR_NUM                 4
  39 #define GPC_MAX_IRQS            (IMR_NUM * 32)
  40
  41 #define GPU_VPU_PUP_REQ         BIT(1)
  42 #define GPU_VPU_PDN_REQ         BIT(0)
  43
  44 #define GPC_CLK_MAX             6
  45
  46 struct pu_domain {
  47         struct generic_pm_domain base;
  48         struct regulator *reg;
  49         struct clk *clk[GPC_CLK_MAX];
  50         int num_clks;
  51 };
  52
  53 static void __iomem *gpc_base;
  54 static u32 gpc_wake_irqs[IMR_NUM];
  55 static u32 gpc_saved_imrs[IMR_NUM];
  56
  57 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
  58 {
  59         writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
  60                 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
  61 }
  62
  63 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
  64 {
  65         writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
  66                 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
  67 }
  68
  69 void imx_gpc_set_arm_power_in_lpm(bool power_off)
  70 {
  71         writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
  72 }
  73
  74 void imx_gpc_pre_suspend(bool arm_power_off)
  75 {
  76         void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
  77         int i;
  78
  79         /* Tell GPC to power off ARM core when suspend */
  80         if (arm_power_off)
  81                 imx_gpc_set_arm_power_in_lpm(arm_power_off);
  82
  83         for (i = 0; i < IMR_NUM; i++) {
  84                 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
  85                 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
  86         }
  87 }
  88
  89 void imx_gpc_post_resume(void)
  90 {
  91         void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
  92         int i;
  93
  94         /* Keep ARM core powered on for other low-power modes */
  95         imx_gpc_set_arm_power_in_lpm(false);
  96
  97         for (i = 0; i < IMR_NUM; i++)
  98                 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
  99 }
 100
 101 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
 102 {
 103         unsigned int idx = d->hwirq / 32;
 104         u32 mask;
 105
 106         mask = 1 << d->hwirq % 32;
 107         gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
 108                                   gpc_wake_irqs[idx] & ~mask;
 109
 110         /*
 111          * Do *not* call into the parent, as the GIC doesn't have any
 112          * wake-up facility...
 113          */
 114         return 0;
 115 }
 116
 117 void imx_gpc_mask_all(void)
 118 {
 119         void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
 120         int i;
 121
 122         for (i = 0; i < IMR_NUM; i++) {
 123                 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
 124                 writel_relaxed(~0, reg_imr1 + i * 4);
 125         }
 126
 127 }
 128
 129 void imx_gpc_restore_all(void)
 130 {
 131         void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
 132         int i;
 133
 134         for (i = 0; i < IMR_NUM; i++)
 135                 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
 136 }
 137
 138 void imx_gpc_hwirq_unmask(unsigned int hwirq)
 139 {
 140         void __iomem *reg;
 141         u32 val;
 142
 143         reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
 144         val = readl_relaxed(reg);
 145         val &= ~(1 << hwirq % 32);
 146         writel_relaxed(val, reg);
 147 }
 148
 149 void imx_gpc_hwirq_mask(unsigned int hwirq)
 150 {
 151         void __iomem *reg;
 152         u32 val;
 153
 154         reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
 155         val = readl_relaxed(reg);
 156         val |= 1 << (hwirq % 32);
 157         writel_relaxed(val, reg);
 158 }
 159
 160 static void imx_gpc_irq_unmask(struct irq_data *d)
 161 {
 162         imx_gpc_hwirq_unmask(d->hwirq);
 163         irq_chip_unmask_parent(d);
 164 }
 165
 166 static void imx_gpc_irq_mask(struct irq_data *d)
 167 {
 168         imx_gpc_hwirq_mask(d->hwirq);
 169         irq_chip_mask_parent(d);
 170 }
 171
 172 static struct irq_chip imx_gpc_chip = {
 173         .name                   = "GPC",
 174         .irq_eoi                = irq_chip_eoi_parent,
 175         .irq_mask               = imx_gpc_irq_mask,
 176         .irq_unmask             = imx_gpc_irq_unmask,
 177         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 178         .irq_set_wake           = imx_gpc_irq_set_wake,
 179 #ifdef CONFIG_SMP
 180         .irq_set_affinity       = irq_chip_set_affinity_parent,
 181 #endif
 182 };
 183
 184 static int imx_gpc_domain_translate(struct irq_domain *d,
 185                                     struct irq_fwspec *fwspec,
 186                                     unsigned long *hwirq,
 187                                     unsigned int *type)
 188 {
 189         if (is_of_node(fwspec->fwnode)) {
 190                 if (fwspec->param_count != 3)
 191                         return -EINVAL;
 192
 193                 /* No PPI should point to this domain */
 194                 if (fwspec->param[0] != 0)
 195                         return -EINVAL;
 196
 197                 *hwirq = fwspec->param[1];
 198                 *type = fwspec->param[2];
 199                 return 0;
 200         }
 201
 202         return -EINVAL;
 203 }
 204
 205 static int imx_gpc_domain_alloc(struct irq_domain *domain,
 206                                   unsigned int irq,
 207                                   unsigned int nr_irqs, void *data)
 208 {
 209         struct irq_fwspec *fwspec = data;
 210         struct irq_fwspec parent_fwspec;
 211         irq_hw_number_t hwirq;
 212         int i;
 213
 214         if (fwspec->param_count != 3)
 215                 return -EINVAL; /* Not GIC compliant */
 216         if (fwspec->param[0] != 0)
 217                 return -EINVAL; /* No PPI should point to this domain */
 218
 219         hwirq = fwspec->param[1];
 220         if (hwirq >= GPC_MAX_IRQS)
 221                 return -EINVAL; /* Can't deal with this */
 222
 223         for (i = 0; i < nr_irqs; i++)
 224                 irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
 225                                               &imx_gpc_chip, NULL);
 226
 227         parent_fwspec = *fwspec;
 228         parent_fwspec.fwnode = domain->parent->fwnode;
 229         return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
 230                                             &parent_fwspec);
 231 }
 232
 233 static const struct irq_domain_ops imx_gpc_domain_ops = {
 234         .translate      = imx_gpc_domain_translate,
 235         .alloc          = imx_gpc_domain_alloc,
 236         .free           = irq_domain_free_irqs_common,
 237 };
 238
 239 static int __init imx_gpc_init(struct device_node *node,
 240                                struct device_node *parent)
 241 {
 242         struct irq_domain *parent_domain, *domain;
 243         int i;
 244
 245         if (!parent) {
 246                 pr_err("%s: no parent, giving up\n", node->full_name);
 247                 return -ENODEV;
 248         }
 249
 250         parent_domain = irq_find_host(parent);
 251         if (!parent_domain) {
 252                 pr_err("%s: unable to obtain parent domain\n", node->full_name);
 253                 return -ENXIO;
 254         }
 255
 256         gpc_base = of_iomap(node, 0);
 257         if (WARN_ON(!gpc_base))
 258                 return -ENOMEM;
 259
 260         domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
 261                                           node, &imx_gpc_domain_ops,
 262                                           NULL);
 263         if (!domain) {
 264                 iounmap(gpc_base);
 265                 return -ENOMEM;
 266         }
 267
 268         /* Initially mask all interrupts */
 269         for (i = 0; i < IMR_NUM; i++)
 270                 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
 271
 272         return 0;
 273 }
 274
 275 /*
 276  * We cannot use the IRQCHIP_DECLARE macro that lives in
 277  * drivers/irqchip, so we're forced to roll our own. Not very nice.
 278  */
 279 OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
 280
 281 void __init imx_gpc_check_dt(void)
 282 {
 283         struct device_node *np;
 284
 285         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
 286         if (WARN_ON(!np))
 287                 return;
 288
 289         if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
 290                 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
 291
 292                 /* map GPC, so that at least CPUidle and WARs keep working */
 293                 gpc_base = of_iomap(np, 0);
 294         }
 295 }
 296
 297 static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
 298 {
 299         int iso, iso2sw;
 300         u32 val;
 301
 302         /* Read ISO and ISO2SW power down delays */
 303         val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
 304         iso = val & 0x3f;
 305         iso2sw = (val >> 8) & 0x3f;
 306
 307         /* Gate off PU domain when GPU/VPU when powered down */
 308         writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
 309
 310         /* Request GPC to power down GPU/VPU */
 311         val = readl_relaxed(gpc_base + GPC_CNTR);
 312         val |= GPU_VPU_PDN_REQ;
 313         writel_relaxed(val, gpc_base + GPC_CNTR);
 314
 315         /* Wait ISO + ISO2SW IPG clock cycles */
 316         ndelay((iso + iso2sw) * 1000 / 66);
 317 }
 318
 319 static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
 320 {
 321         struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
 322
 323         _imx6q_pm_pu_power_off(genpd);
 324
 325         if (pu->reg)
 326                 regulator_disable(pu->reg);
 327
 328         return 0;
 329 }
 330
 331 static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
 332 {
 333         struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
 334         int i, ret, sw, sw2iso;
 335         u32 val;
 336
 337         if (pu->reg)
 338                 ret = regulator_enable(pu->reg);
 339         if (pu->reg && ret) {
 340                 pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
 341                 return ret;
 342         }
 343
 344         /* Enable reset clocks for all devices in the PU domain */
 345         for (i = 0; i < pu->num_clks; i++)
 346                 clk_prepare_enable(pu->clk[i]);
 347
 348         /* Gate off PU domain when GPU/VPU when powered down */
 349         writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
 350
 351         /* Read ISO and ISO2SW power down delays */
 352         val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
 353         sw = val & 0x3f;
 354         sw2iso = (val >> 8) & 0x3f;
 355
 356         /* Request GPC to power up GPU/VPU */
 357         val = readl_relaxed(gpc_base + GPC_CNTR);
 358         val |= GPU_VPU_PUP_REQ;
 359         writel_relaxed(val, gpc_base + GPC_CNTR);
 360
 361         /* Wait ISO + ISO2SW IPG clock cycles */
 362         ndelay((sw + sw2iso) * 1000 / 66);
 363
 364         /* Disable reset clocks for all devices in the PU domain */
 365         for (i = 0; i < pu->num_clks; i++)
 366                 clk_disable_unprepare(pu->clk[i]);
 367
 368         return 0;
 369 }
 370
 371 static struct generic_pm_domain imx6q_arm_domain = {
 372         .name = "ARM",
 373 };
 374
 375 static struct pu_domain imx6q_pu_domain = {
 376         .base = {
 377                 .name = "PU",
 378                 .power_off = imx6q_pm_pu_power_off,
 379                 .power_on = imx6q_pm_pu_power_on,
 380                 .power_off_latency_ns = 25000,
 381                 .power_on_latency_ns = 2000000,
 382         },
 383 };
 384
 385 static struct generic_pm_domain imx6sl_display_domain = {
 386         .name = "DISPLAY",
 387 };
 388
 389 static struct generic_pm_domain *imx_gpc_domains[] = {
 390         &imx6q_arm_domain,
 391         &imx6q_pu_domain.base,
 392         &imx6sl_display_domain,
 393 };
 394
 395 static struct genpd_onecell_data imx_gpc_onecell_data = {
 396         .domains = imx_gpc_domains,
 397         .num_domains = ARRAY_SIZE(imx_gpc_domains),
 398 };
 399
 400 static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
 401 {
 402         struct clk *clk;
 403         int i;
 404
 405         imx6q_pu_domain.reg = pu_reg;
 406
 407         for (i = 0; ; i++) {
 408                 clk = of_clk_get(dev->of_node, i);
 409                 if (IS_ERR(clk))
 410                         break;
 411                 if (i >= GPC_CLK_MAX) {
 412                         dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
 413                         goto clk_err;
 414                 }
 415                 imx6q_pu_domain.clk[i] = clk;
 416         }
 417         imx6q_pu_domain.num_clks = i;
 418
 419         /* Enable power always in case bootloader disabled it. */
 420         imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
 421
 422         if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
 423                 return 0;
 424
 425         pm_genpd_init(&imx6q_pu_domain.base, NULL, false);
 426         return of_genpd_add_provider_onecell(dev->of_node,
 427                                              &imx_gpc_onecell_data);
 428
 429 clk_err:
 430         while (i--)
 431                 clk_put(imx6q_pu_domain.clk[i]);
 432         return -EINVAL;
 433 }
 434
 435 static int imx_gpc_probe(struct platform_device *pdev)
 436 {
 437         struct regulator *pu_reg;
 438         int ret;
 439
 440         /* bail out if DT too old and doesn't provide the necessary info */
 441         if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
 442                 return 0;
 443
 444         pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
 445         if (PTR_ERR(pu_reg) == -ENODEV)
 446                 pu_reg = NULL;
 447         if (IS_ERR(pu_reg)) {
 448                 ret = PTR_ERR(pu_reg);
 449                 dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
 450                 return ret;
 451         }
 452
 453         return imx_gpc_genpd_init(&pdev->dev, pu_reg);
 454 }
 455
 456 static const struct of_device_id imx_gpc_dt_ids[] = {
 457         { .compatible = "fsl,imx6q-gpc" },
 458         { .compatible = "fsl,imx6sl-gpc" },
 459         { }
 460 };
 461
 462 static struct platform_driver imx_gpc_driver = {
 463         .driver = {
 464                 .name = "imx-gpc",
 465                 .of_match_table = imx_gpc_dt_ids,
 466         },
 467         .probe = imx_gpc_probe,
 468 };
 469
 470 static int __init imx_pgc_init(void)
 471 {
 472         return platform_driver_register(&imx_gpc_driver);
 473 }
 474 subsys_initcall(imx_pgc_init);