arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  * Note that this file is currently not in sync with autogeneration scripts.
  16  * The above note to be removed, once it is synced up.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/io.h>
  24 #include <linux/platform_data/gpio-omap.h>
  25 #include <linux/platform_data/hsmmc-omap.h>
  26 #include <linux/power/smartreflex.h>
  27 #include <linux/i2c-omap.h>
  28
  29 #include <linux/omap-dma.h>
  30
  31 #include <linux/platform_data/spi-omap2-mcspi.h>
  32 #include <linux/platform_data/asoc-ti-mcbsp.h>
  33 #include <linux/platform_data/iommu-omap.h>
  34 #include <plat/dmtimer.h>
  35
  36 #include "omap_hwmod.h"
  37 #include "omap_hwmod_common_data.h"
  38 #include "cm1_44xx.h"
  39 #include "cm2_44xx.h"
  40 #include "prm44xx.h"
  41 #include "prm-regbits-44xx.h"
  42 #include "i2c.h"
  43 #include "wd_timer.h"
  44
  45 /* Base offset for all OMAP4 interrupts external to MPUSS */
  46 #define OMAP44XX_IRQ_GIC_START  32
  47
  48 /* Base offset for all OMAP4 dma requests */
  49 #define OMAP44XX_DMA_REQ_START  1
  50
  51 /*
  52  * IP blocks
  53  */
  54
  55 /*
  56  * 'dmm' class
  57  * instance(s): dmm
  58  */
  59 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  60         .name   = "dmm",
  61 };
  62
  63 /* dmm */
  64 static struct omap_hwmod omap44xx_dmm_hwmod = {
  65         .name           = "dmm",
  66         .class          = &omap44xx_dmm_hwmod_class,
  67         .clkdm_name     = "l3_emif_clkdm",
  68         .prcm = {
  69                 .omap4 = {
  70                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  71                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  72                 },
  73         },
  74 };
  75
  76 /*
  77  * 'l3' class
  78  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  79  */
  80 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  81         .name   = "l3",
  82 };
  83
  84 /* l3_instr */
  85 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  86         .name           = "l3_instr",
  87         .class          = &omap44xx_l3_hwmod_class,
  88         .clkdm_name     = "l3_instr_clkdm",
  89         .prcm = {
  90                 .omap4 = {
  91                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  92                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  93                         .modulemode   = MODULEMODE_HWCTRL,
  94                 },
  95         },
  96 };
  97
  98 /* l3_main_1 */
  99 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 100         .name           = "l3_main_1",
 101         .class          = &omap44xx_l3_hwmod_class,
 102         .clkdm_name     = "l3_1_clkdm",
 103         .prcm = {
 104                 .omap4 = {
 105                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 106                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 107                 },
 108         },
 109 };
 110
 111 /* l3_main_2 */
 112 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 113         .name           = "l3_main_2",
 114         .class          = &omap44xx_l3_hwmod_class,
 115         .clkdm_name     = "l3_2_clkdm",
 116         .prcm = {
 117                 .omap4 = {
 118                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 119                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 120                 },
 121         },
 122 };
 123
 124 /* l3_main_3 */
 125 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 126         .name           = "l3_main_3",
 127         .class          = &omap44xx_l3_hwmod_class,
 128         .clkdm_name     = "l3_instr_clkdm",
 129         .prcm = {
 130                 .omap4 = {
 131                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 132                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 133                         .modulemode   = MODULEMODE_HWCTRL,
 134                 },
 135         },
 136 };
 137
 138 /*
 139  * 'l4' class
 140  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 141  */
 142 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 143         .name   = "l4",
 144 };
 145
 146 /* l4_abe */
 147 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 148         .name           = "l4_abe",
 149         .class          = &omap44xx_l4_hwmod_class,
 150         .clkdm_name     = "abe_clkdm",
 151         .prcm = {
 152                 .omap4 = {
 153                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 154                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 155                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 156                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 157                 },
 158         },
 159 };
 160
 161 /* l4_cfg */
 162 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 163         .name           = "l4_cfg",
 164         .class          = &omap44xx_l4_hwmod_class,
 165         .clkdm_name     = "l4_cfg_clkdm",
 166         .prcm = {
 167                 .omap4 = {
 168                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 169                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 170                 },
 171         },
 172 };
 173
 174 /* l4_per */
 175 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 176         .name           = "l4_per",
 177         .class          = &omap44xx_l4_hwmod_class,
 178         .clkdm_name     = "l4_per_clkdm",
 179         .prcm = {
 180                 .omap4 = {
 181                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 182                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 183                 },
 184         },
 185 };
 186
 187 /* l4_wkup */
 188 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 189         .name           = "l4_wkup",
 190         .class          = &omap44xx_l4_hwmod_class,
 191         .clkdm_name     = "l4_wkup_clkdm",
 192         .prcm = {
 193                 .omap4 = {
 194                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 195                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 196                 },
 197         },
 198 };
 199
 200 /*
 201  * 'mpu_bus' class
 202  * instance(s): mpu_private
 203  */
 204 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 205         .name   = "mpu_bus",
 206 };
 207
 208 /* mpu_private */
 209 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 210         .name           = "mpu_private",
 211         .class          = &omap44xx_mpu_bus_hwmod_class,
 212         .clkdm_name     = "mpuss_clkdm",
 213         .prcm = {
 214                 .omap4 = {
 215                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 216                 },
 217         },
 218 };
 219
 220 /*
 221  * 'ocp_wp_noc' class
 222  * instance(s): ocp_wp_noc
 223  */
 224 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 225         .name   = "ocp_wp_noc",
 226 };
 227
 228 /* ocp_wp_noc */
 229 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 230         .name           = "ocp_wp_noc",
 231         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 232         .clkdm_name     = "l3_instr_clkdm",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 236                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 237                         .modulemode   = MODULEMODE_HWCTRL,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * Modules omap_hwmod structures
 244  *
 245  * The following IPs are excluded for the moment because:
 246  * - They do not need an explicit SW control using omap_hwmod API.
 247  * - They still need to be validated with the driver
 248  *   properly adapted to omap_hwmod / omap_device
 249  *
 250  * usim
 251  */
 252
 253 /*
 254  * 'aess' class
 255  * audio engine sub system
 256  */
 257
 258 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 259         .rev_offs       = 0x0000,
 260         .sysc_offs      = 0x0010,
 261         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 262         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 263                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 264                            MSTANDBY_SMART_WKUP),
 265         .sysc_fields    = &omap_hwmod_sysc_type2,
 266 };
 267
 268 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 269         .name   = "aess",
 270         .sysc   = &omap44xx_aess_sysc,
 271         .enable_preprogram = omap_hwmod_aess_preprogram,
 272 };
 273
 274 /* aess */
 275 static struct omap_hwmod omap44xx_aess_hwmod = {
 276         .name           = "aess",
 277         .class          = &omap44xx_aess_hwmod_class,
 278         .clkdm_name     = "abe_clkdm",
 279         .main_clk       = "aess_fclk",
 280         .prcm = {
 281                 .omap4 = {
 282                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 283                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 284                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 285                         .modulemode   = MODULEMODE_SWCTRL,
 286                 },
 287         },
 288 };
 289
 290 /*
 291  * 'c2c' class
 292  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 293  * soc
 294  */
 295
 296 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 297         .name   = "c2c",
 298 };
 299
 300 /* c2c */
 301 static struct omap_hwmod omap44xx_c2c_hwmod = {
 302         .name           = "c2c",
 303         .class          = &omap44xx_c2c_hwmod_class,
 304         .clkdm_name     = "d2d_clkdm",
 305         .prcm = {
 306                 .omap4 = {
 307                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 308                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 309                 },
 310         },
 311 };
 312
 313 /*
 314  * 'counter' class
 315  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 316  */
 317
 318 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 319         .rev_offs       = 0x0000,
 320         .sysc_offs      = 0x0004,
 321         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 322         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 323         .sysc_fields    = &omap_hwmod_sysc_type1,
 324 };
 325
 326 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 327         .name   = "counter",
 328         .sysc   = &omap44xx_counter_sysc,
 329 };
 330
 331 /* counter_32k */
 332 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 333         .name           = "counter_32k",
 334         .class          = &omap44xx_counter_hwmod_class,
 335         .clkdm_name     = "l4_wkup_clkdm",
 336         .flags          = HWMOD_SWSUP_SIDLE,
 337         .main_clk       = "sys_32k_ck",
 338         .prcm = {
 339                 .omap4 = {
 340                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 341                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 342                 },
 343         },
 344 };
 345
 346 /*
 347  * 'ctrl_module' class
 348  * attila core control module + core pad control module + wkup pad control
 349  * module + attila wkup control module
 350  */
 351
 352 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 353         .rev_offs       = 0x0000,
 354         .sysc_offs      = 0x0010,
 355         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 356         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 357                            SIDLE_SMART_WKUP),
 358         .sysc_fields    = &omap_hwmod_sysc_type2,
 359 };
 360
 361 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 362         .name   = "ctrl_module",
 363         .sysc   = &omap44xx_ctrl_module_sysc,
 364 };
 365
 366 /* ctrl_module_core */
 367 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 368         .name           = "ctrl_module_core",
 369         .class          = &omap44xx_ctrl_module_hwmod_class,
 370         .clkdm_name     = "l4_cfg_clkdm",
 371         .prcm = {
 372                 .omap4 = {
 373                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 374                 },
 375         },
 376 };
 377
 378 /* ctrl_module_pad_core */
 379 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 380         .name           = "ctrl_module_pad_core",
 381         .class          = &omap44xx_ctrl_module_hwmod_class,
 382         .clkdm_name     = "l4_cfg_clkdm",
 383         .prcm = {
 384                 .omap4 = {
 385                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 386                 },
 387         },
 388 };
 389
 390 /* ctrl_module_wkup */
 391 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 392         .name           = "ctrl_module_wkup",
 393         .class          = &omap44xx_ctrl_module_hwmod_class,
 394         .clkdm_name     = "l4_wkup_clkdm",
 395         .prcm = {
 396                 .omap4 = {
 397                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 398                 },
 399         },
 400 };
 401
 402 /* ctrl_module_pad_wkup */
 403 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 404         .name           = "ctrl_module_pad_wkup",
 405         .class          = &omap44xx_ctrl_module_hwmod_class,
 406         .clkdm_name     = "l4_wkup_clkdm",
 407         .prcm = {
 408                 .omap4 = {
 409                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 410                 },
 411         },
 412 };
 413
 414 /*
 415  * 'debugss' class
 416  * debug and emulation sub system
 417  */
 418
 419 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 420         .name   = "debugss",
 421 };
 422
 423 /* debugss */
 424 static struct omap_hwmod omap44xx_debugss_hwmod = {
 425         .name           = "debugss",
 426         .class          = &omap44xx_debugss_hwmod_class,
 427         .clkdm_name     = "emu_sys_clkdm",
 428         .main_clk       = "trace_clk_div_ck",
 429         .prcm = {
 430                 .omap4 = {
 431                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 432                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 433                 },
 434         },
 435 };
 436
 437 /*
 438  * 'dma' class
 439  * dma controller for data exchange between memory to memory (i.e. internal or
 440  * external memory) and gp peripherals to memory or memory to gp peripherals
 441  */
 442
 443 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 444         .rev_offs       = 0x0000,
 445         .sysc_offs      = 0x002c,
 446         .syss_offs      = 0x0028,
 447         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 448                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 449                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 450                            SYSS_HAS_RESET_STATUS),
 451         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 452                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 453         .sysc_fields    = &omap_hwmod_sysc_type1,
 454 };
 455
 456 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 457         .name   = "dma",
 458         .sysc   = &omap44xx_dma_sysc,
 459 };
 460
 461 /* dma dev_attr */
 462 static struct omap_dma_dev_attr dma_dev_attr = {
 463         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 464                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 465         .lch_count      = 32,
 466 };
 467
 468 /* dma_system */
 469 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 470         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 471         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 472         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 473         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 474         { .irq = -1 }
 475 };
 476
 477 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 478         .name           = "dma_system",
 479         .class          = &omap44xx_dma_hwmod_class,
 480         .clkdm_name     = "l3_dma_clkdm",
 481         .mpu_irqs       = omap44xx_dma_system_irqs,
 482         .xlate_irq      = omap4_xlate_irq,
 483         .main_clk       = "l3_div_ck",
 484         .prcm = {
 485                 .omap4 = {
 486                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 487                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 488                 },
 489         },
 490         .dev_attr       = &dma_dev_attr,
 491 };
 492
 493 /*
 494  * 'dmic' class
 495  * digital microphone controller
 496  */
 497
 498 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 499         .rev_offs       = 0x0000,
 500         .sysc_offs      = 0x0010,
 501         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 502                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 503         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 504                            SIDLE_SMART_WKUP),
 505         .sysc_fields    = &omap_hwmod_sysc_type2,
 506 };
 507
 508 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 509         .name   = "dmic",
 510         .sysc   = &omap44xx_dmic_sysc,
 511 };
 512
 513 /* dmic */
 514 static struct omap_hwmod omap44xx_dmic_hwmod = {
 515         .name           = "dmic",
 516         .class          = &omap44xx_dmic_hwmod_class,
 517         .clkdm_name     = "abe_clkdm",
 518         .main_clk       = "func_dmic_abe_gfclk",
 519         .prcm = {
 520                 .omap4 = {
 521                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 522                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 523                         .modulemode   = MODULEMODE_SWCTRL,
 524                 },
 525         },
 526 };
 527
 528 /*
 529  * 'dsp' class
 530  * dsp sub-system
 531  */
 532
 533 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 534         .name   = "dsp",
 535 };
 536
 537 /* dsp */
 538 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 539         { .name = "dsp", .rst_shift = 0 },
 540 };
 541
 542 static struct omap_hwmod omap44xx_dsp_hwmod = {
 543         .name           = "dsp",
 544         .class          = &omap44xx_dsp_hwmod_class,
 545         .clkdm_name     = "tesla_clkdm",
 546         .rst_lines      = omap44xx_dsp_resets,
 547         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 548         .main_clk       = "dpll_iva_m4x2_ck",
 549         .prcm = {
 550                 .omap4 = {
 551                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 552                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 553                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 554                         .modulemode   = MODULEMODE_HWCTRL,
 555                 },
 556         },
 557 };
 558
 559 /*
 560  * 'dss' class
 561  * display sub-system
 562  */
 563
 564 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 565         .rev_offs       = 0x0000,
 566         .syss_offs      = 0x0014,
 567         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 568 };
 569
 570 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 571         .name   = "dss",
 572         .sysc   = &omap44xx_dss_sysc,
 573         .reset  = omap_dss_reset,
 574 };
 575
 576 /* dss */
 577 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 578         { .role = "sys_clk", .clk = "dss_sys_clk" },
 579         { .role = "tv_clk", .clk = "dss_tv_clk" },
 580         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 581 };
 582
 583 static struct omap_hwmod omap44xx_dss_hwmod = {
 584         .name           = "dss_core",
 585         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 586         .class          = &omap44xx_dss_hwmod_class,
 587         .clkdm_name     = "l3_dss_clkdm",
 588         .main_clk       = "dss_dss_clk",
 589         .prcm = {
 590                 .omap4 = {
 591                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 592                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 593                         .modulemode   = MODULEMODE_SWCTRL,
 594                 },
 595         },
 596         .opt_clks       = dss_opt_clks,
 597         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 598 };
 599
 600 /*
 601  * 'dispc' class
 602  * display controller
 603  */
 604
 605 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 606         .rev_offs       = 0x0000,
 607         .sysc_offs      = 0x0010,
 608         .syss_offs      = 0x0014,
 609         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 610                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 611                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 612                            SYSS_HAS_RESET_STATUS),
 613         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 614                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 615         .sysc_fields    = &omap_hwmod_sysc_type1,
 616 };
 617
 618 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 619         .name   = "dispc",
 620         .sysc   = &omap44xx_dispc_sysc,
 621 };
 622
 623 /* dss_dispc */
 624 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 625         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 626         { .irq = -1 }
 627 };
 628
 629 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 630         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 631         { .dma_req = -1 }
 632 };
 633
 634 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 635         .manager_count          = 3,
 636         .has_framedonetv_irq    = 1
 637 };
 638
 639 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 640         .name           = "dss_dispc",
 641         .class          = &omap44xx_dispc_hwmod_class,
 642         .clkdm_name     = "l3_dss_clkdm",
 643         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 644         .xlate_irq      = omap4_xlate_irq,
 645         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 646         .main_clk       = "dss_dss_clk",
 647         .prcm = {
 648                 .omap4 = {
 649                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 650                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 651                 },
 652         },
 653         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 654         .parent_hwmod   = &omap44xx_dss_hwmod,
 655 };
 656
 657 /*
 658  * 'dsi' class
 659  * display serial interface controller
 660  */
 661
 662 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 663         .rev_offs       = 0x0000,
 664         .sysc_offs      = 0x0010,
 665         .syss_offs      = 0x0014,
 666         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 667                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 668                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 669         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 670         .sysc_fields    = &omap_hwmod_sysc_type1,
 671 };
 672
 673 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 674         .name   = "dsi",
 675         .sysc   = &omap44xx_dsi_sysc,
 676 };
 677
 678 /* dss_dsi1 */
 679 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 680         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 681         { .irq = -1 }
 682 };
 683
 684 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 685         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 686         { .dma_req = -1 }
 687 };
 688
 689 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 690         { .role = "sys_clk", .clk = "dss_sys_clk" },
 691 };
 692
 693 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 694         .name           = "dss_dsi1",
 695         .class          = &omap44xx_dsi_hwmod_class,
 696         .clkdm_name     = "l3_dss_clkdm",
 697         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 698         .xlate_irq      = omap4_xlate_irq,
 699         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 700         .main_clk       = "dss_dss_clk",
 701         .prcm = {
 702                 .omap4 = {
 703                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 704                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 705                 },
 706         },
 707         .opt_clks       = dss_dsi1_opt_clks,
 708         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 709         .parent_hwmod   = &omap44xx_dss_hwmod,
 710 };
 711
 712 /* dss_dsi2 */
 713 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 714         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 715         { .irq = -1 }
 716 };
 717
 718 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 719         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 720         { .dma_req = -1 }
 721 };
 722
 723 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 724         { .role = "sys_clk", .clk = "dss_sys_clk" },
 725 };
 726
 727 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 728         .name           = "dss_dsi2",
 729         .class          = &omap44xx_dsi_hwmod_class,
 730         .clkdm_name     = "l3_dss_clkdm",
 731         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 732         .xlate_irq      = omap4_xlate_irq,
 733         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 734         .main_clk       = "dss_dss_clk",
 735         .prcm = {
 736                 .omap4 = {
 737                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 738                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 739                 },
 740         },
 741         .opt_clks       = dss_dsi2_opt_clks,
 742         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 743         .parent_hwmod   = &omap44xx_dss_hwmod,
 744 };
 745
 746 /*
 747  * 'hdmi' class
 748  * hdmi controller
 749  */
 750
 751 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 752         .rev_offs       = 0x0000,
 753         .sysc_offs      = 0x0010,
 754         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 755                            SYSC_HAS_SOFTRESET),
 756         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 757                            SIDLE_SMART_WKUP),
 758         .sysc_fields    = &omap_hwmod_sysc_type2,
 759 };
 760
 761 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 762         .name   = "hdmi",
 763         .sysc   = &omap44xx_hdmi_sysc,
 764 };
 765
 766 /* dss_hdmi */
 767 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 768         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 769         { .irq = -1 }
 770 };
 771
 772 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 773         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 774         { .dma_req = -1 }
 775 };
 776
 777 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 778         { .role = "sys_clk", .clk = "dss_sys_clk" },
 779 };
 780
 781 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 782         .name           = "dss_hdmi",
 783         .class          = &omap44xx_hdmi_hwmod_class,
 784         .clkdm_name     = "l3_dss_clkdm",
 785         /*
 786          * HDMI audio requires to use no-idle mode. Hence,
 787          * set idle mode by software.
 788          */
 789         .flags          = HWMOD_SWSUP_SIDLE,
 790         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 791         .xlate_irq      = omap4_xlate_irq,
 792         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 793         .main_clk       = "dss_48mhz_clk",
 794         .prcm = {
 795                 .omap4 = {
 796                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 797                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 798                 },
 799         },
 800         .opt_clks       = dss_hdmi_opt_clks,
 801         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 802         .parent_hwmod   = &omap44xx_dss_hwmod,
 803 };
 804
 805 /*
 806  * 'rfbi' class
 807  * remote frame buffer interface
 808  */
 809
 810 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 811         .rev_offs       = 0x0000,
 812         .sysc_offs      = 0x0010,
 813         .syss_offs      = 0x0014,
 814         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 815                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 816         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 817         .sysc_fields    = &omap_hwmod_sysc_type1,
 818 };
 819
 820 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 821         .name   = "rfbi",
 822         .sysc   = &omap44xx_rfbi_sysc,
 823 };
 824
 825 /* dss_rfbi */
 826 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 827         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 828         { .dma_req = -1 }
 829 };
 830
 831 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 832         { .role = "ick", .clk = "l3_div_ck" },
 833 };
 834
 835 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 836         .name           = "dss_rfbi",
 837         .class          = &omap44xx_rfbi_hwmod_class,
 838         .clkdm_name     = "l3_dss_clkdm",
 839         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 840         .main_clk       = "dss_dss_clk",
 841         .prcm = {
 842                 .omap4 = {
 843                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 844                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 845                 },
 846         },
 847         .opt_clks       = dss_rfbi_opt_clks,
 848         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 849         .parent_hwmod   = &omap44xx_dss_hwmod,
 850 };
 851
 852 /*
 853  * 'venc' class
 854  * video encoder
 855  */
 856
 857 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 858         .name   = "venc",
 859 };
 860
 861 /* dss_venc */
 862 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 863         .name           = "dss_venc",
 864         .class          = &omap44xx_venc_hwmod_class,
 865         .clkdm_name     = "l3_dss_clkdm",
 866         .main_clk       = "dss_tv_clk",
 867         .prcm = {
 868                 .omap4 = {
 869                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 870                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 871                 },
 872         },
 873         .parent_hwmod   = &omap44xx_dss_hwmod,
 874 };
 875
 876 /*
 877  * 'elm' class
 878  * bch error location module
 879  */
 880
 881 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 882         .rev_offs       = 0x0000,
 883         .sysc_offs      = 0x0010,
 884         .syss_offs      = 0x0014,
 885         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 886                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 887                            SYSS_HAS_RESET_STATUS),
 888         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 889         .sysc_fields    = &omap_hwmod_sysc_type1,
 890 };
 891
 892 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 893         .name   = "elm",
 894         .sysc   = &omap44xx_elm_sysc,
 895 };
 896
 897 /* elm */
 898 static struct omap_hwmod omap44xx_elm_hwmod = {
 899         .name           = "elm",
 900         .class          = &omap44xx_elm_hwmod_class,
 901         .clkdm_name     = "l4_per_clkdm",
 902         .prcm = {
 903                 .omap4 = {
 904                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 905                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 906                 },
 907         },
 908 };
 909
 910 /*
 911  * 'emif' class
 912  * external memory interface no1
 913  */
 914
 915 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 916         .rev_offs       = 0x0000,
 917 };
 918
 919 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 920         .name   = "emif",
 921         .sysc   = &omap44xx_emif_sysc,
 922 };
 923
 924 /* emif1 */
 925 static struct omap_hwmod omap44xx_emif1_hwmod = {
 926         .name           = "emif1",
 927         .class          = &omap44xx_emif_hwmod_class,
 928         .clkdm_name     = "l3_emif_clkdm",
 929         .flags          = HWMOD_INIT_NO_IDLE,
 930         .main_clk       = "ddrphy_ck",
 931         .prcm = {
 932                 .omap4 = {
 933                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 934                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 935                         .modulemode   = MODULEMODE_HWCTRL,
 936                 },
 937         },
 938 };
 939
 940 /* emif2 */
 941 static struct omap_hwmod omap44xx_emif2_hwmod = {
 942         .name           = "emif2",
 943         .class          = &omap44xx_emif_hwmod_class,
 944         .clkdm_name     = "l3_emif_clkdm",
 945         .flags          = HWMOD_INIT_NO_IDLE,
 946         .main_clk       = "ddrphy_ck",
 947         .prcm = {
 948                 .omap4 = {
 949                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 950                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 951                         .modulemode   = MODULEMODE_HWCTRL,
 952                 },
 953         },
 954 };
 955
 956 /*
 957  * 'fdif' class
 958  * face detection hw accelerator module
 959  */
 960
 961 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
 962         .rev_offs       = 0x0000,
 963         .sysc_offs      = 0x0010,
 964         /*
 965          * FDIF needs 100 OCP clk cycles delay after a softreset before
 966          * accessing sysconfig again.
 967          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 968          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 969          *
 970          * TODO: Indicate errata when available.
 971          */
 972         .srst_udelay    = 2,
 973         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 974                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 975         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 976                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 977         .sysc_fields    = &omap_hwmod_sysc_type2,
 978 };
 979
 980 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
 981         .name   = "fdif",
 982         .sysc   = &omap44xx_fdif_sysc,
 983 };
 984
 985 /* fdif */
 986 static struct omap_hwmod omap44xx_fdif_hwmod = {
 987         .name           = "fdif",
 988         .class          = &omap44xx_fdif_hwmod_class,
 989         .clkdm_name     = "iss_clkdm",
 990         .main_clk       = "fdif_fck",
 991         .prcm = {
 992                 .omap4 = {
 993                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
 994                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
 995                         .modulemode   = MODULEMODE_SWCTRL,
 996                 },
 997         },
 998 };
 999
1000 /*
1001  * 'gpio' class
1002  * general purpose io module
1003  */
1004
1005 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1006         .rev_offs       = 0x0000,
1007         .sysc_offs      = 0x0010,
1008         .syss_offs      = 0x0114,
1009         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1010                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1011                            SYSS_HAS_RESET_STATUS),
1012         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1013                            SIDLE_SMART_WKUP),
1014         .sysc_fields    = &omap_hwmod_sysc_type1,
1015 };
1016
1017 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1018         .name   = "gpio",
1019         .sysc   = &omap44xx_gpio_sysc,
1020         .rev    = 2,
1021 };
1022
1023 /* gpio dev_attr */
1024 static struct omap_gpio_dev_attr gpio_dev_attr = {
1025         .bank_width     = 32,
1026         .dbck_flag      = true,
1027 };
1028
1029 /* gpio1 */
1030 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1031         { .role = "dbclk", .clk = "gpio1_dbclk" },
1032 };
1033
1034 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1035         .name           = "gpio1",
1036         .class          = &omap44xx_gpio_hwmod_class,
1037         .clkdm_name     = "l4_wkup_clkdm",
1038         .main_clk       = "l4_wkup_clk_mux_ck",
1039         .prcm = {
1040                 .omap4 = {
1041                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1042                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1043                         .modulemode   = MODULEMODE_HWCTRL,
1044                 },
1045         },
1046         .opt_clks       = gpio1_opt_clks,
1047         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1048         .dev_attr       = &gpio_dev_attr,
1049 };
1050
1051 /* gpio2 */
1052 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1053         { .role = "dbclk", .clk = "gpio2_dbclk" },
1054 };
1055
1056 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1057         .name           = "gpio2",
1058         .class          = &omap44xx_gpio_hwmod_class,
1059         .clkdm_name     = "l4_per_clkdm",
1060         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1061         .main_clk       = "l4_div_ck",
1062         .prcm = {
1063                 .omap4 = {
1064                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1065                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1066                         .modulemode   = MODULEMODE_HWCTRL,
1067                 },
1068         },
1069         .opt_clks       = gpio2_opt_clks,
1070         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1071         .dev_attr       = &gpio_dev_attr,
1072 };
1073
1074 /* gpio3 */
1075 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1076         { .role = "dbclk", .clk = "gpio3_dbclk" },
1077 };
1078
1079 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1080         .name           = "gpio3",
1081         .class          = &omap44xx_gpio_hwmod_class,
1082         .clkdm_name     = "l4_per_clkdm",
1083         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1084         .main_clk       = "l4_div_ck",
1085         .prcm = {
1086                 .omap4 = {
1087                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1088                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1089                         .modulemode   = MODULEMODE_HWCTRL,
1090                 },
1091         },
1092         .opt_clks       = gpio3_opt_clks,
1093         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1094         .dev_attr       = &gpio_dev_attr,
1095 };
1096
1097 /* gpio4 */
1098 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1099         { .role = "dbclk", .clk = "gpio4_dbclk" },
1100 };
1101
1102 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1103         .name           = "gpio4",
1104         .class          = &omap44xx_gpio_hwmod_class,
1105         .clkdm_name     = "l4_per_clkdm",
1106         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1107         .main_clk       = "l4_div_ck",
1108         .prcm = {
1109                 .omap4 = {
1110                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1111                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1112                         .modulemode   = MODULEMODE_HWCTRL,
1113                 },
1114         },
1115         .opt_clks       = gpio4_opt_clks,
1116         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1117         .dev_attr       = &gpio_dev_attr,
1118 };
1119
1120 /* gpio5 */
1121 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1122         { .role = "dbclk", .clk = "gpio5_dbclk" },
1123 };
1124
1125 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1126         .name           = "gpio5",
1127         .class          = &omap44xx_gpio_hwmod_class,
1128         .clkdm_name     = "l4_per_clkdm",
1129         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1130         .main_clk       = "l4_div_ck",
1131         .prcm = {
1132                 .omap4 = {
1133                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1134                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1135                         .modulemode   = MODULEMODE_HWCTRL,
1136                 },
1137         },
1138         .opt_clks       = gpio5_opt_clks,
1139         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1140         .dev_attr       = &gpio_dev_attr,
1141 };
1142
1143 /* gpio6 */
1144 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1145         { .role = "dbclk", .clk = "gpio6_dbclk" },
1146 };
1147
1148 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1149         .name           = "gpio6",
1150         .class          = &omap44xx_gpio_hwmod_class,
1151         .clkdm_name     = "l4_per_clkdm",
1152         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1153         .main_clk       = "l4_div_ck",
1154         .prcm = {
1155                 .omap4 = {
1156                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1157                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1158                         .modulemode   = MODULEMODE_HWCTRL,
1159                 },
1160         },
1161         .opt_clks       = gpio6_opt_clks,
1162         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1163         .dev_attr       = &gpio_dev_attr,
1164 };
1165
1166 /*
1167  * 'gpmc' class
1168  * general purpose memory controller
1169  */
1170
1171 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1172         .rev_offs       = 0x0000,
1173         .sysc_offs      = 0x0010,
1174         .syss_offs      = 0x0014,
1175         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1176                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1177         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1178         .sysc_fields    = &omap_hwmod_sysc_type1,
1179 };
1180
1181 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1182         .name   = "gpmc",
1183         .sysc   = &omap44xx_gpmc_sysc,
1184 };
1185
1186 /* gpmc */
1187 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1188         .name           = "gpmc",
1189         .class          = &omap44xx_gpmc_hwmod_class,
1190         .clkdm_name     = "l3_2_clkdm",
1191         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1192         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1193         .prcm = {
1194                 .omap4 = {
1195                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1196                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1197                         .modulemode   = MODULEMODE_HWCTRL,
1198                 },
1199         },
1200 };
1201
1202 /*
1203  * 'gpu' class
1204  * 2d/3d graphics accelerator
1205  */
1206
1207 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1208         .rev_offs       = 0x1fc00,
1209         .sysc_offs      = 0x1fc10,
1210         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1211         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1212                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1213                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1214         .sysc_fields    = &omap_hwmod_sysc_type2,
1215 };
1216
1217 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1218         .name   = "gpu",
1219         .sysc   = &omap44xx_gpu_sysc,
1220 };
1221
1222 /* gpu */
1223 static struct omap_hwmod omap44xx_gpu_hwmod = {
1224         .name           = "gpu",
1225         .class          = &omap44xx_gpu_hwmod_class,
1226         .clkdm_name     = "l3_gfx_clkdm",
1227         .main_clk       = "sgx_clk_mux",
1228         .prcm = {
1229                 .omap4 = {
1230                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1231                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1232                         .modulemode   = MODULEMODE_SWCTRL,
1233                 },
1234         },
1235 };
1236
1237 /*
1238  * 'hdq1w' class
1239  * hdq / 1-wire serial interface controller
1240  */
1241
1242 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1243         .rev_offs       = 0x0000,
1244         .sysc_offs      = 0x0014,
1245         .syss_offs      = 0x0018,
1246         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1247                            SYSS_HAS_RESET_STATUS),
1248         .sysc_fields    = &omap_hwmod_sysc_type1,
1249 };
1250
1251 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1252         .name   = "hdq1w",
1253         .sysc   = &omap44xx_hdq1w_sysc,
1254 };
1255
1256 /* hdq1w */
1257 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1258         .name           = "hdq1w",
1259         .class          = &omap44xx_hdq1w_hwmod_class,
1260         .clkdm_name     = "l4_per_clkdm",
1261         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1262         .main_clk       = "func_12m_fclk",
1263         .prcm = {
1264                 .omap4 = {
1265                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1266                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1267                         .modulemode   = MODULEMODE_SWCTRL,
1268                 },
1269         },
1270 };
1271
1272 /*
1273  * 'hsi' class
1274  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1275  * serial if)
1276  */
1277
1278 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1279         .rev_offs       = 0x0000,
1280         .sysc_offs      = 0x0010,
1281         .syss_offs      = 0x0014,
1282         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1283                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1284                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1285         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1286                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1287                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1288         .sysc_fields    = &omap_hwmod_sysc_type1,
1289 };
1290
1291 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1292         .name   = "hsi",
1293         .sysc   = &omap44xx_hsi_sysc,
1294 };
1295
1296 /* hsi */
1297 static struct omap_hwmod omap44xx_hsi_hwmod = {
1298         .name           = "hsi",
1299         .class          = &omap44xx_hsi_hwmod_class,
1300         .clkdm_name     = "l3_init_clkdm",
1301         .main_clk       = "hsi_fck",
1302         .prcm = {
1303                 .omap4 = {
1304                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1305                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1306                         .modulemode   = MODULEMODE_HWCTRL,
1307                 },
1308         },
1309 };
1310
1311 /*
1312  * 'i2c' class
1313  * multimaster high-speed i2c controller
1314  */
1315
1316 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1317         .sysc_offs      = 0x0010,
1318         .syss_offs      = 0x0090,
1319         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1320                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1321                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1322         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1323                            SIDLE_SMART_WKUP),
1324         .clockact       = CLOCKACT_TEST_ICLK,
1325         .sysc_fields    = &omap_hwmod_sysc_type1,
1326 };
1327
1328 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1329         .name   = "i2c",
1330         .sysc   = &omap44xx_i2c_sysc,
1331         .rev    = OMAP_I2C_IP_VERSION_2,
1332         .reset  = &omap_i2c_reset,
1333 };
1334
1335 static struct omap_i2c_dev_attr i2c_dev_attr = {
1336         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1337 };
1338
1339 /* i2c1 */
1340 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1341         .name           = "i2c1",
1342         .class          = &omap44xx_i2c_hwmod_class,
1343         .clkdm_name     = "l4_per_clkdm",
1344         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1345         .main_clk       = "func_96m_fclk",
1346         .prcm = {
1347                 .omap4 = {
1348                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1349                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1350                         .modulemode   = MODULEMODE_SWCTRL,
1351                 },
1352         },
1353         .dev_attr       = &i2c_dev_attr,
1354 };
1355
1356 /* i2c2 */
1357 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1358         .name           = "i2c2",
1359         .class          = &omap44xx_i2c_hwmod_class,
1360         .clkdm_name     = "l4_per_clkdm",
1361         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1362         .main_clk       = "func_96m_fclk",
1363         .prcm = {
1364                 .omap4 = {
1365                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1366                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1367                         .modulemode   = MODULEMODE_SWCTRL,
1368                 },
1369         },
1370         .dev_attr       = &i2c_dev_attr,
1371 };
1372
1373 /* i2c3 */
1374 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1375         .name           = "i2c3",
1376         .class          = &omap44xx_i2c_hwmod_class,
1377         .clkdm_name     = "l4_per_clkdm",
1378         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1379         .main_clk       = "func_96m_fclk",
1380         .prcm = {
1381                 .omap4 = {
1382                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1383                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1384                         .modulemode   = MODULEMODE_SWCTRL,
1385                 },
1386         },
1387         .dev_attr       = &i2c_dev_attr,
1388 };
1389
1390 /* i2c4 */
1391 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1392         .name           = "i2c4",
1393         .class          = &omap44xx_i2c_hwmod_class,
1394         .clkdm_name     = "l4_per_clkdm",
1395         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1396         .main_clk       = "func_96m_fclk",
1397         .prcm = {
1398                 .omap4 = {
1399                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1400                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1401                         .modulemode   = MODULEMODE_SWCTRL,
1402                 },
1403         },
1404         .dev_attr       = &i2c_dev_attr,
1405 };
1406
1407 /*
1408  * 'ipu' class
1409  * imaging processor unit
1410  */
1411
1412 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1413         .name   = "ipu",
1414 };
1415
1416 /* ipu */
1417 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1418         { .name = "cpu0", .rst_shift = 0 },
1419         { .name = "cpu1", .rst_shift = 1 },
1420 };
1421
1422 static struct omap_hwmod omap44xx_ipu_hwmod = {
1423         .name           = "ipu",
1424         .class          = &omap44xx_ipu_hwmod_class,
1425         .clkdm_name     = "ducati_clkdm",
1426         .rst_lines      = omap44xx_ipu_resets,
1427         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1428         .main_clk       = "ducati_clk_mux_ck",
1429         .prcm = {
1430                 .omap4 = {
1431                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1432                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1433                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1434                         .modulemode   = MODULEMODE_HWCTRL,
1435                 },
1436         },
1437 };
1438
1439 /*
1440  * 'iss' class
1441  * external images sensor pixel data processor
1442  */
1443
1444 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1445         .rev_offs       = 0x0000,
1446         .sysc_offs      = 0x0010,
1447         /*
1448          * ISS needs 100 OCP clk cycles delay after a softreset before
1449          * accessing sysconfig again.
1450          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1451          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1452          *
1453          * TODO: Indicate errata when available.
1454          */
1455         .srst_udelay    = 2,
1456         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1457                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1458         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1459                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1460                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1461         .sysc_fields    = &omap_hwmod_sysc_type2,
1462 };
1463
1464 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1465         .name   = "iss",
1466         .sysc   = &omap44xx_iss_sysc,
1467 };
1468
1469 /* iss */
1470 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1471         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1472 };
1473
1474 static struct omap_hwmod omap44xx_iss_hwmod = {
1475         .name           = "iss",
1476         .class          = &omap44xx_iss_hwmod_class,
1477         .clkdm_name     = "iss_clkdm",
1478         .main_clk       = "ducati_clk_mux_ck",
1479         .prcm = {
1480                 .omap4 = {
1481                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1482                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1483                         .modulemode   = MODULEMODE_SWCTRL,
1484                 },
1485         },
1486         .opt_clks       = iss_opt_clks,
1487         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1488 };
1489
1490 /*
1491  * 'iva' class
1492  * multi-standard video encoder/decoder hardware accelerator
1493  */
1494
1495 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1496         .name   = "iva",
1497 };
1498
1499 /* iva */
1500 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1501         { .name = "seq0", .rst_shift = 0 },
1502         { .name = "seq1", .rst_shift = 1 },
1503         { .name = "logic", .rst_shift = 2 },
1504 };
1505
1506 static struct omap_hwmod omap44xx_iva_hwmod = {
1507         .name           = "iva",
1508         .class          = &omap44xx_iva_hwmod_class,
1509         .clkdm_name     = "ivahd_clkdm",
1510         .rst_lines      = omap44xx_iva_resets,
1511         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1512         .main_clk       = "dpll_iva_m5x2_ck",
1513         .prcm = {
1514                 .omap4 = {
1515                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1516                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1517                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1518                         .modulemode   = MODULEMODE_HWCTRL,
1519                 },
1520         },
1521 };
1522
1523 /*
1524  * 'kbd' class
1525  * keyboard controller
1526  */
1527
1528 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1529         .rev_offs       = 0x0000,
1530         .sysc_offs      = 0x0010,
1531         .syss_offs      = 0x0014,
1532         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1533                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1534                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1535                            SYSS_HAS_RESET_STATUS),
1536         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1537         .sysc_fields    = &omap_hwmod_sysc_type1,
1538 };
1539
1540 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1541         .name   = "kbd",
1542         .sysc   = &omap44xx_kbd_sysc,
1543 };
1544
1545 /* kbd */
1546 static struct omap_hwmod omap44xx_kbd_hwmod = {
1547         .name           = "kbd",
1548         .class          = &omap44xx_kbd_hwmod_class,
1549         .clkdm_name     = "l4_wkup_clkdm",
1550         .main_clk       = "sys_32k_ck",
1551         .prcm = {
1552                 .omap4 = {
1553                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1554                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1555                         .modulemode   = MODULEMODE_SWCTRL,
1556                 },
1557         },
1558 };
1559
1560 /*
1561  * 'mailbox' class
1562  * mailbox module allowing communication between the on-chip processors using a
1563  * queued mailbox-interrupt mechanism.
1564  */
1565
1566 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1567         .rev_offs       = 0x0000,
1568         .sysc_offs      = 0x0010,
1569         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1570                            SYSC_HAS_SOFTRESET),
1571         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1572         .sysc_fields    = &omap_hwmod_sysc_type2,
1573 };
1574
1575 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1576         .name   = "mailbox",
1577         .sysc   = &omap44xx_mailbox_sysc,
1578 };
1579
1580 /* mailbox */
1581 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1582         .name           = "mailbox",
1583         .class          = &omap44xx_mailbox_hwmod_class,
1584         .clkdm_name     = "l4_cfg_clkdm",
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1588                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1589                 },
1590         },
1591 };
1592
1593 /*
1594  * 'mcasp' class
1595  * multi-channel audio serial port controller
1596  */
1597
1598 /* The IP is not compliant to type1 / type2 scheme */
1599 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1600         .sidle_shift    = 0,
1601 };
1602
1603 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1604         .sysc_offs      = 0x0004,
1605         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1606         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1607                            SIDLE_SMART_WKUP),
1608         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1609 };
1610
1611 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1612         .name   = "mcasp",
1613         .sysc   = &omap44xx_mcasp_sysc,
1614 };
1615
1616 /* mcasp */
1617 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1618         .name           = "mcasp",
1619         .class          = &omap44xx_mcasp_hwmod_class,
1620         .clkdm_name     = "abe_clkdm",
1621         .main_clk       = "func_mcasp_abe_gfclk",
1622         .prcm = {
1623                 .omap4 = {
1624                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1625                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1626                         .modulemode   = MODULEMODE_SWCTRL,
1627                 },
1628         },
1629 };
1630
1631 /*
1632  * 'mcbsp' class
1633  * multi channel buffered serial port controller
1634  */
1635
1636 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1637         .sysc_offs      = 0x008c,
1638         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1639                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1640         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1641         .sysc_fields    = &omap_hwmod_sysc_type1,
1642 };
1643
1644 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1645         .name   = "mcbsp",
1646         .sysc   = &omap44xx_mcbsp_sysc,
1647         .rev    = MCBSP_CONFIG_TYPE4,
1648 };
1649
1650 /* mcbsp1 */
1651 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1652         { .role = "pad_fck", .clk = "pad_clks_ck" },
1653         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1654 };
1655
1656 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1657         .name           = "mcbsp1",
1658         .class          = &omap44xx_mcbsp_hwmod_class,
1659         .clkdm_name     = "abe_clkdm",
1660         .main_clk       = "func_mcbsp1_gfclk",
1661         .prcm = {
1662                 .omap4 = {
1663                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1664                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1665                         .modulemode   = MODULEMODE_SWCTRL,
1666                 },
1667         },
1668         .opt_clks       = mcbsp1_opt_clks,
1669         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1670 };
1671
1672 /* mcbsp2 */
1673 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1674         { .role = "pad_fck", .clk = "pad_clks_ck" },
1675         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1676 };
1677
1678 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1679         .name           = "mcbsp2",
1680         .class          = &omap44xx_mcbsp_hwmod_class,
1681         .clkdm_name     = "abe_clkdm",
1682         .main_clk       = "func_mcbsp2_gfclk",
1683         .prcm = {
1684                 .omap4 = {
1685                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1686                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1687                         .modulemode   = MODULEMODE_SWCTRL,
1688                 },
1689         },
1690         .opt_clks       = mcbsp2_opt_clks,
1691         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1692 };
1693
1694 /* mcbsp3 */
1695 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1696         { .role = "pad_fck", .clk = "pad_clks_ck" },
1697         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1698 };
1699
1700 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1701         .name           = "mcbsp3",
1702         .class          = &omap44xx_mcbsp_hwmod_class,
1703         .clkdm_name     = "abe_clkdm",
1704         .main_clk       = "func_mcbsp3_gfclk",
1705         .prcm = {
1706                 .omap4 = {
1707                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1708                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1709                         .modulemode   = MODULEMODE_SWCTRL,
1710                 },
1711         },
1712         .opt_clks       = mcbsp3_opt_clks,
1713         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1714 };
1715
1716 /* mcbsp4 */
1717 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1718         { .role = "pad_fck", .clk = "pad_clks_ck" },
1719         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1720 };
1721
1722 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1723         .name           = "mcbsp4",
1724         .class          = &omap44xx_mcbsp_hwmod_class,
1725         .clkdm_name     = "l4_per_clkdm",
1726         .main_clk       = "per_mcbsp4_gfclk",
1727         .prcm = {
1728                 .omap4 = {
1729                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1730                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1731                         .modulemode   = MODULEMODE_SWCTRL,
1732                 },
1733         },
1734         .opt_clks       = mcbsp4_opt_clks,
1735         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
1736 };
1737
1738 /*
1739  * 'mcpdm' class
1740  * multi channel pdm controller (proprietary interface with phoenix power
1741  * ic)
1742  */
1743
1744 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1745         .rev_offs       = 0x0000,
1746         .sysc_offs      = 0x0010,
1747         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1748                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1749         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1750                            SIDLE_SMART_WKUP),
1751         .sysc_fields    = &omap_hwmod_sysc_type2,
1752 };
1753
1754 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1755         .name   = "mcpdm",
1756         .sysc   = &omap44xx_mcpdm_sysc,
1757 };
1758
1759 /* mcpdm */
1760 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1761         .name           = "mcpdm",
1762         .class          = &omap44xx_mcpdm_hwmod_class,
1763         .clkdm_name     = "abe_clkdm",
1764         /*
1765          * It's suspected that the McPDM requires an off-chip main
1766          * functional clock, controlled via I2C.  This IP block is
1767          * currently reset very early during boot, before I2C is
1768          * available, so it doesn't seem that we have any choice in
1769          * the kernel other than to avoid resetting it.
1770          *
1771          * Also, McPDM needs to be configured to NO_IDLE mode when it
1772          * is in used otherwise vital clocks will be gated which
1773          * results 'slow motion' audio playback.
1774          */
1775         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1776         .main_clk       = "pad_clks_ck",
1777         .prcm = {
1778                 .omap4 = {
1779                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1780                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1781                         .modulemode   = MODULEMODE_SWCTRL,
1782                 },
1783         },
1784 };
1785
1786 /*
1787  * 'mcspi' class
1788  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1789  * bus
1790  */
1791
1792 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1793         .rev_offs       = 0x0000,
1794         .sysc_offs      = 0x0010,
1795         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1796                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1797         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1798                            SIDLE_SMART_WKUP),
1799         .sysc_fields    = &omap_hwmod_sysc_type2,
1800 };
1801
1802 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1803         .name   = "mcspi",
1804         .sysc   = &omap44xx_mcspi_sysc,
1805         .rev    = OMAP4_MCSPI_REV,
1806 };
1807
1808 /* mcspi1 */
1809 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1810         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1811         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1812         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1813         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1814         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1815         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1816         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1817         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1818         { .dma_req = -1 }
1819 };
1820
1821 /* mcspi1 dev_attr */
1822 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1823         .num_chipselect = 4,
1824 };
1825
1826 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1827         .name           = "mcspi1",
1828         .class          = &omap44xx_mcspi_hwmod_class,
1829         .clkdm_name     = "l4_per_clkdm",
1830         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
1831         .main_clk       = "func_48m_fclk",
1832         .prcm = {
1833                 .omap4 = {
1834                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1835                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1836                         .modulemode   = MODULEMODE_SWCTRL,
1837                 },
1838         },
1839         .dev_attr       = &mcspi1_dev_attr,
1840 };
1841
1842 /* mcspi2 */
1843 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1844         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1845         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1846         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1847         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1848         { .dma_req = -1 }
1849 };
1850
1851 /* mcspi2 dev_attr */
1852 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1853         .num_chipselect = 2,
1854 };
1855
1856 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1857         .name           = "mcspi2",
1858         .class          = &omap44xx_mcspi_hwmod_class,
1859         .clkdm_name     = "l4_per_clkdm",
1860         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
1861         .main_clk       = "func_48m_fclk",
1862         .prcm = {
1863                 .omap4 = {
1864                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1865                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1866                         .modulemode   = MODULEMODE_SWCTRL,
1867                 },
1868         },
1869         .dev_attr       = &mcspi2_dev_attr,
1870 };
1871
1872 /* mcspi3 */
1873 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1874         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1875         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1876         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1877         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1878         { .dma_req = -1 }
1879 };
1880
1881 /* mcspi3 dev_attr */
1882 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1883         .num_chipselect = 2,
1884 };
1885
1886 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1887         .name           = "mcspi3",
1888         .class          = &omap44xx_mcspi_hwmod_class,
1889         .clkdm_name     = "l4_per_clkdm",
1890         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
1891         .main_clk       = "func_48m_fclk",
1892         .prcm = {
1893                 .omap4 = {
1894                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1895                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1896                         .modulemode   = MODULEMODE_SWCTRL,
1897                 },
1898         },
1899         .dev_attr       = &mcspi3_dev_attr,
1900 };
1901
1902 /* mcspi4 */
1903 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1904         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1905         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1906         { .dma_req = -1 }
1907 };
1908
1909 /* mcspi4 dev_attr */
1910 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1911         .num_chipselect = 1,
1912 };
1913
1914 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1915         .name           = "mcspi4",
1916         .class          = &omap44xx_mcspi_hwmod_class,
1917         .clkdm_name     = "l4_per_clkdm",
1918         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
1919         .main_clk       = "func_48m_fclk",
1920         .prcm = {
1921                 .omap4 = {
1922                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1923                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1924                         .modulemode   = MODULEMODE_SWCTRL,
1925                 },
1926         },
1927         .dev_attr       = &mcspi4_dev_attr,
1928 };
1929
1930 /*
1931  * 'mmc' class
1932  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1933  */
1934
1935 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1936         .rev_offs       = 0x0000,
1937         .sysc_offs      = 0x0010,
1938         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1939                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1940                            SYSC_HAS_SOFTRESET),
1941         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1942                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1943                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1944         .sysc_fields    = &omap_hwmod_sysc_type2,
1945 };
1946
1947 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1948         .name   = "mmc",
1949         .sysc   = &omap44xx_mmc_sysc,
1950 };
1951
1952 /* mmc1 */
1953 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1954         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1955         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1956         { .dma_req = -1 }
1957 };
1958
1959 /* mmc1 dev_attr */
1960 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1961         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1962 };
1963
1964 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1965         .name           = "mmc1",
1966         .class          = &omap44xx_mmc_hwmod_class,
1967         .clkdm_name     = "l3_init_clkdm",
1968         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
1969         .main_clk       = "hsmmc1_fclk",
1970         .prcm = {
1971                 .omap4 = {
1972                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1973                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1974                         .modulemode   = MODULEMODE_SWCTRL,
1975                 },
1976         },
1977         .dev_attr       = &mmc1_dev_attr,
1978 };
1979
1980 /* mmc2 */
1981 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1982         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1983         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1984         { .dma_req = -1 }
1985 };
1986
1987 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1988         .name           = "mmc2",
1989         .class          = &omap44xx_mmc_hwmod_class,
1990         .clkdm_name     = "l3_init_clkdm",
1991         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
1992         .main_clk       = "hsmmc2_fclk",
1993         .prcm = {
1994                 .omap4 = {
1995                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1996                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1997                         .modulemode   = MODULEMODE_SWCTRL,
1998                 },
1999         },
2000 };
2001
2002 /* mmc3 */
2003 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2004         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2005         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2006         { .dma_req = -1 }
2007 };
2008
2009 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2010         .name           = "mmc3",
2011         .class          = &omap44xx_mmc_hwmod_class,
2012         .clkdm_name     = "l4_per_clkdm",
2013         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2014         .main_clk       = "func_48m_fclk",
2015         .prcm = {
2016                 .omap4 = {
2017                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2018                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2019                         .modulemode   = MODULEMODE_SWCTRL,
2020                 },
2021         },
2022 };
2023
2024 /* mmc4 */
2025 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2026         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2027         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2028         { .dma_req = -1 }
2029 };
2030
2031 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2032         .name           = "mmc4",
2033         .class          = &omap44xx_mmc_hwmod_class,
2034         .clkdm_name     = "l4_per_clkdm",
2035         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2036         .main_clk       = "func_48m_fclk",
2037         .prcm = {
2038                 .omap4 = {
2039                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2040                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2041                         .modulemode   = MODULEMODE_SWCTRL,
2042                 },
2043         },
2044 };
2045
2046 /* mmc5 */
2047 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2048         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2049         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2050         { .dma_req = -1 }
2051 };
2052
2053 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2054         .name           = "mmc5",
2055         .class          = &omap44xx_mmc_hwmod_class,
2056         .clkdm_name     = "l4_per_clkdm",
2057         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2058         .main_clk       = "func_48m_fclk",
2059         .prcm = {
2060                 .omap4 = {
2061                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2062                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2063                         .modulemode   = MODULEMODE_SWCTRL,
2064                 },
2065         },
2066 };
2067
2068 /*
2069  * 'mmu' class
2070  * The memory management unit performs virtual to physical address translation
2071  * for its requestors.
2072  */
2073
2074 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2075         .rev_offs       = 0x000,
2076         .sysc_offs      = 0x010,
2077         .syss_offs      = 0x014,
2078         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2079                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2080         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2081         .sysc_fields    = &omap_hwmod_sysc_type1,
2082 };
2083
2084 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2085         .name = "mmu",
2086         .sysc = &mmu_sysc,
2087 };
2088
2089 /* mmu ipu */
2090
2091 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2092         .nr_tlb_entries = 32,
2093 };
2094
2095 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2096 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2097         { .name = "mmu_cache", .rst_shift = 2 },
2098 };
2099
2100 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2101         {
2102                 .pa_start       = 0x55082000,
2103                 .pa_end         = 0x550820ff,
2104                 .flags          = ADDR_TYPE_RT,
2105         },
2106         { }
2107 };
2108
2109 /* l3_main_2 -> mmu_ipu */
2110 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2111         .master         = &omap44xx_l3_main_2_hwmod,
2112         .slave          = &omap44xx_mmu_ipu_hwmod,
2113         .clk            = "l3_div_ck",
2114         .addr           = omap44xx_mmu_ipu_addrs,
2115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2116 };
2117
2118 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2119         .name           = "mmu_ipu",
2120         .class          = &omap44xx_mmu_hwmod_class,
2121         .clkdm_name     = "ducati_clkdm",
2122         .rst_lines      = omap44xx_mmu_ipu_resets,
2123         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2124         .main_clk       = "ducati_clk_mux_ck",
2125         .prcm = {
2126                 .omap4 = {
2127                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2128                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2129                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2130                         .modulemode   = MODULEMODE_HWCTRL,
2131                 },
2132         },
2133         .dev_attr       = &mmu_ipu_dev_attr,
2134 };
2135
2136 /* mmu dsp */
2137
2138 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2139         .nr_tlb_entries = 32,
2140 };
2141
2142 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2143 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2144         { .name = "mmu_cache", .rst_shift = 1 },
2145 };
2146
2147 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2148         {
2149                 .pa_start       = 0x4a066000,
2150                 .pa_end         = 0x4a0660ff,
2151                 .flags          = ADDR_TYPE_RT,
2152         },
2153         { }
2154 };
2155
2156 /* l4_cfg -> dsp */
2157 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2158         .master         = &omap44xx_l4_cfg_hwmod,
2159         .slave          = &omap44xx_mmu_dsp_hwmod,
2160         .clk            = "l4_div_ck",
2161         .addr           = omap44xx_mmu_dsp_addrs,
2162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2163 };
2164
2165 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2166         .name           = "mmu_dsp",
2167         .class          = &omap44xx_mmu_hwmod_class,
2168         .clkdm_name     = "tesla_clkdm",
2169         .rst_lines      = omap44xx_mmu_dsp_resets,
2170         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2171         .main_clk       = "dpll_iva_m4x2_ck",
2172         .prcm = {
2173                 .omap4 = {
2174                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2175                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2176                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2177                         .modulemode   = MODULEMODE_HWCTRL,
2178                 },
2179         },
2180         .dev_attr       = &mmu_dsp_dev_attr,
2181 };
2182
2183 /*
2184  * 'mpu' class
2185  * mpu sub-system
2186  */
2187
2188 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2189         .name   = "mpu",
2190 };
2191
2192 /* mpu */
2193 static struct omap_hwmod omap44xx_mpu_hwmod = {
2194         .name           = "mpu",
2195         .class          = &omap44xx_mpu_hwmod_class,
2196         .clkdm_name     = "mpuss_clkdm",
2197         .flags          = HWMOD_INIT_NO_IDLE,
2198         .main_clk       = "dpll_mpu_m2_ck",
2199         .prcm = {
2200                 .omap4 = {
2201                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2202                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2203                 },
2204         },
2205 };
2206
2207 /*
2208  * 'ocmc_ram' class
2209  * top-level core on-chip ram
2210  */
2211
2212 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2213         .name   = "ocmc_ram",
2214 };
2215
2216 /* ocmc_ram */
2217 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2218         .name           = "ocmc_ram",
2219         .class          = &omap44xx_ocmc_ram_hwmod_class,
2220         .clkdm_name     = "l3_2_clkdm",
2221         .prcm = {
2222                 .omap4 = {
2223                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2224                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2225                 },
2226         },
2227 };
2228
2229 /*
2230  * 'ocp2scp' class
2231  * bridge to transform ocp interface protocol to scp (serial control port)
2232  * protocol
2233  */
2234
2235 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2236         .rev_offs       = 0x0000,
2237         .sysc_offs      = 0x0010,
2238         .syss_offs      = 0x0014,
2239         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2240                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2241         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2242         .sysc_fields    = &omap_hwmod_sysc_type1,
2243 };
2244
2245 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2246         .name   = "ocp2scp",
2247         .sysc   = &omap44xx_ocp2scp_sysc,
2248 };
2249
2250 /* ocp2scp_usb_phy */
2251 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2252         .name           = "ocp2scp_usb_phy",
2253         .class          = &omap44xx_ocp2scp_hwmod_class,
2254         .clkdm_name     = "l3_init_clkdm",
2255         /*
2256          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2257          * block as an "optional clock," and normally should never be
2258          * specified as the main_clk for an OMAP IP block.  However it
2259          * turns out that this clock is actually the main clock for
2260          * the ocp2scp_usb_phy IP block:
2261          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2262          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2263          * to be the best workaround.
2264          */
2265         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2266         .prcm = {
2267                 .omap4 = {
2268                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2269                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2270                         .modulemode   = MODULEMODE_HWCTRL,
2271                 },
2272         },
2273 };
2274
2275 /*
2276  * 'prcm' class
2277  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2278  * + clock manager 1 (in always on power domain) + local prm in mpu
2279  */
2280
2281 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2282         .name   = "prcm",
2283 };
2284
2285 /* prcm_mpu */
2286 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2287         .name           = "prcm_mpu",
2288         .class          = &omap44xx_prcm_hwmod_class,
2289         .clkdm_name     = "l4_wkup_clkdm",
2290         .flags          = HWMOD_NO_IDLEST,
2291         .prcm = {
2292                 .omap4 = {
2293                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2294                 },
2295         },
2296 };
2297
2298 /* cm_core_aon */
2299 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2300         .name           = "cm_core_aon",
2301         .class          = &omap44xx_prcm_hwmod_class,
2302         .flags          = HWMOD_NO_IDLEST,
2303         .prcm = {
2304                 .omap4 = {
2305                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2306                 },
2307         },
2308 };
2309
2310 /* cm_core */
2311 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2312         .name           = "cm_core",
2313         .class          = &omap44xx_prcm_hwmod_class,
2314         .flags          = HWMOD_NO_IDLEST,
2315         .prcm = {
2316                 .omap4 = {
2317                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2318                 },
2319         },
2320 };
2321
2322 /* prm */
2323 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2324         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2325         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2326 };
2327
2328 static struct omap_hwmod omap44xx_prm_hwmod = {
2329         .name           = "prm",
2330         .class          = &omap44xx_prcm_hwmod_class,
2331         .rst_lines      = omap44xx_prm_resets,
2332         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2333 };
2334
2335 /*
2336  * 'scrm' class
2337  * system clock and reset manager
2338  */
2339
2340 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2341         .name   = "scrm",
2342 };
2343
2344 /* scrm */
2345 static struct omap_hwmod omap44xx_scrm_hwmod = {
2346         .name           = "scrm",
2347         .class          = &omap44xx_scrm_hwmod_class,
2348         .clkdm_name     = "l4_wkup_clkdm",
2349         .prcm = {
2350                 .omap4 = {
2351                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2352                 },
2353         },
2354 };
2355
2356 /*
2357  * 'sl2if' class
2358  * shared level 2 memory interface
2359  */
2360
2361 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2362         .name   = "sl2if",
2363 };
2364
2365 /* sl2if */
2366 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2367         .name           = "sl2if",
2368         .class          = &omap44xx_sl2if_hwmod_class,
2369         .clkdm_name     = "ivahd_clkdm",
2370         .prcm = {
2371                 .omap4 = {
2372                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2373                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2374                         .modulemode   = MODULEMODE_HWCTRL,
2375                 },
2376         },
2377 };
2378
2379 /*
2380  * 'slimbus' class
2381  * bidirectional, multi-drop, multi-channel two-line serial interface between
2382  * the device and external components
2383  */
2384
2385 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2386         .rev_offs       = 0x0000,
2387         .sysc_offs      = 0x0010,
2388         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2389                            SYSC_HAS_SOFTRESET),
2390         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2391                            SIDLE_SMART_WKUP),
2392         .sysc_fields    = &omap_hwmod_sysc_type2,
2393 };
2394
2395 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2396         .name   = "slimbus",
2397         .sysc   = &omap44xx_slimbus_sysc,
2398 };
2399
2400 /* slimbus1 */
2401 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2402         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2403         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2404         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2405         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2406 };
2407
2408 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2409         .name           = "slimbus1",
2410         .class          = &omap44xx_slimbus_hwmod_class,
2411         .clkdm_name     = "abe_clkdm",
2412         .prcm = {
2413                 .omap4 = {
2414                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2415                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2416                         .modulemode   = MODULEMODE_SWCTRL,
2417                 },
2418         },
2419         .opt_clks       = slimbus1_opt_clks,
2420         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2421 };
2422
2423 /* slimbus2 */
2424 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2425         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2426         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2427         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2428 };
2429
2430 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2431         .name           = "slimbus2",
2432         .class          = &omap44xx_slimbus_hwmod_class,
2433         .clkdm_name     = "l4_per_clkdm",
2434         .prcm = {
2435                 .omap4 = {
2436                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2437                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2438                         .modulemode   = MODULEMODE_SWCTRL,
2439                 },
2440         },
2441         .opt_clks       = slimbus2_opt_clks,
2442         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2443 };
2444
2445 /*
2446  * 'smartreflex' class
2447  * smartreflex module (monitor silicon performance and outputs a measure of
2448  * performance error)
2449  */
2450
2451 /* The IP is not compliant to type1 / type2 scheme */
2452 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2453         .sidle_shift    = 24,
2454         .enwkup_shift   = 26,
2455 };
2456
2457 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2458         .sysc_offs      = 0x0038,
2459         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2460         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2461                            SIDLE_SMART_WKUP),
2462         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2463 };
2464
2465 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2466         .name   = "smartreflex",
2467         .sysc   = &omap44xx_smartreflex_sysc,
2468         .rev    = 2,
2469 };
2470
2471 /* smartreflex_core */
2472 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2473         .sensor_voltdm_name   = "core",
2474 };
2475
2476 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2477         .name           = "smartreflex_core",
2478         .class          = &omap44xx_smartreflex_hwmod_class,
2479         .clkdm_name     = "l4_ao_clkdm",
2480
2481         .main_clk       = "smartreflex_core_fck",
2482         .prcm = {
2483                 .omap4 = {
2484                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2485                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2486                         .modulemode   = MODULEMODE_SWCTRL,
2487                 },
2488         },
2489         .dev_attr       = &smartreflex_core_dev_attr,
2490 };
2491
2492 /* smartreflex_iva */
2493 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2494         .sensor_voltdm_name     = "iva",
2495 };
2496
2497 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2498         .name           = "smartreflex_iva",
2499         .class          = &omap44xx_smartreflex_hwmod_class,
2500         .clkdm_name     = "l4_ao_clkdm",
2501         .main_clk       = "smartreflex_iva_fck",
2502         .prcm = {
2503                 .omap4 = {
2504                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2505                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2506                         .modulemode   = MODULEMODE_SWCTRL,
2507                 },
2508         },
2509         .dev_attr       = &smartreflex_iva_dev_attr,
2510 };
2511
2512 /* smartreflex_mpu */
2513 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2514         .sensor_voltdm_name     = "mpu",
2515 };
2516
2517 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2518         .name           = "smartreflex_mpu",
2519         .class          = &omap44xx_smartreflex_hwmod_class,
2520         .clkdm_name     = "l4_ao_clkdm",
2521         .main_clk       = "smartreflex_mpu_fck",
2522         .prcm = {
2523                 .omap4 = {
2524                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2525                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2526                         .modulemode   = MODULEMODE_SWCTRL,
2527                 },
2528         },
2529         .dev_attr       = &smartreflex_mpu_dev_attr,
2530 };
2531
2532 /*
2533  * 'spinlock' class
2534  * spinlock provides hardware assistance for synchronizing the processes
2535  * running on multiple processors
2536  */
2537
2538 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2539         .rev_offs       = 0x0000,
2540         .sysc_offs      = 0x0010,
2541         .syss_offs      = 0x0014,
2542         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2543                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2544                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2545         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2546         .sysc_fields    = &omap_hwmod_sysc_type1,
2547 };
2548
2549 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2550         .name   = "spinlock",
2551         .sysc   = &omap44xx_spinlock_sysc,
2552 };
2553
2554 /* spinlock */
2555 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2556         .name           = "spinlock",
2557         .class          = &omap44xx_spinlock_hwmod_class,
2558         .clkdm_name     = "l4_cfg_clkdm",
2559         .prcm = {
2560                 .omap4 = {
2561                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2562                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2563                 },
2564         },
2565 };
2566
2567 /*
2568  * 'timer' class
2569  * general purpose timer module with accurate 1ms tick
2570  * This class contains several variants: ['timer_1ms', 'timer']
2571  */
2572
2573 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2574         .rev_offs       = 0x0000,
2575         .sysc_offs      = 0x0010,
2576         .syss_offs      = 0x0014,
2577         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2578                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2579                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2580                            SYSS_HAS_RESET_STATUS),
2581         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2582         .clockact       = CLOCKACT_TEST_ICLK,
2583         .sysc_fields    = &omap_hwmod_sysc_type1,
2584 };
2585
2586 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2587         .name   = "timer",
2588         .sysc   = &omap44xx_timer_1ms_sysc,
2589 };
2590
2591 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2592         .rev_offs       = 0x0000,
2593         .sysc_offs      = 0x0010,
2594         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2595                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2596         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2597                            SIDLE_SMART_WKUP),
2598         .sysc_fields    = &omap_hwmod_sysc_type2,
2599 };
2600
2601 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2602         .name   = "timer",
2603         .sysc   = &omap44xx_timer_sysc,
2604 };
2605
2606 /* always-on timers dev attribute */
2607 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2608         .timer_capability       = OMAP_TIMER_ALWON,
2609 };
2610
2611 /* pwm timers dev attribute */
2612 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2613         .timer_capability       = OMAP_TIMER_HAS_PWM,
2614 };
2615
2616 /* timers with DSP interrupt dev attribute */
2617 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2618         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
2619 };
2620
2621 /* pwm timers with DSP interrupt dev attribute */
2622 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2623         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2624 };
2625
2626 /* timer1 */
2627 static struct omap_hwmod omap44xx_timer1_hwmod = {
2628         .name           = "timer1",
2629         .class          = &omap44xx_timer_1ms_hwmod_class,
2630         .clkdm_name     = "l4_wkup_clkdm",
2631         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2632         .main_clk       = "dmt1_clk_mux",
2633         .prcm = {
2634                 .omap4 = {
2635                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2636                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2637                         .modulemode   = MODULEMODE_SWCTRL,
2638                 },
2639         },
2640         .dev_attr       = &capability_alwon_dev_attr,
2641 };
2642
2643 /* timer2 */
2644 static struct omap_hwmod omap44xx_timer2_hwmod = {
2645         .name           = "timer2",
2646         .class          = &omap44xx_timer_1ms_hwmod_class,
2647         .clkdm_name     = "l4_per_clkdm",
2648         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2649         .main_clk       = "cm2_dm2_mux",
2650         .prcm = {
2651                 .omap4 = {
2652                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2653                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2654                         .modulemode   = MODULEMODE_SWCTRL,
2655                 },
2656         },
2657 };
2658
2659 /* timer3 */
2660 static struct omap_hwmod omap44xx_timer3_hwmod = {
2661         .name           = "timer3",
2662         .class          = &omap44xx_timer_hwmod_class,
2663         .clkdm_name     = "l4_per_clkdm",
2664         .main_clk       = "cm2_dm3_mux",
2665         .prcm = {
2666                 .omap4 = {
2667                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2668                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2669                         .modulemode   = MODULEMODE_SWCTRL,
2670                 },
2671         },
2672 };
2673
2674 /* timer4 */
2675 static struct omap_hwmod omap44xx_timer4_hwmod = {
2676         .name           = "timer4",
2677         .class          = &omap44xx_timer_hwmod_class,
2678         .clkdm_name     = "l4_per_clkdm",
2679         .main_clk       = "cm2_dm4_mux",
2680         .prcm = {
2681                 .omap4 = {
2682                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2683                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2684                         .modulemode   = MODULEMODE_SWCTRL,
2685                 },
2686         },
2687 };
2688
2689 /* timer5 */
2690 static struct omap_hwmod omap44xx_timer5_hwmod = {
2691         .name           = "timer5",
2692         .class          = &omap44xx_timer_hwmod_class,
2693         .clkdm_name     = "abe_clkdm",
2694         .main_clk       = "timer5_sync_mux",
2695         .prcm = {
2696                 .omap4 = {
2697                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2698                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2699                         .modulemode   = MODULEMODE_SWCTRL,
2700                 },
2701         },
2702         .dev_attr       = &capability_dsp_dev_attr,
2703 };
2704
2705 /* timer6 */
2706 static struct omap_hwmod omap44xx_timer6_hwmod = {
2707         .name           = "timer6",
2708         .class          = &omap44xx_timer_hwmod_class,
2709         .clkdm_name     = "abe_clkdm",
2710         .main_clk       = "timer6_sync_mux",
2711         .prcm = {
2712                 .omap4 = {
2713                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2714                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2715                         .modulemode   = MODULEMODE_SWCTRL,
2716                 },
2717         },
2718         .dev_attr       = &capability_dsp_dev_attr,
2719 };
2720
2721 /* timer7 */
2722 static struct omap_hwmod omap44xx_timer7_hwmod = {
2723         .name           = "timer7",
2724         .class          = &omap44xx_timer_hwmod_class,
2725         .clkdm_name     = "abe_clkdm",
2726         .main_clk       = "timer7_sync_mux",
2727         .prcm = {
2728                 .omap4 = {
2729                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2730                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2731                         .modulemode   = MODULEMODE_SWCTRL,
2732                 },
2733         },
2734         .dev_attr       = &capability_dsp_dev_attr,
2735 };
2736
2737 /* timer8 */
2738 static struct omap_hwmod omap44xx_timer8_hwmod = {
2739         .name           = "timer8",
2740         .class          = &omap44xx_timer_hwmod_class,
2741         .clkdm_name     = "abe_clkdm",
2742         .main_clk       = "timer8_sync_mux",
2743         .prcm = {
2744                 .omap4 = {
2745                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2746                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2747                         .modulemode   = MODULEMODE_SWCTRL,
2748                 },
2749         },
2750         .dev_attr       = &capability_dsp_pwm_dev_attr,
2751 };
2752
2753 /* timer9 */
2754 static struct omap_hwmod omap44xx_timer9_hwmod = {
2755         .name           = "timer9",
2756         .class          = &omap44xx_timer_hwmod_class,
2757         .clkdm_name     = "l4_per_clkdm",
2758         .main_clk       = "cm2_dm9_mux",
2759         .prcm = {
2760                 .omap4 = {
2761                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2762                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2763                         .modulemode   = MODULEMODE_SWCTRL,
2764                 },
2765         },
2766         .dev_attr       = &capability_pwm_dev_attr,
2767 };
2768
2769 /* timer10 */
2770 static struct omap_hwmod omap44xx_timer10_hwmod = {
2771         .name           = "timer10",
2772         .class          = &omap44xx_timer_1ms_hwmod_class,
2773         .clkdm_name     = "l4_per_clkdm",
2774         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2775         .main_clk       = "cm2_dm10_mux",
2776         .prcm = {
2777                 .omap4 = {
2778                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2779                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2780                         .modulemode   = MODULEMODE_SWCTRL,
2781                 },
2782         },
2783         .dev_attr       = &capability_pwm_dev_attr,
2784 };
2785
2786 /* timer11 */
2787 static struct omap_hwmod omap44xx_timer11_hwmod = {
2788         .name           = "timer11",
2789         .class          = &omap44xx_timer_hwmod_class,
2790         .clkdm_name     = "l4_per_clkdm",
2791         .main_clk       = "cm2_dm11_mux",
2792         .prcm = {
2793                 .omap4 = {
2794                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2795                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2796                         .modulemode   = MODULEMODE_SWCTRL,
2797                 },
2798         },
2799         .dev_attr       = &capability_pwm_dev_attr,
2800 };
2801
2802 /*
2803  * 'uart' class
2804  * universal asynchronous receiver/transmitter (uart)
2805  */
2806
2807 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2808         .rev_offs       = 0x0050,
2809         .sysc_offs      = 0x0054,
2810         .syss_offs      = 0x0058,
2811         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2812                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2813                            SYSS_HAS_RESET_STATUS),
2814         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2815                            SIDLE_SMART_WKUP),
2816         .sysc_fields    = &omap_hwmod_sysc_type1,
2817 };
2818
2819 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2820         .name   = "uart",
2821         .sysc   = &omap44xx_uart_sysc,
2822 };
2823
2824 /* uart1 */
2825 static struct omap_hwmod omap44xx_uart1_hwmod = {
2826         .name           = "uart1",
2827         .class          = &omap44xx_uart_hwmod_class,
2828         .clkdm_name     = "l4_per_clkdm",
2829         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2830         .main_clk       = "func_48m_fclk",
2831         .prcm = {
2832                 .omap4 = {
2833                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2834                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2835                         .modulemode   = MODULEMODE_SWCTRL,
2836                 },
2837         },
2838 };
2839
2840 /* uart2 */
2841 static struct omap_hwmod omap44xx_uart2_hwmod = {
2842         .name           = "uart2",
2843         .class          = &omap44xx_uart_hwmod_class,
2844         .clkdm_name     = "l4_per_clkdm",
2845         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2846         .main_clk       = "func_48m_fclk",
2847         .prcm = {
2848                 .omap4 = {
2849                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2850                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2851                         .modulemode   = MODULEMODE_SWCTRL,
2852                 },
2853         },
2854 };
2855
2856 /* uart3 */
2857 static struct omap_hwmod omap44xx_uart3_hwmod = {
2858         .name           = "uart3",
2859         .class          = &omap44xx_uart_hwmod_class,
2860         .clkdm_name     = "l4_per_clkdm",
2861         .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2862         .main_clk       = "func_48m_fclk",
2863         .prcm = {
2864                 .omap4 = {
2865                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2866                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2867                         .modulemode   = MODULEMODE_SWCTRL,
2868                 },
2869         },
2870 };
2871
2872 /* uart4 */
2873 static struct omap_hwmod omap44xx_uart4_hwmod = {
2874         .name           = "uart4",
2875         .class          = &omap44xx_uart_hwmod_class,
2876         .clkdm_name     = "l4_per_clkdm",
2877         .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2878         .main_clk       = "func_48m_fclk",
2879         .prcm = {
2880                 .omap4 = {
2881                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2882                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2883                         .modulemode   = MODULEMODE_SWCTRL,
2884                 },
2885         },
2886 };
2887
2888 /*
2889  * 'usb_host_fs' class
2890  * full-speed usb host controller
2891  */
2892
2893 /* The IP is not compliant to type1 / type2 scheme */
2894 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2895         .midle_shift    = 4,
2896         .sidle_shift    = 2,
2897         .srst_shift     = 1,
2898 };
2899
2900 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2901         .rev_offs       = 0x0000,
2902         .sysc_offs      = 0x0210,
2903         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2904                            SYSC_HAS_SOFTRESET),
2905         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2906                            SIDLE_SMART_WKUP),
2907         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
2908 };
2909
2910 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2911         .name   = "usb_host_fs",
2912         .sysc   = &omap44xx_usb_host_fs_sysc,
2913 };
2914
2915 /* usb_host_fs */
2916 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2917         .name           = "usb_host_fs",
2918         .class          = &omap44xx_usb_host_fs_hwmod_class,
2919         .clkdm_name     = "l3_init_clkdm",
2920         .main_clk       = "usb_host_fs_fck",
2921         .prcm = {
2922                 .omap4 = {
2923                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2924                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2925                         .modulemode   = MODULEMODE_SWCTRL,
2926                 },
2927         },
2928 };
2929
2930 /*
2931  * 'usb_host_hs' class
2932  * high-speed multi-port usb host controller
2933  */
2934
2935 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2936         .rev_offs       = 0x0000,
2937         .sysc_offs      = 0x0010,
2938         .syss_offs      = 0x0014,
2939         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2940                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2941         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2942                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2943                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2944         .sysc_fields    = &omap_hwmod_sysc_type2,
2945 };
2946
2947 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2948         .name   = "usb_host_hs",
2949         .sysc   = &omap44xx_usb_host_hs_sysc,
2950 };
2951
2952 /* usb_host_hs */
2953 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2954         .name           = "usb_host_hs",
2955         .class          = &omap44xx_usb_host_hs_hwmod_class,
2956         .clkdm_name     = "l3_init_clkdm",
2957         .main_clk       = "usb_host_hs_fck",
2958         .prcm = {
2959                 .omap4 = {
2960                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2961                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2962                         .modulemode   = MODULEMODE_SWCTRL,
2963                 },
2964         },
2965
2966         /*
2967          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2968          * id: i660
2969          *
2970          * Description:
2971          * In the following configuration :
2972          * - USBHOST module is set to smart-idle mode
2973          * - PRCM asserts idle_req to the USBHOST module ( This typically
2974          *   happens when the system is going to a low power mode : all ports
2975          *   have been suspended, the master part of the USBHOST module has
2976          *   entered the standby state, and SW has cut the functional clocks)
2977          * - an USBHOST interrupt occurs before the module is able to answer
2978          *   idle_ack, typically a remote wakeup IRQ.
2979          * Then the USB HOST module will enter a deadlock situation where it
2980          * is no more accessible nor functional.
2981          *
2982          * Workaround:
2983          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2984          */
2985
2986         /*
2987          * Errata: USB host EHCI may stall when entering smart-standby mode
2988          * Id: i571
2989          *
2990          * Description:
2991          * When the USBHOST module is set to smart-standby mode, and when it is
2992          * ready to enter the standby state (i.e. all ports are suspended and
2993          * all attached devices are in suspend mode), then it can wrongly assert
2994          * the Mstandby signal too early while there are still some residual OCP
2995          * transactions ongoing. If this condition occurs, the internal state
2996          * machine may go to an undefined state and the USB link may be stuck
2997          * upon the next resume.
2998          *
2999          * Workaround:
3000          * Don't use smart standby; use only force standby,
3001          * hence HWMOD_SWSUP_MSTANDBY
3002          */
3003
3004         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3005 };
3006
3007 /*
3008  * 'usb_otg_hs' class
3009  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3010  */
3011
3012 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3013         .rev_offs       = 0x0400,
3014         .sysc_offs      = 0x0404,
3015         .syss_offs      = 0x0408,
3016         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3017                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3018                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3019         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3020                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3021                            MSTANDBY_SMART),
3022         .sysc_fields    = &omap_hwmod_sysc_type1,
3023 };
3024
3025 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3026         .name   = "usb_otg_hs",
3027         .sysc   = &omap44xx_usb_otg_hs_sysc,
3028 };
3029
3030 /* usb_otg_hs */
3031 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3032         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3033 };
3034
3035 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3036         .name           = "usb_otg_hs",
3037         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3038         .clkdm_name     = "l3_init_clkdm",
3039         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3040         .main_clk       = "usb_otg_hs_ick",
3041         .prcm = {
3042                 .omap4 = {
3043                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3044                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3045                         .modulemode   = MODULEMODE_HWCTRL,
3046                 },
3047         },
3048         .opt_clks       = usb_otg_hs_opt_clks,
3049         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3050 };
3051
3052 /*
3053  * 'usb_tll_hs' class
3054  * usb_tll_hs module is the adapter on the usb_host_hs ports
3055  */
3056
3057 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3058         .rev_offs       = 0x0000,
3059         .sysc_offs      = 0x0010,
3060         .syss_offs      = 0x0014,
3061         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3062                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3063                            SYSC_HAS_AUTOIDLE),
3064         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3065         .sysc_fields    = &omap_hwmod_sysc_type1,
3066 };
3067
3068 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3069         .name   = "usb_tll_hs",
3070         .sysc   = &omap44xx_usb_tll_hs_sysc,
3071 };
3072
3073 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3074         .name           = "usb_tll_hs",
3075         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3076         .clkdm_name     = "l3_init_clkdm",
3077         .main_clk       = "usb_tll_hs_ick",
3078         .prcm = {
3079                 .omap4 = {
3080                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3081                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3082                         .modulemode   = MODULEMODE_HWCTRL,
3083                 },
3084         },
3085 };
3086
3087 /*
3088  * 'wd_timer' class
3089  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3090  * overflow condition
3091  */
3092
3093 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3094         .rev_offs       = 0x0000,
3095         .sysc_offs      = 0x0010,
3096         .syss_offs      = 0x0014,
3097         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3098                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3099         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3100                            SIDLE_SMART_WKUP),
3101         .sysc_fields    = &omap_hwmod_sysc_type1,
3102 };
3103
3104 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3105         .name           = "wd_timer",
3106         .sysc           = &omap44xx_wd_timer_sysc,
3107         .pre_shutdown   = &omap2_wd_timer_disable,
3108         .reset          = &omap2_wd_timer_reset,
3109 };
3110
3111 /* wd_timer2 */
3112 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3113         .name           = "wd_timer2",
3114         .class          = &omap44xx_wd_timer_hwmod_class,
3115         .clkdm_name     = "l4_wkup_clkdm",
3116         .main_clk       = "sys_32k_ck",
3117         .prcm = {
3118                 .omap4 = {
3119                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3120                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3121                         .modulemode   = MODULEMODE_SWCTRL,
3122                 },
3123         },
3124 };
3125
3126 /* wd_timer3 */
3127 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3128         .name           = "wd_timer3",
3129         .class          = &omap44xx_wd_timer_hwmod_class,
3130         .clkdm_name     = "abe_clkdm",
3131         .main_clk       = "sys_32k_ck",
3132         .prcm = {
3133                 .omap4 = {
3134                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3135                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3136                         .modulemode   = MODULEMODE_SWCTRL,
3137                 },
3138         },
3139 };
3140
3141
3142 /*
3143  * interfaces
3144  */
3145
3146 /* l3_main_1 -> dmm */
3147 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3148         .master         = &omap44xx_l3_main_1_hwmod,
3149         .slave          = &omap44xx_dmm_hwmod,
3150         .clk            = "l3_div_ck",
3151         .user           = OCP_USER_SDMA,
3152 };
3153
3154 /* mpu -> dmm */
3155 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3156         .master         = &omap44xx_mpu_hwmod,
3157         .slave          = &omap44xx_dmm_hwmod,
3158         .clk            = "l3_div_ck",
3159         .user           = OCP_USER_MPU,
3160 };
3161
3162 /* iva -> l3_instr */
3163 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3164         .master         = &omap44xx_iva_hwmod,
3165         .slave          = &omap44xx_l3_instr_hwmod,
3166         .clk            = "l3_div_ck",
3167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3168 };
3169
3170 /* l3_main_3 -> l3_instr */
3171 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3172         .master         = &omap44xx_l3_main_3_hwmod,
3173         .slave          = &omap44xx_l3_instr_hwmod,
3174         .clk            = "l3_div_ck",
3175         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3176 };
3177
3178 /* ocp_wp_noc -> l3_instr */
3179 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3180         .master         = &omap44xx_ocp_wp_noc_hwmod,
3181         .slave          = &omap44xx_l3_instr_hwmod,
3182         .clk            = "l3_div_ck",
3183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3184 };
3185
3186 /* dsp -> l3_main_1 */
3187 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3188         .master         = &omap44xx_dsp_hwmod,
3189         .slave          = &omap44xx_l3_main_1_hwmod,
3190         .clk            = "l3_div_ck",
3191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3192 };
3193
3194 /* dss -> l3_main_1 */
3195 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3196         .master         = &omap44xx_dss_hwmod,
3197         .slave          = &omap44xx_l3_main_1_hwmod,
3198         .clk            = "l3_div_ck",
3199         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3200 };
3201
3202 /* l3_main_2 -> l3_main_1 */
3203 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3204         .master         = &omap44xx_l3_main_2_hwmod,
3205         .slave          = &omap44xx_l3_main_1_hwmod,
3206         .clk            = "l3_div_ck",
3207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3208 };
3209
3210 /* l4_cfg -> l3_main_1 */
3211 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3212         .master         = &omap44xx_l4_cfg_hwmod,
3213         .slave          = &omap44xx_l3_main_1_hwmod,
3214         .clk            = "l4_div_ck",
3215         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3216 };
3217
3218 /* mmc1 -> l3_main_1 */
3219 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3220         .master         = &omap44xx_mmc1_hwmod,
3221         .slave          = &omap44xx_l3_main_1_hwmod,
3222         .clk            = "l3_div_ck",
3223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3224 };
3225
3226 /* mmc2 -> l3_main_1 */
3227 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3228         .master         = &omap44xx_mmc2_hwmod,
3229         .slave          = &omap44xx_l3_main_1_hwmod,
3230         .clk            = "l3_div_ck",
3231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3232 };
3233
3234 /* mpu -> l3_main_1 */
3235 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3236         .master         = &omap44xx_mpu_hwmod,
3237         .slave          = &omap44xx_l3_main_1_hwmod,
3238         .clk            = "l3_div_ck",
3239         .user           = OCP_USER_MPU,
3240 };
3241
3242 /* debugss -> l3_main_2 */
3243 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3244         .master         = &omap44xx_debugss_hwmod,
3245         .slave          = &omap44xx_l3_main_2_hwmod,
3246         .clk            = "dbgclk_mux_ck",
3247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3248 };
3249
3250 /* dma_system -> l3_main_2 */
3251 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3252         .master         = &omap44xx_dma_system_hwmod,
3253         .slave          = &omap44xx_l3_main_2_hwmod,
3254         .clk            = "l3_div_ck",
3255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3256 };
3257
3258 /* fdif -> l3_main_2 */
3259 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3260         .master         = &omap44xx_fdif_hwmod,
3261         .slave          = &omap44xx_l3_main_2_hwmod,
3262         .clk            = "l3_div_ck",
3263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3264 };
3265
3266 /* gpu -> l3_main_2 */
3267 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3268         .master         = &omap44xx_gpu_hwmod,
3269         .slave          = &omap44xx_l3_main_2_hwmod,
3270         .clk            = "l3_div_ck",
3271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3272 };
3273
3274 /* hsi -> l3_main_2 */
3275 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3276         .master         = &omap44xx_hsi_hwmod,
3277         .slave          = &omap44xx_l3_main_2_hwmod,
3278         .clk            = "l3_div_ck",
3279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3280 };
3281
3282 /* ipu -> l3_main_2 */
3283 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3284         .master         = &omap44xx_ipu_hwmod,
3285         .slave          = &omap44xx_l3_main_2_hwmod,
3286         .clk            = "l3_div_ck",
3287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3288 };
3289
3290 /* iss -> l3_main_2 */
3291 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3292         .master         = &omap44xx_iss_hwmod,
3293         .slave          = &omap44xx_l3_main_2_hwmod,
3294         .clk            = "l3_div_ck",
3295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3296 };
3297
3298 /* iva -> l3_main_2 */
3299 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3300         .master         = &omap44xx_iva_hwmod,
3301         .slave          = &omap44xx_l3_main_2_hwmod,
3302         .clk            = "l3_div_ck",
3303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3304 };
3305
3306 /* l3_main_1 -> l3_main_2 */
3307 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3308         .master         = &omap44xx_l3_main_1_hwmod,
3309         .slave          = &omap44xx_l3_main_2_hwmod,
3310         .clk            = "l3_div_ck",
3311         .user           = OCP_USER_MPU,
3312 };
3313
3314 /* l4_cfg -> l3_main_2 */
3315 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3316         .master         = &omap44xx_l4_cfg_hwmod,
3317         .slave          = &omap44xx_l3_main_2_hwmod,
3318         .clk            = "l4_div_ck",
3319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3320 };
3321
3322 /* usb_host_fs -> l3_main_2 */
3323 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3324         .master         = &omap44xx_usb_host_fs_hwmod,
3325         .slave          = &omap44xx_l3_main_2_hwmod,
3326         .clk            = "l3_div_ck",
3327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3328 };
3329
3330 /* usb_host_hs -> l3_main_2 */
3331 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3332         .master         = &omap44xx_usb_host_hs_hwmod,
3333         .slave          = &omap44xx_l3_main_2_hwmod,
3334         .clk            = "l3_div_ck",
3335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3336 };
3337
3338 /* usb_otg_hs -> l3_main_2 */
3339 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3340         .master         = &omap44xx_usb_otg_hs_hwmod,
3341         .slave          = &omap44xx_l3_main_2_hwmod,
3342         .clk            = "l3_div_ck",
3343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3344 };
3345
3346 /* l3_main_1 -> l3_main_3 */
3347 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3348         .master         = &omap44xx_l3_main_1_hwmod,
3349         .slave          = &omap44xx_l3_main_3_hwmod,
3350         .clk            = "l3_div_ck",
3351         .user           = OCP_USER_MPU,
3352 };
3353
3354 /* l3_main_2 -> l3_main_3 */
3355 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3356         .master         = &omap44xx_l3_main_2_hwmod,
3357         .slave          = &omap44xx_l3_main_3_hwmod,
3358         .clk            = "l3_div_ck",
3359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3360 };
3361
3362 /* l4_cfg -> l3_main_3 */
3363 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3364         .master         = &omap44xx_l4_cfg_hwmod,
3365         .slave          = &omap44xx_l3_main_3_hwmod,
3366         .clk            = "l4_div_ck",
3367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3368 };
3369
3370 /* aess -> l4_abe */
3371 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3372         .master         = &omap44xx_aess_hwmod,
3373         .slave          = &omap44xx_l4_abe_hwmod,
3374         .clk            = "ocp_abe_iclk",
3375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3376 };
3377
3378 /* dsp -> l4_abe */
3379 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3380         .master         = &omap44xx_dsp_hwmod,
3381         .slave          = &omap44xx_l4_abe_hwmod,
3382         .clk            = "ocp_abe_iclk",
3383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3384 };
3385
3386 /* l3_main_1 -> l4_abe */
3387 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3388         .master         = &omap44xx_l3_main_1_hwmod,
3389         .slave          = &omap44xx_l4_abe_hwmod,
3390         .clk            = "l3_div_ck",
3391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3392 };
3393
3394 /* mpu -> l4_abe */
3395 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3396         .master         = &omap44xx_mpu_hwmod,
3397         .slave          = &omap44xx_l4_abe_hwmod,
3398         .clk            = "ocp_abe_iclk",
3399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3400 };
3401
3402 /* l3_main_1 -> l4_cfg */
3403 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3404         .master         = &omap44xx_l3_main_1_hwmod,
3405         .slave          = &omap44xx_l4_cfg_hwmod,
3406         .clk            = "l3_div_ck",
3407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3408 };
3409
3410 /* l3_main_2 -> l4_per */
3411 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3412         .master         = &omap44xx_l3_main_2_hwmod,
3413         .slave          = &omap44xx_l4_per_hwmod,
3414         .clk            = "l3_div_ck",
3415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3417
3418 /* l4_cfg -> l4_wkup */
3419 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3420         .master         = &omap44xx_l4_cfg_hwmod,
3421         .slave          = &omap44xx_l4_wkup_hwmod,
3422         .clk            = "l4_div_ck",
3423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3424 };
3425
3426 /* mpu -> mpu_private */
3427 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3428         .master         = &omap44xx_mpu_hwmod,
3429         .slave          = &omap44xx_mpu_private_hwmod,
3430         .clk            = "l3_div_ck",
3431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3432 };
3433
3434 /* l4_cfg -> ocp_wp_noc */
3435 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3436         .master         = &omap44xx_l4_cfg_hwmod,
3437         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3438         .clk            = "l4_div_ck",
3439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3440 };
3441
3442 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3443         {
3444                 .name           = "dmem",
3445                 .pa_start       = 0x40180000,
3446                 .pa_end         = 0x4018ffff
3447         },
3448         {
3449                 .name           = "cmem",
3450                 .pa_start       = 0x401a0000,
3451                 .pa_end         = 0x401a1fff
3452         },
3453         {
3454                 .name           = "smem",
3455                 .pa_start       = 0x401c0000,
3456                 .pa_end         = 0x401c5fff
3457         },
3458         {
3459                 .name           = "pmem",
3460                 .pa_start       = 0x401e0000,
3461                 .pa_end         = 0x401e1fff
3462         },
3463         {
3464                 .name           = "mpu",
3465                 .pa_start       = 0x401f1000,
3466                 .pa_end         = 0x401f13ff,
3467                 .flags          = ADDR_TYPE_RT
3468         },
3469         { }
3470 };
3471
3472 /* l4_abe -> aess */
3473 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3474         .master         = &omap44xx_l4_abe_hwmod,
3475         .slave          = &omap44xx_aess_hwmod,
3476         .clk            = "ocp_abe_iclk",
3477         .addr           = omap44xx_aess_addrs,
3478         .user           = OCP_USER_MPU,
3479 };
3480
3481 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3482         {
3483                 .name           = "dmem_dma",
3484                 .pa_start       = 0x49080000,
3485                 .pa_end         = 0x4908ffff
3486         },
3487         {
3488                 .name           = "cmem_dma",
3489                 .pa_start       = 0x490a0000,
3490                 .pa_end         = 0x490a1fff
3491         },
3492         {
3493                 .name           = "smem_dma",
3494                 .pa_start       = 0x490c0000,
3495                 .pa_end         = 0x490c5fff
3496         },
3497         {
3498                 .name           = "pmem_dma",
3499                 .pa_start       = 0x490e0000,
3500                 .pa_end         = 0x490e1fff
3501         },
3502         {
3503                 .name           = "dma",
3504                 .pa_start       = 0x490f1000,
3505                 .pa_end         = 0x490f13ff,
3506                 .flags          = ADDR_TYPE_RT
3507         },
3508         { }
3509 };
3510
3511 /* l4_abe -> aess (dma) */
3512 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3513         .master         = &omap44xx_l4_abe_hwmod,
3514         .slave          = &omap44xx_aess_hwmod,
3515         .clk            = "ocp_abe_iclk",
3516         .addr           = omap44xx_aess_dma_addrs,
3517         .user           = OCP_USER_SDMA,
3518 };
3519
3520 /* l3_main_2 -> c2c */
3521 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3522         .master         = &omap44xx_l3_main_2_hwmod,
3523         .slave          = &omap44xx_c2c_hwmod,
3524         .clk            = "l3_div_ck",
3525         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3526 };
3527
3528 /* l4_wkup -> counter_32k */
3529 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3530         .master         = &omap44xx_l4_wkup_hwmod,
3531         .slave          = &omap44xx_counter_32k_hwmod,
3532         .clk            = "l4_wkup_clk_mux_ck",
3533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3534 };
3535
3536 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3537         {
3538                 .pa_start       = 0x4a002000,
3539                 .pa_end         = 0x4a0027ff,
3540                 .flags          = ADDR_TYPE_RT
3541         },
3542         { }
3543 };
3544
3545 /* l4_cfg -> ctrl_module_core */
3546 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3547         .master         = &omap44xx_l4_cfg_hwmod,
3548         .slave          = &omap44xx_ctrl_module_core_hwmod,
3549         .clk            = "l4_div_ck",
3550         .addr           = omap44xx_ctrl_module_core_addrs,
3551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3552 };
3553
3554 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3555         {
3556                 .pa_start       = 0x4a100000,
3557                 .pa_end         = 0x4a1007ff,
3558                 .flags          = ADDR_TYPE_RT
3559         },
3560         { }
3561 };
3562
3563 /* l4_cfg -> ctrl_module_pad_core */
3564 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3565         .master         = &omap44xx_l4_cfg_hwmod,
3566         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
3567         .clk            = "l4_div_ck",
3568         .addr           = omap44xx_ctrl_module_pad_core_addrs,
3569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3570 };
3571
3572 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3573         {
3574                 .pa_start       = 0x4a30c000,
3575                 .pa_end         = 0x4a30c7ff,
3576                 .flags          = ADDR_TYPE_RT
3577         },
3578         { }
3579 };
3580
3581 /* l4_wkup -> ctrl_module_wkup */
3582 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3583         .master         = &omap44xx_l4_wkup_hwmod,
3584         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
3585         .clk            = "l4_wkup_clk_mux_ck",
3586         .addr           = omap44xx_ctrl_module_wkup_addrs,
3587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3588 };
3589
3590 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3591         {
3592                 .pa_start       = 0x4a31e000,
3593                 .pa_end         = 0x4a31e7ff,
3594                 .flags          = ADDR_TYPE_RT
3595         },
3596         { }
3597 };
3598
3599 /* l4_wkup -> ctrl_module_pad_wkup */
3600 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3601         .master         = &omap44xx_l4_wkup_hwmod,
3602         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
3603         .clk            = "l4_wkup_clk_mux_ck",
3604         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
3605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3606 };
3607
3608 /* l3_instr -> debugss */
3609 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3610         .master         = &omap44xx_l3_instr_hwmod,
3611         .slave          = &omap44xx_debugss_hwmod,
3612         .clk            = "l3_div_ck",
3613         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3614 };
3615
3616 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3617         {
3618                 .pa_start       = 0x4a056000,
3619                 .pa_end         = 0x4a056fff,
3620                 .flags          = ADDR_TYPE_RT
3621         },
3622         { }
3623 };
3624
3625 /* l4_cfg -> dma_system */
3626 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3627         .master         = &omap44xx_l4_cfg_hwmod,
3628         .slave          = &omap44xx_dma_system_hwmod,
3629         .clk            = "l4_div_ck",
3630         .addr           = omap44xx_dma_system_addrs,
3631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3632 };
3633
3634 /* l4_abe -> dmic */
3635 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3636         .master         = &omap44xx_l4_abe_hwmod,
3637         .slave          = &omap44xx_dmic_hwmod,
3638         .clk            = "ocp_abe_iclk",
3639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3640 };
3641
3642 /* dsp -> iva */
3643 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3644         .master         = &omap44xx_dsp_hwmod,
3645         .slave          = &omap44xx_iva_hwmod,
3646         .clk            = "dpll_iva_m5x2_ck",
3647         .user           = OCP_USER_DSP,
3648 };
3649
3650 /* dsp -> sl2if */
3651 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3652         .master         = &omap44xx_dsp_hwmod,
3653         .slave          = &omap44xx_sl2if_hwmod,
3654         .clk            = "dpll_iva_m5x2_ck",
3655         .user           = OCP_USER_DSP,
3656 };
3657
3658 /* l4_cfg -> dsp */
3659 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3660         .master         = &omap44xx_l4_cfg_hwmod,
3661         .slave          = &omap44xx_dsp_hwmod,
3662         .clk            = "l4_div_ck",
3663         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3664 };
3665
3666 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3667         {
3668                 .pa_start       = 0x58000000,
3669                 .pa_end         = 0x5800007f,
3670                 .flags          = ADDR_TYPE_RT
3671         },
3672         { }
3673 };
3674
3675 /* l3_main_2 -> dss */
3676 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3677         .master         = &omap44xx_l3_main_2_hwmod,
3678         .slave          = &omap44xx_dss_hwmod,
3679         .clk            = "l3_div_ck",
3680         .addr           = omap44xx_dss_dma_addrs,
3681         .user           = OCP_USER_SDMA,
3682 };
3683
3684 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3685         {
3686                 .pa_start       = 0x48040000,
3687                 .pa_end         = 0x4804007f,
3688                 .flags          = ADDR_TYPE_RT
3689         },
3690         { }
3691 };
3692
3693 /* l4_per -> dss */
3694 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3695         .master         = &omap44xx_l4_per_hwmod,
3696         .slave          = &omap44xx_dss_hwmod,
3697         .clk            = "l4_div_ck",
3698         .addr           = omap44xx_dss_addrs,
3699         .user           = OCP_USER_MPU,
3700 };
3701
3702 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3703         {
3704                 .pa_start       = 0x58001000,
3705                 .pa_end         = 0x58001fff,
3706                 .flags          = ADDR_TYPE_RT
3707         },
3708         { }
3709 };
3710
3711 /* l3_main_2 -> dss_dispc */
3712 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3713         .master         = &omap44xx_l3_main_2_hwmod,
3714         .slave          = &omap44xx_dss_dispc_hwmod,
3715         .clk            = "l3_div_ck",
3716         .addr           = omap44xx_dss_dispc_dma_addrs,
3717         .user           = OCP_USER_SDMA,
3718 };
3719
3720 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3721         {
3722                 .pa_start       = 0x48041000,
3723                 .pa_end         = 0x48041fff,
3724                 .flags          = ADDR_TYPE_RT
3725         },
3726         { }
3727 };
3728
3729 /* l4_per -> dss_dispc */
3730 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3731         .master         = &omap44xx_l4_per_hwmod,
3732         .slave          = &omap44xx_dss_dispc_hwmod,
3733         .clk            = "l4_div_ck",
3734         .addr           = omap44xx_dss_dispc_addrs,
3735         .user           = OCP_USER_MPU,
3736 };
3737
3738 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3739         {
3740                 .pa_start       = 0x58004000,
3741                 .pa_end         = 0x580041ff,
3742                 .flags          = ADDR_TYPE_RT
3743         },
3744         { }
3745 };
3746
3747 /* l3_main_2 -> dss_dsi1 */
3748 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3749         .master         = &omap44xx_l3_main_2_hwmod,
3750         .slave          = &omap44xx_dss_dsi1_hwmod,
3751         .clk            = "l3_div_ck",
3752         .addr           = omap44xx_dss_dsi1_dma_addrs,
3753         .user           = OCP_USER_SDMA,
3754 };
3755
3756 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3757         {
3758                 .pa_start       = 0x48044000,
3759                 .pa_end         = 0x480441ff,
3760                 .flags          = ADDR_TYPE_RT
3761         },
3762         { }
3763 };
3764
3765 /* l4_per -> dss_dsi1 */
3766 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3767         .master         = &omap44xx_l4_per_hwmod,
3768         .slave          = &omap44xx_dss_dsi1_hwmod,
3769         .clk            = "l4_div_ck",
3770         .addr           = omap44xx_dss_dsi1_addrs,
3771         .user           = OCP_USER_MPU,
3772 };
3773
3774 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3775         {
3776                 .pa_start       = 0x58005000,
3777                 .pa_end         = 0x580051ff,
3778                 .flags          = ADDR_TYPE_RT
3779         },
3780         { }
3781 };
3782
3783 /* l3_main_2 -> dss_dsi2 */
3784 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3785         .master         = &omap44xx_l3_main_2_hwmod,
3786         .slave          = &omap44xx_dss_dsi2_hwmod,
3787         .clk            = "l3_div_ck",
3788         .addr           = omap44xx_dss_dsi2_dma_addrs,
3789         .user           = OCP_USER_SDMA,
3790 };
3791
3792 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3793         {
3794                 .pa_start       = 0x48045000,
3795                 .pa_end         = 0x480451ff,
3796                 .flags          = ADDR_TYPE_RT
3797         },
3798         { }
3799 };
3800
3801 /* l4_per -> dss_dsi2 */
3802 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3803         .master         = &omap44xx_l4_per_hwmod,
3804         .slave          = &omap44xx_dss_dsi2_hwmod,
3805         .clk            = "l4_div_ck",
3806         .addr           = omap44xx_dss_dsi2_addrs,
3807         .user           = OCP_USER_MPU,
3808 };
3809
3810 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3811         {
3812                 .pa_start       = 0x58006000,
3813                 .pa_end         = 0x58006fff,
3814                 .flags          = ADDR_TYPE_RT
3815         },
3816         { }
3817 };
3818
3819 /* l3_main_2 -> dss_hdmi */
3820 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3821         .master         = &omap44xx_l3_main_2_hwmod,
3822         .slave          = &omap44xx_dss_hdmi_hwmod,
3823         .clk            = "l3_div_ck",
3824         .addr           = omap44xx_dss_hdmi_dma_addrs,
3825         .user           = OCP_USER_SDMA,
3826 };
3827
3828 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3829         {
3830                 .pa_start       = 0x48046000,
3831                 .pa_end         = 0x48046fff,
3832                 .flags          = ADDR_TYPE_RT
3833         },
3834         { }
3835 };
3836
3837 /* l4_per -> dss_hdmi */
3838 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3839         .master         = &omap44xx_l4_per_hwmod,
3840         .slave          = &omap44xx_dss_hdmi_hwmod,
3841         .clk            = "l4_div_ck",
3842         .addr           = omap44xx_dss_hdmi_addrs,
3843         .user           = OCP_USER_MPU,
3844 };
3845
3846 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3847         {
3848                 .pa_start       = 0x58002000,
3849                 .pa_end         = 0x580020ff,
3850                 .flags          = ADDR_TYPE_RT
3851         },
3852         { }
3853 };
3854
3855 /* l3_main_2 -> dss_rfbi */
3856 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3857         .master         = &omap44xx_l3_main_2_hwmod,
3858         .slave          = &omap44xx_dss_rfbi_hwmod,
3859         .clk            = "l3_div_ck",
3860         .addr           = omap44xx_dss_rfbi_dma_addrs,
3861         .user           = OCP_USER_SDMA,
3862 };
3863
3864 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3865         {
3866                 .pa_start       = 0x48042000,
3867                 .pa_end         = 0x480420ff,
3868                 .flags          = ADDR_TYPE_RT
3869         },
3870         { }
3871 };
3872
3873 /* l4_per -> dss_rfbi */
3874 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3875         .master         = &omap44xx_l4_per_hwmod,
3876         .slave          = &omap44xx_dss_rfbi_hwmod,
3877         .clk            = "l4_div_ck",
3878         .addr           = omap44xx_dss_rfbi_addrs,
3879         .user           = OCP_USER_MPU,
3880 };
3881
3882 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3883         {
3884                 .pa_start       = 0x58003000,
3885                 .pa_end         = 0x580030ff,
3886                 .flags          = ADDR_TYPE_RT
3887         },
3888         { }
3889 };
3890
3891 /* l3_main_2 -> dss_venc */
3892 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3893         .master         = &omap44xx_l3_main_2_hwmod,
3894         .slave          = &omap44xx_dss_venc_hwmod,
3895         .clk            = "l3_div_ck",
3896         .addr           = omap44xx_dss_venc_dma_addrs,
3897         .user           = OCP_USER_SDMA,
3898 };
3899
3900 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3901         {
3902                 .pa_start       = 0x48043000,
3903                 .pa_end         = 0x480430ff,
3904                 .flags          = ADDR_TYPE_RT
3905         },
3906         { }
3907 };
3908
3909 /* l4_per -> dss_venc */
3910 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3911         .master         = &omap44xx_l4_per_hwmod,
3912         .slave          = &omap44xx_dss_venc_hwmod,
3913         .clk            = "l4_div_ck",
3914         .addr           = omap44xx_dss_venc_addrs,
3915         .user           = OCP_USER_MPU,
3916 };
3917
3918 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
3919         {
3920                 .pa_start       = 0x48078000,
3921                 .pa_end         = 0x48078fff,
3922                 .flags          = ADDR_TYPE_RT
3923         },
3924         { }
3925 };
3926
3927 /* l4_per -> elm */
3928 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3929         .master         = &omap44xx_l4_per_hwmod,
3930         .slave          = &omap44xx_elm_hwmod,
3931         .clk            = "l4_div_ck",
3932         .addr           = omap44xx_elm_addrs,
3933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3934 };
3935
3936 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3937         {
3938                 .pa_start       = 0x4a10a000,
3939                 .pa_end         = 0x4a10a1ff,
3940                 .flags          = ADDR_TYPE_RT
3941         },
3942         { }
3943 };
3944
3945 /* l4_cfg -> fdif */
3946 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3947         .master         = &omap44xx_l4_cfg_hwmod,
3948         .slave          = &omap44xx_fdif_hwmod,
3949         .clk            = "l4_div_ck",
3950         .addr           = omap44xx_fdif_addrs,
3951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3952 };
3953
3954 /* l4_wkup -> gpio1 */
3955 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3956         .master         = &omap44xx_l4_wkup_hwmod,
3957         .slave          = &omap44xx_gpio1_hwmod,
3958         .clk            = "l4_wkup_clk_mux_ck",
3959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3960 };
3961
3962 /* l4_per -> gpio2 */
3963 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3964         .master         = &omap44xx_l4_per_hwmod,
3965         .slave          = &omap44xx_gpio2_hwmod,
3966         .clk            = "l4_div_ck",
3967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3968 };
3969
3970 /* l4_per -> gpio3 */
3971 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3972         .master         = &omap44xx_l4_per_hwmod,
3973         .slave          = &omap44xx_gpio3_hwmod,
3974         .clk            = "l4_div_ck",
3975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3976 };
3977
3978 /* l4_per -> gpio4 */
3979 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3980         .master         = &omap44xx_l4_per_hwmod,
3981         .slave          = &omap44xx_gpio4_hwmod,
3982         .clk            = "l4_div_ck",
3983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3984 };
3985
3986 /* l4_per -> gpio5 */
3987 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3988         .master         = &omap44xx_l4_per_hwmod,
3989         .slave          = &omap44xx_gpio5_hwmod,
3990         .clk            = "l4_div_ck",
3991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3992 };
3993
3994 /* l4_per -> gpio6 */
3995 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3996         .master         = &omap44xx_l4_per_hwmod,
3997         .slave          = &omap44xx_gpio6_hwmod,
3998         .clk            = "l4_div_ck",
3999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4000 };
4001
4002 /* l3_main_2 -> gpmc */
4003 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4004         .master         = &omap44xx_l3_main_2_hwmod,
4005         .slave          = &omap44xx_gpmc_hwmod,
4006         .clk            = "l3_div_ck",
4007         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4008 };
4009
4010 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4011         {
4012                 .pa_start       = 0x56000000,
4013                 .pa_end         = 0x5600ffff,
4014                 .flags          = ADDR_TYPE_RT
4015         },
4016         { }
4017 };
4018
4019 /* l3_main_2 -> gpu */
4020 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4021         .master         = &omap44xx_l3_main_2_hwmod,
4022         .slave          = &omap44xx_gpu_hwmod,
4023         .clk            = "l3_div_ck",
4024         .addr           = omap44xx_gpu_addrs,
4025         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4026 };
4027
4028 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4029         {
4030                 .pa_start       = 0x480b2000,
4031                 .pa_end         = 0x480b201f,
4032                 .flags          = ADDR_TYPE_RT
4033         },
4034         { }
4035 };
4036
4037 /* l4_per -> hdq1w */
4038 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4039         .master         = &omap44xx_l4_per_hwmod,
4040         .slave          = &omap44xx_hdq1w_hwmod,
4041         .clk            = "l4_div_ck",
4042         .addr           = omap44xx_hdq1w_addrs,
4043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4044 };
4045
4046 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4047         {
4048                 .pa_start       = 0x4a058000,
4049                 .pa_end         = 0x4a05bfff,
4050                 .flags          = ADDR_TYPE_RT
4051         },
4052         { }
4053 };
4054
4055 /* l4_cfg -> hsi */
4056 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4057         .master         = &omap44xx_l4_cfg_hwmod,
4058         .slave          = &omap44xx_hsi_hwmod,
4059         .clk            = "l4_div_ck",
4060         .addr           = omap44xx_hsi_addrs,
4061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4062 };
4063
4064 /* l4_per -> i2c1 */
4065 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4066         .master         = &omap44xx_l4_per_hwmod,
4067         .slave          = &omap44xx_i2c1_hwmod,
4068         .clk            = "l4_div_ck",
4069         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4070 };
4071
4072 /* l4_per -> i2c2 */
4073 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4074         .master         = &omap44xx_l4_per_hwmod,
4075         .slave          = &omap44xx_i2c2_hwmod,
4076         .clk            = "l4_div_ck",
4077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4078 };
4079
4080 /* l4_per -> i2c3 */
4081 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4082         .master         = &omap44xx_l4_per_hwmod,
4083         .slave          = &omap44xx_i2c3_hwmod,
4084         .clk            = "l4_div_ck",
4085         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4086 };
4087
4088 /* l4_per -> i2c4 */
4089 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4090         .master         = &omap44xx_l4_per_hwmod,
4091         .slave          = &omap44xx_i2c4_hwmod,
4092         .clk            = "l4_div_ck",
4093         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4094 };
4095
4096 /* l3_main_2 -> ipu */
4097 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4098         .master         = &omap44xx_l3_main_2_hwmod,
4099         .slave          = &omap44xx_ipu_hwmod,
4100         .clk            = "l3_div_ck",
4101         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4102 };
4103
4104 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4105         {
4106                 .pa_start       = 0x52000000,
4107                 .pa_end         = 0x520000ff,
4108                 .flags          = ADDR_TYPE_RT
4109         },
4110         { }
4111 };
4112
4113 /* l3_main_2 -> iss */
4114 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4115         .master         = &omap44xx_l3_main_2_hwmod,
4116         .slave          = &omap44xx_iss_hwmod,
4117         .clk            = "l3_div_ck",
4118         .addr           = omap44xx_iss_addrs,
4119         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4120 };
4121
4122 /* iva -> sl2if */
4123 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4124         .master         = &omap44xx_iva_hwmod,
4125         .slave          = &omap44xx_sl2if_hwmod,
4126         .clk            = "dpll_iva_m5x2_ck",
4127         .user           = OCP_USER_IVA,
4128 };
4129
4130 /* l3_main_2 -> iva */
4131 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4132         .master         = &omap44xx_l3_main_2_hwmod,
4133         .slave          = &omap44xx_iva_hwmod,
4134         .clk            = "l3_div_ck",
4135         .user           = OCP_USER_MPU,
4136 };
4137
4138 /* l4_wkup -> kbd */
4139 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4140         .master         = &omap44xx_l4_wkup_hwmod,
4141         .slave          = &omap44xx_kbd_hwmod,
4142         .clk            = "l4_wkup_clk_mux_ck",
4143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4144 };
4145
4146 /* l4_cfg -> mailbox */
4147 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4148         .master         = &omap44xx_l4_cfg_hwmod,
4149         .slave          = &omap44xx_mailbox_hwmod,
4150         .clk            = "l4_div_ck",
4151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4152 };
4153
4154 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4155         {
4156                 .pa_start       = 0x40128000,
4157                 .pa_end         = 0x401283ff,
4158                 .flags          = ADDR_TYPE_RT
4159         },
4160         { }
4161 };
4162
4163 /* l4_abe -> mcasp */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4165         .master         = &omap44xx_l4_abe_hwmod,
4166         .slave          = &omap44xx_mcasp_hwmod,
4167         .clk            = "ocp_abe_iclk",
4168         .addr           = omap44xx_mcasp_addrs,
4169         .user           = OCP_USER_MPU,
4170 };
4171
4172 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4173         {
4174                 .pa_start       = 0x49028000,
4175                 .pa_end         = 0x490283ff,
4176                 .flags          = ADDR_TYPE_RT
4177         },
4178         { }
4179 };
4180
4181 /* l4_abe -> mcasp (dma) */
4182 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4183         .master         = &omap44xx_l4_abe_hwmod,
4184         .slave          = &omap44xx_mcasp_hwmod,
4185         .clk            = "ocp_abe_iclk",
4186         .addr           = omap44xx_mcasp_dma_addrs,
4187         .user           = OCP_USER_SDMA,
4188 };
4189
4190 /* l4_abe -> mcbsp1 */
4191 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4192         .master         = &omap44xx_l4_abe_hwmod,
4193         .slave          = &omap44xx_mcbsp1_hwmod,
4194         .clk            = "ocp_abe_iclk",
4195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4196 };
4197
4198 /* l4_abe -> mcbsp2 */
4199 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4200         .master         = &omap44xx_l4_abe_hwmod,
4201         .slave          = &omap44xx_mcbsp2_hwmod,
4202         .clk            = "ocp_abe_iclk",
4203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4204 };
4205
4206 /* l4_abe -> mcbsp3 */
4207 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4208         .master         = &omap44xx_l4_abe_hwmod,
4209         .slave          = &omap44xx_mcbsp3_hwmod,
4210         .clk            = "ocp_abe_iclk",
4211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4212 };
4213
4214 /* l4_per -> mcbsp4 */
4215 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4216         .master         = &omap44xx_l4_per_hwmod,
4217         .slave          = &omap44xx_mcbsp4_hwmod,
4218         .clk            = "l4_div_ck",
4219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4220 };
4221
4222 /* l4_abe -> mcpdm */
4223 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4224         .master         = &omap44xx_l4_abe_hwmod,
4225         .slave          = &omap44xx_mcpdm_hwmod,
4226         .clk            = "ocp_abe_iclk",
4227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4228 };
4229
4230 /* l4_per -> mcspi1 */
4231 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4232         .master         = &omap44xx_l4_per_hwmod,
4233         .slave          = &omap44xx_mcspi1_hwmod,
4234         .clk            = "l4_div_ck",
4235         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4236 };
4237
4238 /* l4_per -> mcspi2 */
4239 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4240         .master         = &omap44xx_l4_per_hwmod,
4241         .slave          = &omap44xx_mcspi2_hwmod,
4242         .clk            = "l4_div_ck",
4243         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4244 };
4245
4246 /* l4_per -> mcspi3 */
4247 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4248         .master         = &omap44xx_l4_per_hwmod,
4249         .slave          = &omap44xx_mcspi3_hwmod,
4250         .clk            = "l4_div_ck",
4251         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4252 };
4253
4254 /* l4_per -> mcspi4 */
4255 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4256         .master         = &omap44xx_l4_per_hwmod,
4257         .slave          = &omap44xx_mcspi4_hwmod,
4258         .clk            = "l4_div_ck",
4259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4260 };
4261
4262 /* l4_per -> mmc1 */
4263 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4264         .master         = &omap44xx_l4_per_hwmod,
4265         .slave          = &omap44xx_mmc1_hwmod,
4266         .clk            = "l4_div_ck",
4267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4268 };
4269
4270 /* l4_per -> mmc2 */
4271 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4272         .master         = &omap44xx_l4_per_hwmod,
4273         .slave          = &omap44xx_mmc2_hwmod,
4274         .clk            = "l4_div_ck",
4275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4276 };
4277
4278 /* l4_per -> mmc3 */
4279 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4280         .master         = &omap44xx_l4_per_hwmod,
4281         .slave          = &omap44xx_mmc3_hwmod,
4282         .clk            = "l4_div_ck",
4283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4284 };
4285
4286 /* l4_per -> mmc4 */
4287 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4288         .master         = &omap44xx_l4_per_hwmod,
4289         .slave          = &omap44xx_mmc4_hwmod,
4290         .clk            = "l4_div_ck",
4291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4292 };
4293
4294 /* l4_per -> mmc5 */
4295 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4296         .master         = &omap44xx_l4_per_hwmod,
4297         .slave          = &omap44xx_mmc5_hwmod,
4298         .clk            = "l4_div_ck",
4299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4300 };
4301
4302 /* l3_main_2 -> ocmc_ram */
4303 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4304         .master         = &omap44xx_l3_main_2_hwmod,
4305         .slave          = &omap44xx_ocmc_ram_hwmod,
4306         .clk            = "l3_div_ck",
4307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4308 };
4309
4310 /* l4_cfg -> ocp2scp_usb_phy */
4311 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4312         .master         = &omap44xx_l4_cfg_hwmod,
4313         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
4314         .clk            = "l4_div_ck",
4315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4316 };
4317
4318 /* mpu_private -> prcm_mpu */
4319 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4320         .master         = &omap44xx_mpu_private_hwmod,
4321         .slave          = &omap44xx_prcm_mpu_hwmod,
4322         .clk            = "l3_div_ck",
4323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4324 };
4325
4326 /* l4_wkup -> cm_core_aon */
4327 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4328         .master         = &omap44xx_l4_wkup_hwmod,
4329         .slave          = &omap44xx_cm_core_aon_hwmod,
4330         .clk            = "l4_wkup_clk_mux_ck",
4331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4332 };
4333
4334 /* l4_cfg -> cm_core */
4335 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4336         .master         = &omap44xx_l4_cfg_hwmod,
4337         .slave          = &omap44xx_cm_core_hwmod,
4338         .clk            = "l4_div_ck",
4339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4340 };
4341
4342 /* l4_wkup -> prm */
4343 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4344         .master         = &omap44xx_l4_wkup_hwmod,
4345         .slave          = &omap44xx_prm_hwmod,
4346         .clk            = "l4_wkup_clk_mux_ck",
4347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4348 };
4349
4350 /* l4_wkup -> scrm */
4351 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4352         .master         = &omap44xx_l4_wkup_hwmod,
4353         .slave          = &omap44xx_scrm_hwmod,
4354         .clk            = "l4_wkup_clk_mux_ck",
4355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4356 };
4357
4358 /* l3_main_2 -> sl2if */
4359 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4360         .master         = &omap44xx_l3_main_2_hwmod,
4361         .slave          = &omap44xx_sl2if_hwmod,
4362         .clk            = "l3_div_ck",
4363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4364 };
4365
4366 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4367         {
4368                 .pa_start       = 0x4012c000,
4369                 .pa_end         = 0x4012c3ff,
4370                 .flags          = ADDR_TYPE_RT
4371         },
4372         { }
4373 };
4374
4375 /* l4_abe -> slimbus1 */
4376 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4377         .master         = &omap44xx_l4_abe_hwmod,
4378         .slave          = &omap44xx_slimbus1_hwmod,
4379         .clk            = "ocp_abe_iclk",
4380         .addr           = omap44xx_slimbus1_addrs,
4381         .user           = OCP_USER_MPU,
4382 };
4383
4384 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4385         {
4386                 .pa_start       = 0x4902c000,
4387                 .pa_end         = 0x4902c3ff,
4388                 .flags          = ADDR_TYPE_RT
4389         },
4390         { }
4391 };
4392
4393 /* l4_abe -> slimbus1 (dma) */
4394 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4395         .master         = &omap44xx_l4_abe_hwmod,
4396         .slave          = &omap44xx_slimbus1_hwmod,
4397         .clk            = "ocp_abe_iclk",
4398         .addr           = omap44xx_slimbus1_dma_addrs,
4399         .user           = OCP_USER_SDMA,
4400 };
4401
4402 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4403         {
4404                 .pa_start       = 0x48076000,
4405                 .pa_end         = 0x480763ff,
4406                 .flags          = ADDR_TYPE_RT
4407         },
4408         { }
4409 };
4410
4411 /* l4_per -> slimbus2 */
4412 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4413         .master         = &omap44xx_l4_per_hwmod,
4414         .slave          = &omap44xx_slimbus2_hwmod,
4415         .clk            = "l4_div_ck",
4416         .addr           = omap44xx_slimbus2_addrs,
4417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4418 };
4419
4420 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4421         {
4422                 .pa_start       = 0x4a0dd000,
4423                 .pa_end         = 0x4a0dd03f,
4424                 .flags          = ADDR_TYPE_RT
4425         },
4426         { }
4427 };
4428
4429 /* l4_cfg -> smartreflex_core */
4430 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4431         .master         = &omap44xx_l4_cfg_hwmod,
4432         .slave          = &omap44xx_smartreflex_core_hwmod,
4433         .clk            = "l4_div_ck",
4434         .addr           = omap44xx_smartreflex_core_addrs,
4435         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4436 };
4437
4438 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4439         {
4440                 .pa_start       = 0x4a0db000,
4441                 .pa_end         = 0x4a0db03f,
4442                 .flags          = ADDR_TYPE_RT
4443         },
4444         { }
4445 };
4446
4447 /* l4_cfg -> smartreflex_iva */
4448 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4449         .master         = &omap44xx_l4_cfg_hwmod,
4450         .slave          = &omap44xx_smartreflex_iva_hwmod,
4451         .clk            = "l4_div_ck",
4452         .addr           = omap44xx_smartreflex_iva_addrs,
4453         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4454 };
4455
4456 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4457         {
4458                 .pa_start       = 0x4a0d9000,
4459                 .pa_end         = 0x4a0d903f,
4460                 .flags          = ADDR_TYPE_RT
4461         },
4462         { }
4463 };
4464
4465 /* l4_cfg -> smartreflex_mpu */
4466 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4467         .master         = &omap44xx_l4_cfg_hwmod,
4468         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4469         .clk            = "l4_div_ck",
4470         .addr           = omap44xx_smartreflex_mpu_addrs,
4471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4472 };
4473
4474 /* l4_cfg -> spinlock */
4475 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4476         .master         = &omap44xx_l4_cfg_hwmod,
4477         .slave          = &omap44xx_spinlock_hwmod,
4478         .clk            = "l4_div_ck",
4479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4480 };
4481
4482 /* l4_wkup -> timer1 */
4483 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4484         .master         = &omap44xx_l4_wkup_hwmod,
4485         .slave          = &omap44xx_timer1_hwmod,
4486         .clk            = "l4_wkup_clk_mux_ck",
4487         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4488 };
4489
4490 /* l4_per -> timer2 */
4491 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4492         .master         = &omap44xx_l4_per_hwmod,
4493         .slave          = &omap44xx_timer2_hwmod,
4494         .clk            = "l4_div_ck",
4495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4496 };
4497
4498 /* l4_per -> timer3 */
4499 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4500         .master         = &omap44xx_l4_per_hwmod,
4501         .slave          = &omap44xx_timer3_hwmod,
4502         .clk            = "l4_div_ck",
4503         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4504 };
4505
4506 /* l4_per -> timer4 */
4507 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4508         .master         = &omap44xx_l4_per_hwmod,
4509         .slave          = &omap44xx_timer4_hwmod,
4510         .clk            = "l4_div_ck",
4511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4512 };
4513
4514 /* l4_abe -> timer5 */
4515 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4516         .master         = &omap44xx_l4_abe_hwmod,
4517         .slave          = &omap44xx_timer5_hwmod,
4518         .clk            = "ocp_abe_iclk",
4519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4520 };
4521
4522 /* l4_abe -> timer6 */
4523 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4524         .master         = &omap44xx_l4_abe_hwmod,
4525         .slave          = &omap44xx_timer6_hwmod,
4526         .clk            = "ocp_abe_iclk",
4527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4528 };
4529
4530 /* l4_abe -> timer7 */
4531 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4532         .master         = &omap44xx_l4_abe_hwmod,
4533         .slave          = &omap44xx_timer7_hwmod,
4534         .clk            = "ocp_abe_iclk",
4535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4536 };
4537
4538 /* l4_abe -> timer8 */
4539 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4540         .master         = &omap44xx_l4_abe_hwmod,
4541         .slave          = &omap44xx_timer8_hwmod,
4542         .clk            = "ocp_abe_iclk",
4543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4544 };
4545
4546 /* l4_per -> timer9 */
4547 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4548         .master         = &omap44xx_l4_per_hwmod,
4549         .slave          = &omap44xx_timer9_hwmod,
4550         .clk            = "l4_div_ck",
4551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4552 };
4553
4554 /* l4_per -> timer10 */
4555 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4556         .master         = &omap44xx_l4_per_hwmod,
4557         .slave          = &omap44xx_timer10_hwmod,
4558         .clk            = "l4_div_ck",
4559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4560 };
4561
4562 /* l4_per -> timer11 */
4563 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4564         .master         = &omap44xx_l4_per_hwmod,
4565         .slave          = &omap44xx_timer11_hwmod,
4566         .clk            = "l4_div_ck",
4567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4568 };
4569
4570 /* l4_per -> uart1 */
4571 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4572         .master         = &omap44xx_l4_per_hwmod,
4573         .slave          = &omap44xx_uart1_hwmod,
4574         .clk            = "l4_div_ck",
4575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4576 };
4577
4578 /* l4_per -> uart2 */
4579 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4580         .master         = &omap44xx_l4_per_hwmod,
4581         .slave          = &omap44xx_uart2_hwmod,
4582         .clk            = "l4_div_ck",
4583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4584 };
4585
4586 /* l4_per -> uart3 */
4587 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4588         .master         = &omap44xx_l4_per_hwmod,
4589         .slave          = &omap44xx_uart3_hwmod,
4590         .clk            = "l4_div_ck",
4591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4592 };
4593
4594 /* l4_per -> uart4 */
4595 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4596         .master         = &omap44xx_l4_per_hwmod,
4597         .slave          = &omap44xx_uart4_hwmod,
4598         .clk            = "l4_div_ck",
4599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4600 };
4601
4602 /* l4_cfg -> usb_host_fs */
4603 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4604         .master         = &omap44xx_l4_cfg_hwmod,
4605         .slave          = &omap44xx_usb_host_fs_hwmod,
4606         .clk            = "l4_div_ck",
4607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4608 };
4609
4610 /* l4_cfg -> usb_host_hs */
4611 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4612         .master         = &omap44xx_l4_cfg_hwmod,
4613         .slave          = &omap44xx_usb_host_hs_hwmod,
4614         .clk            = "l4_div_ck",
4615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4616 };
4617
4618 /* l4_cfg -> usb_otg_hs */
4619 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4620         .master         = &omap44xx_l4_cfg_hwmod,
4621         .slave          = &omap44xx_usb_otg_hs_hwmod,
4622         .clk            = "l4_div_ck",
4623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4624 };
4625
4626 /* l4_cfg -> usb_tll_hs */
4627 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4628         .master         = &omap44xx_l4_cfg_hwmod,
4629         .slave          = &omap44xx_usb_tll_hs_hwmod,
4630         .clk            = "l4_div_ck",
4631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4632 };
4633
4634 /* l4_wkup -> wd_timer2 */
4635 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4636         .master         = &omap44xx_l4_wkup_hwmod,
4637         .slave          = &omap44xx_wd_timer2_hwmod,
4638         .clk            = "l4_wkup_clk_mux_ck",
4639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4640 };
4641
4642 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4643         {
4644                 .pa_start       = 0x40130000,
4645                 .pa_end         = 0x4013007f,
4646                 .flags          = ADDR_TYPE_RT
4647         },
4648         { }
4649 };
4650
4651 /* l4_abe -> wd_timer3 */
4652 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4653         .master         = &omap44xx_l4_abe_hwmod,
4654         .slave          = &omap44xx_wd_timer3_hwmod,
4655         .clk            = "ocp_abe_iclk",
4656         .addr           = omap44xx_wd_timer3_addrs,
4657         .user           = OCP_USER_MPU,
4658 };
4659
4660 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4661         {
4662                 .pa_start       = 0x49030000,
4663                 .pa_end         = 0x4903007f,
4664                 .flags          = ADDR_TYPE_RT
4665         },
4666         { }
4667 };
4668
4669 /* l4_abe -> wd_timer3 (dma) */
4670 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4671         .master         = &omap44xx_l4_abe_hwmod,
4672         .slave          = &omap44xx_wd_timer3_hwmod,
4673         .clk            = "ocp_abe_iclk",
4674         .addr           = omap44xx_wd_timer3_dma_addrs,
4675         .user           = OCP_USER_SDMA,
4676 };
4677
4678 /* mpu -> emif1 */
4679 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4680         .master         = &omap44xx_mpu_hwmod,
4681         .slave          = &omap44xx_emif1_hwmod,
4682         .clk            = "l3_div_ck",
4683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4684 };
4685
4686 /* mpu -> emif2 */
4687 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4688         .master         = &omap44xx_mpu_hwmod,
4689         .slave          = &omap44xx_emif2_hwmod,
4690         .clk            = "l3_div_ck",
4691         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4692 };
4693
4694 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4695         &omap44xx_l3_main_1__dmm,
4696         &omap44xx_mpu__dmm,
4697         &omap44xx_iva__l3_instr,
4698         &omap44xx_l3_main_3__l3_instr,
4699         &omap44xx_ocp_wp_noc__l3_instr,
4700         &omap44xx_dsp__l3_main_1,
4701         &omap44xx_dss__l3_main_1,
4702         &omap44xx_l3_main_2__l3_main_1,
4703         &omap44xx_l4_cfg__l3_main_1,
4704         &omap44xx_mmc1__l3_main_1,
4705         &omap44xx_mmc2__l3_main_1,
4706         &omap44xx_mpu__l3_main_1,
4707         &omap44xx_debugss__l3_main_2,
4708         &omap44xx_dma_system__l3_main_2,
4709         &omap44xx_fdif__l3_main_2,
4710         &omap44xx_gpu__l3_main_2,
4711         &omap44xx_hsi__l3_main_2,
4712         &omap44xx_ipu__l3_main_2,
4713         &omap44xx_iss__l3_main_2,
4714         &omap44xx_iva__l3_main_2,
4715         &omap44xx_l3_main_1__l3_main_2,
4716         &omap44xx_l4_cfg__l3_main_2,
4717         /* &omap44xx_usb_host_fs__l3_main_2, */
4718         &omap44xx_usb_host_hs__l3_main_2,
4719         &omap44xx_usb_otg_hs__l3_main_2,
4720         &omap44xx_l3_main_1__l3_main_3,
4721         &omap44xx_l3_main_2__l3_main_3,
4722         &omap44xx_l4_cfg__l3_main_3,
4723         &omap44xx_aess__l4_abe,
4724         &omap44xx_dsp__l4_abe,
4725         &omap44xx_l3_main_1__l4_abe,
4726         &omap44xx_mpu__l4_abe,
4727         &omap44xx_l3_main_1__l4_cfg,
4728         &omap44xx_l3_main_2__l4_per,
4729         &omap44xx_l4_cfg__l4_wkup,
4730         &omap44xx_mpu__mpu_private,
4731         &omap44xx_l4_cfg__ocp_wp_noc,
4732         &omap44xx_l4_abe__aess,
4733         &omap44xx_l4_abe__aess_dma,
4734         &omap44xx_l3_main_2__c2c,
4735         &omap44xx_l4_wkup__counter_32k,
4736         &omap44xx_l4_cfg__ctrl_module_core,
4737         &omap44xx_l4_cfg__ctrl_module_pad_core,
4738         &omap44xx_l4_wkup__ctrl_module_wkup,
4739         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4740         &omap44xx_l3_instr__debugss,
4741         &omap44xx_l4_cfg__dma_system,
4742         &omap44xx_l4_abe__dmic,
4743         &omap44xx_dsp__iva,
4744         /* &omap44xx_dsp__sl2if, */
4745         &omap44xx_l4_cfg__dsp,
4746         &omap44xx_l3_main_2__dss,
4747         &omap44xx_l4_per__dss,
4748         &omap44xx_l3_main_2__dss_dispc,
4749         &omap44xx_l4_per__dss_dispc,
4750         &omap44xx_l3_main_2__dss_dsi1,
4751         &omap44xx_l4_per__dss_dsi1,
4752         &omap44xx_l3_main_2__dss_dsi2,
4753         &omap44xx_l4_per__dss_dsi2,
4754         &omap44xx_l3_main_2__dss_hdmi,
4755         &omap44xx_l4_per__dss_hdmi,
4756         &omap44xx_l3_main_2__dss_rfbi,
4757         &omap44xx_l4_per__dss_rfbi,
4758         &omap44xx_l3_main_2__dss_venc,
4759         &omap44xx_l4_per__dss_venc,
4760         &omap44xx_l4_per__elm,
4761         &omap44xx_l4_cfg__fdif,
4762         &omap44xx_l4_wkup__gpio1,
4763         &omap44xx_l4_per__gpio2,
4764         &omap44xx_l4_per__gpio3,
4765         &omap44xx_l4_per__gpio4,
4766         &omap44xx_l4_per__gpio5,
4767         &omap44xx_l4_per__gpio6,
4768         &omap44xx_l3_main_2__gpmc,
4769         &omap44xx_l3_main_2__gpu,
4770         &omap44xx_l4_per__hdq1w,
4771         &omap44xx_l4_cfg__hsi,
4772         &omap44xx_l4_per__i2c1,
4773         &omap44xx_l4_per__i2c2,
4774         &omap44xx_l4_per__i2c3,
4775         &omap44xx_l4_per__i2c4,
4776         &omap44xx_l3_main_2__ipu,
4777         &omap44xx_l3_main_2__iss,
4778         /* &omap44xx_iva__sl2if, */
4779         &omap44xx_l3_main_2__iva,
4780         &omap44xx_l4_wkup__kbd,
4781         &omap44xx_l4_cfg__mailbox,
4782         &omap44xx_l4_abe__mcasp,
4783         &omap44xx_l4_abe__mcasp_dma,
4784         &omap44xx_l4_abe__mcbsp1,
4785         &omap44xx_l4_abe__mcbsp2,
4786         &omap44xx_l4_abe__mcbsp3,
4787         &omap44xx_l4_per__mcbsp4,
4788         &omap44xx_l4_abe__mcpdm,
4789         &omap44xx_l4_per__mcspi1,
4790         &omap44xx_l4_per__mcspi2,
4791         &omap44xx_l4_per__mcspi3,
4792         &omap44xx_l4_per__mcspi4,
4793         &omap44xx_l4_per__mmc1,
4794         &omap44xx_l4_per__mmc2,
4795         &omap44xx_l4_per__mmc3,
4796         &omap44xx_l4_per__mmc4,
4797         &omap44xx_l4_per__mmc5,
4798         &omap44xx_l3_main_2__mmu_ipu,
4799         &omap44xx_l4_cfg__mmu_dsp,
4800         &omap44xx_l3_main_2__ocmc_ram,
4801         &omap44xx_l4_cfg__ocp2scp_usb_phy,
4802         &omap44xx_mpu_private__prcm_mpu,
4803         &omap44xx_l4_wkup__cm_core_aon,
4804         &omap44xx_l4_cfg__cm_core,
4805         &omap44xx_l4_wkup__prm,
4806         &omap44xx_l4_wkup__scrm,
4807         /* &omap44xx_l3_main_2__sl2if, */
4808         &omap44xx_l4_abe__slimbus1,
4809         &omap44xx_l4_abe__slimbus1_dma,
4810         &omap44xx_l4_per__slimbus2,
4811         &omap44xx_l4_cfg__smartreflex_core,
4812         &omap44xx_l4_cfg__smartreflex_iva,
4813         &omap44xx_l4_cfg__smartreflex_mpu,
4814         &omap44xx_l4_cfg__spinlock,
4815         &omap44xx_l4_wkup__timer1,
4816         &omap44xx_l4_per__timer2,
4817         &omap44xx_l4_per__timer3,
4818         &omap44xx_l4_per__timer4,
4819         &omap44xx_l4_abe__timer5,
4820         &omap44xx_l4_abe__timer6,
4821         &omap44xx_l4_abe__timer7,
4822         &omap44xx_l4_abe__timer8,
4823         &omap44xx_l4_per__timer9,
4824         &omap44xx_l4_per__timer10,
4825         &omap44xx_l4_per__timer11,
4826         &omap44xx_l4_per__uart1,
4827         &omap44xx_l4_per__uart2,
4828         &omap44xx_l4_per__uart3,
4829         &omap44xx_l4_per__uart4,
4830         /* &omap44xx_l4_cfg__usb_host_fs, */
4831         &omap44xx_l4_cfg__usb_host_hs,
4832         &omap44xx_l4_cfg__usb_otg_hs,
4833         &omap44xx_l4_cfg__usb_tll_hs,
4834         &omap44xx_l4_wkup__wd_timer2,
4835         &omap44xx_l4_abe__wd_timer3,
4836         &omap44xx_l4_abe__wd_timer3_dma,
4837         &omap44xx_mpu__emif1,
4838         &omap44xx_mpu__emif2,
4839         NULL,
4840 };
4841
4842 int __init omap44xx_hwmod_init(void)
4843 {
4844         omap_hwmod_init();
4845         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4846 }
4847