arch/arm/mach-pxa/zeus.c

   1 /*
   2  *  Support for the Arcom ZEUS.
   3  *
   4  *  Copyright (C) 2006 Arcom Control Systems Ltd.
   5  *
   6  *  Loosely based on Arcom's 2.6.16.28.
   7  *  Maintained by Marc Zyngier <maz@misterjones.org>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/cpufreq.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/pm.h>
  18 #include <linux/gpio.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/dm9000.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/pxa2xx_spi.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/partitions.h>
  26 #include <linux/mtd/physmap.h>
  27 #include <linux/i2c.h>
  28 #include <linux/i2c/pxa-i2c.h>
  29 #include <linux/platform_data/pca953x.h>
  30 #include <linux/apm-emulation.h>
  31 #include <linux/can/platform/mcp251x.h>
  32 #include <linux/regulator/fixed.h>
  33 #include <linux/regulator/machine.h>
  34
  35 #include <asm/mach-types.h>
  36 #include <asm/suspend.h>
  37 #include <asm/system_info.h>
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/map.h>
  40
  41 #include <mach/pxa27x.h>
  42 #include <mach/regs-uart.h>
  43 #include <linux/platform_data/usb-ohci-pxa27x.h>
  44 #include <linux/platform_data/mmc-pxamci.h>
  45 #include <mach/pxa27x-udc.h>
  46 #include <mach/udc.h>
  47 #include <linux/platform_data/video-pxafb.h>
  48 #include <mach/pm.h>
  49 #include <mach/audio.h>
  50 #include <linux/platform_data/pcmcia-pxa2xx_viper.h>
  51 #include <mach/zeus.h>
  52 #include <mach/smemc.h>
  53
  54 #include "generic.h"
  55
  56 /*
  57  * Interrupt handling
  58  */
  59
  60 static unsigned long zeus_irq_enabled_mask;
  61 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
  62 static const int zeus_isa_irq_map[] = {
  63         0,              /* ISA irq #0, invalid */
  64         0,              /* ISA irq #1, invalid */
  65         0,              /* ISA irq #2, invalid */
  66         1 << 0,         /* ISA irq #3 */
  67         1 << 1,         /* ISA irq #4 */
  68         1 << 2,         /* ISA irq #5 */
  69         1 << 3,         /* ISA irq #6 */
  70         1 << 4,         /* ISA irq #7 */
  71         0,              /* ISA irq #8, invalid */
  72         0,              /* ISA irq #9, invalid */
  73         1 << 5,         /* ISA irq #10 */
  74         1 << 6,         /* ISA irq #11 */
  75         1 << 7,         /* ISA irq #12 */
  76 };
  77
  78 static inline int zeus_irq_to_bitmask(unsigned int irq)
  79 {
  80         return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
  81 }
  82
  83 static inline int zeus_bit_to_irq(int bit)
  84 {
  85         return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
  86 }
  87
  88 static void zeus_ack_irq(struct irq_data *d)
  89 {
  90         __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
  91 }
  92
  93 static void zeus_mask_irq(struct irq_data *d)
  94 {
  95         zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
  96 }
  97
  98 static void zeus_unmask_irq(struct irq_data *d)
  99 {
 100         zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
 101 }
 102
 103 static inline unsigned long zeus_irq_pending(void)
 104 {
 105         return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
 106 }
 107
 108 static void zeus_irq_handler(struct irq_desc *desc)
 109 {
 110         unsigned int irq;
 111         unsigned long pending;
 112
 113         pending = zeus_irq_pending();
 114         do {
 115                 /* we're in a chained irq handler,
 116                  * so ack the interrupt by hand */
 117                 desc->irq_data.chip->irq_ack(&desc->irq_data);
 118
 119                 if (likely(pending)) {
 120                         irq = zeus_bit_to_irq(__ffs(pending));
 121                         generic_handle_irq(irq);
 122                 }
 123                 pending = zeus_irq_pending();
 124         } while (pending);
 125 }
 126
 127 static struct irq_chip zeus_irq_chip = {
 128         .name           = "ISA",
 129         .irq_ack        = zeus_ack_irq,
 130         .irq_mask       = zeus_mask_irq,
 131         .irq_unmask     = zeus_unmask_irq,
 132 };
 133
 134 static void __init zeus_init_irq(void)
 135 {
 136         int level;
 137         int isa_irq;
 138
 139         pxa27x_init_irq();
 140
 141         /* Peripheral IRQs. It would be nice to move those inside driver
 142            configuration, but it is not supported at the moment. */
 143         irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
 144         irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
 145         irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
 146         irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
 147                          IRQ_TYPE_EDGE_FALLING);
 148         irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
 149
 150         /* Setup ISA IRQs */
 151         for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
 152                 isa_irq = zeus_bit_to_irq(level);
 153                 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
 154                                          handle_edge_irq);
 155                 irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
 156         }
 157
 158         irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
 159         irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
 160 }
 161
 162
 163 /*
 164  * Platform devices
 165  */
 166
 167 /* Flash */
 168 static struct resource zeus_mtd_resources[] = {
 169         [0] = { /* NOR Flash (up to 64MB) */
 170                 .start  = ZEUS_FLASH_PHYS,
 171                 .end    = ZEUS_FLASH_PHYS + SZ_64M - 1,
 172                 .flags  = IORESOURCE_MEM,
 173         },
 174         [1] = { /* SRAM */
 175                 .start  = ZEUS_SRAM_PHYS,
 176                 .end    = ZEUS_SRAM_PHYS + SZ_512K - 1,
 177                 .flags  = IORESOURCE_MEM,
 178         },
 179 };
 180
 181 static struct physmap_flash_data zeus_flash_data[] = {
 182         [0] = {
 183                 .width          = 2,
 184                 .parts          = NULL,
 185                 .nr_parts       = 0,
 186         },
 187 };
 188
 189 static struct platform_device zeus_mtd_devices[] = {
 190         [0] = {
 191                 .name           = "physmap-flash",
 192                 .id             = 0,
 193                 .dev            = {
 194                         .platform_data = &zeus_flash_data[0],
 195                 },
 196                 .resource       = &zeus_mtd_resources[0],
 197                 .num_resources  = 1,
 198         },
 199 };
 200
 201 /* Serial */
 202 static struct resource zeus_serial_resources[] = {
 203         {
 204                 .start  = 0x10000000,
 205                 .end    = 0x1000000f,
 206                 .flags  = IORESOURCE_MEM,
 207         },
 208         {
 209                 .start  = 0x10800000,
 210                 .end    = 0x1080000f,
 211                 .flags  = IORESOURCE_MEM,
 212         },
 213         {
 214                 .start  = 0x11000000,
 215                 .end    = 0x1100000f,
 216                 .flags  = IORESOURCE_MEM,
 217         },
 218         {
 219                 .start  = 0x40100000,
 220                 .end    = 0x4010001f,
 221                 .flags  = IORESOURCE_MEM,
 222         },
 223         {
 224                 .start  = 0x40200000,
 225                 .end    = 0x4020001f,
 226                 .flags  = IORESOURCE_MEM,
 227         },
 228         {
 229                 .start  = 0x40700000,
 230                 .end    = 0x4070001f,
 231                 .flags  = IORESOURCE_MEM,
 232         },
 233 };
 234
 235 static struct plat_serial8250_port serial_platform_data[] = {
 236         /* External UARTs */
 237         /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
 238         { /* COM1 */
 239                 .mapbase        = 0x10000000,
 240                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
 241                 .irqflags       = IRQF_TRIGGER_RISING,
 242                 .uartclk        = 14745600,
 243                 .regshift       = 1,
 244                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 245                 .iotype         = UPIO_MEM,
 246         },
 247         { /* COM2 */
 248                 .mapbase        = 0x10800000,
 249                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
 250                 .irqflags       = IRQF_TRIGGER_RISING,
 251                 .uartclk        = 14745600,
 252                 .regshift       = 1,
 253                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 254                 .iotype         = UPIO_MEM,
 255         },
 256         { /* COM3 */
 257                 .mapbase        = 0x11000000,
 258                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
 259                 .irqflags       = IRQF_TRIGGER_RISING,
 260                 .uartclk        = 14745600,
 261                 .regshift       = 1,
 262                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 263                 .iotype         = UPIO_MEM,
 264         },
 265         { /* COM4 */
 266                 .mapbase        = 0x11800000,
 267                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
 268                 .irqflags       = IRQF_TRIGGER_RISING,
 269                 .uartclk        = 14745600,
 270                 .regshift       = 1,
 271                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 272                 .iotype         = UPIO_MEM,
 273         },
 274         /* Internal UARTs */
 275         { /* FFUART */
 276                 .membase        = (void *)&FFUART,
 277                 .mapbase        = __PREG(FFUART),
 278                 .irq            = IRQ_FFUART,
 279                 .uartclk        = 921600 * 16,
 280                 .regshift       = 2,
 281                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 282                 .iotype         = UPIO_MEM,
 283         },
 284         { /* BTUART */
 285                 .membase        = (void *)&BTUART,
 286                 .mapbase        = __PREG(BTUART),
 287                 .irq            = IRQ_BTUART,
 288                 .uartclk        = 921600 * 16,
 289                 .regshift       = 2,
 290                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 291                 .iotype         = UPIO_MEM,
 292         },
 293         { /* STUART */
 294                 .membase        = (void *)&STUART,
 295                 .mapbase        = __PREG(STUART),
 296                 .irq            = IRQ_STUART,
 297                 .uartclk        = 921600 * 16,
 298                 .regshift       = 2,
 299                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 300                 .iotype         = UPIO_MEM,
 301         },
 302         { },
 303 };
 304
 305 static struct platform_device zeus_serial_device = {
 306         .name = "serial8250",
 307         .id   = PLAT8250_DEV_PLATFORM,
 308         .dev  = {
 309                 .platform_data = serial_platform_data,
 310         },
 311         .num_resources  = ARRAY_SIZE(zeus_serial_resources),
 312         .resource       = zeus_serial_resources,
 313 };
 314
 315 /* Ethernet */
 316 static struct resource zeus_dm9k0_resource[] = {
 317         [0] = {
 318                 .start = ZEUS_ETH0_PHYS,
 319                 .end   = ZEUS_ETH0_PHYS + 1,
 320                 .flags = IORESOURCE_MEM
 321         },
 322         [1] = {
 323                 .start = ZEUS_ETH0_PHYS + 2,
 324                 .end   = ZEUS_ETH0_PHYS + 3,
 325                 .flags = IORESOURCE_MEM
 326         },
 327         [2] = {
 328                 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
 329                 .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
 330                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 331         },
 332 };
 333
 334 static struct resource zeus_dm9k1_resource[] = {
 335         [0] = {
 336                 .start = ZEUS_ETH1_PHYS,
 337                 .end   = ZEUS_ETH1_PHYS + 1,
 338                 .flags = IORESOURCE_MEM
 339         },
 340         [1] = {
 341                 .start = ZEUS_ETH1_PHYS + 2,
 342                 .end   = ZEUS_ETH1_PHYS + 3,
 343                 .flags = IORESOURCE_MEM,
 344         },
 345         [2] = {
 346                 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
 347                 .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
 348                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 349         },
 350 };
 351
 352 static struct dm9000_plat_data zeus_dm9k_platdata = {
 353         .flags          = DM9000_PLATF_16BITONLY,
 354 };
 355
 356 static struct platform_device zeus_dm9k0_device = {
 357         .name           = "dm9000",
 358         .id             = 0,
 359         .num_resources  = ARRAY_SIZE(zeus_dm9k0_resource),
 360         .resource       = zeus_dm9k0_resource,
 361         .dev            = {
 362                 .platform_data = &zeus_dm9k_platdata,
 363         }
 364 };
 365
 366 static struct platform_device zeus_dm9k1_device = {
 367         .name           = "dm9000",
 368         .id             = 1,
 369         .num_resources  = ARRAY_SIZE(zeus_dm9k1_resource),
 370         .resource       = zeus_dm9k1_resource,
 371         .dev            = {
 372                 .platform_data = &zeus_dm9k_platdata,
 373         }
 374 };
 375
 376 /* External SRAM */
 377 static struct resource zeus_sram_resource = {
 378         .start          = ZEUS_SRAM_PHYS,
 379         .end            = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
 380         .flags          = IORESOURCE_MEM,
 381 };
 382
 383 static struct platform_device zeus_sram_device = {
 384         .name           = "pxa2xx-8bit-sram",
 385         .id             = 0,
 386         .num_resources  = 1,
 387         .resource       = &zeus_sram_resource,
 388 };
 389
 390 /* SPI interface on SSP3 */
 391 static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
 392         .num_chipselect = 1,
 393         .enable_dma     = 1,
 394 };
 395
 396 /* CAN bus on SPI */
 397 static struct regulator_consumer_supply can_regulator_consumer =
 398         REGULATOR_SUPPLY("vdd", "spi3.0");
 399
 400 static struct regulator_init_data can_regulator_init_data = {
 401         .constraints    = {
 402                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 403         },
 404         .consumer_supplies      = &can_regulator_consumer,
 405         .num_consumer_supplies  = 1,
 406 };
 407
 408 static struct fixed_voltage_config can_regulator_pdata = {
 409         .supply_name    = "CAN_SHDN",
 410         .microvolts     = 3300000,
 411         .gpio           = ZEUS_CAN_SHDN_GPIO,
 412         .init_data      = &can_regulator_init_data,
 413 };
 414
 415 static struct platform_device can_regulator_device = {
 416         .name   = "reg-fixed-voltage",
 417         .id     = 0,
 418         .dev    = {
 419                 .platform_data  = &can_regulator_pdata,
 420         },
 421 };
 422
 423 static struct mcp251x_platform_data zeus_mcp2515_pdata = {
 424         .oscillator_frequency   = 16*1000*1000,
 425 };
 426
 427 static struct spi_board_info zeus_spi_board_info[] = {
 428         [0] = {
 429                 .modalias       = "mcp2515",
 430                 .platform_data  = &zeus_mcp2515_pdata,
 431                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
 432                 .max_speed_hz   = 1*1000*1000,
 433                 .bus_num        = 3,
 434                 .mode           = SPI_MODE_0,
 435                 .chip_select    = 0,
 436         },
 437 };
 438
 439 /* Leds */
 440 static struct gpio_led zeus_leds[] = {
 441         [0] = {
 442                 .name            = "zeus:yellow:1",
 443                 .default_trigger = "heartbeat",
 444                 .gpio            = ZEUS_EXT0_GPIO(3),
 445                 .active_low      = 1,
 446         },
 447         [1] = {
 448                 .name            = "zeus:yellow:2",
 449                 .default_trigger = "default-on",
 450                 .gpio            = ZEUS_EXT0_GPIO(4),
 451                 .active_low      = 1,
 452         },
 453         [2] = {
 454                 .name            = "zeus:yellow:3",
 455                 .default_trigger = "default-on",
 456                 .gpio            = ZEUS_EXT0_GPIO(5),
 457                 .active_low      = 1,
 458         },
 459 };
 460
 461 static struct gpio_led_platform_data zeus_leds_info = {
 462         .leds           = zeus_leds,
 463         .num_leds       = ARRAY_SIZE(zeus_leds),
 464 };
 465
 466 static struct platform_device zeus_leds_device = {
 467         .name           = "leds-gpio",
 468         .id             = -1,
 469         .dev            = {
 470                 .platform_data  = &zeus_leds_info,
 471         },
 472 };
 473
 474 static void zeus_cf_reset(int state)
 475 {
 476         u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
 477
 478         if (state)
 479                 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
 480         else
 481                 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
 482
 483         __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
 484 }
 485
 486 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
 487         .cd_gpio        = ZEUS_CF_CD_GPIO,
 488         .rdy_gpio       = ZEUS_CF_RDY_GPIO,
 489         .pwr_gpio       = ZEUS_CF_PWEN_GPIO,
 490         .reset          = zeus_cf_reset,
 491 };
 492
 493 static struct platform_device zeus_pcmcia_device = {
 494         .name           = "zeus-pcmcia",
 495         .id             = -1,
 496         .dev            = {
 497                 .platform_data  = &zeus_pcmcia_info,
 498         },
 499 };
 500
 501 static struct resource zeus_max6369_resource = {
 502         .start          = ZEUS_CPLD_EXTWDOG_PHYS,
 503         .end            = ZEUS_CPLD_EXTWDOG_PHYS,
 504         .flags          = IORESOURCE_MEM,
 505 };
 506
 507 struct platform_device zeus_max6369_device = {
 508         .name           = "max6369_wdt",
 509         .id             = -1,
 510         .resource       = &zeus_max6369_resource,
 511         .num_resources  = 1,
 512 };
 513
 514 /* AC'97 */
 515 static pxa2xx_audio_ops_t zeus_ac97_info = {
 516         .reset_gpio = 95,
 517 };
 518
 519
 520 /*
 521  * USB host
 522  */
 523
 524 static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
 525         REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
 526 };
 527
 528 static struct regulator_init_data zeus_ohci_regulator_data = {
 529         .constraints = {
 530                 .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
 531         },
 532         .num_consumer_supplies  = ARRAY_SIZE(zeus_ohci_regulator_supplies),
 533         .consumer_supplies      = zeus_ohci_regulator_supplies,
 534 };
 535
 536 static struct fixed_voltage_config zeus_ohci_regulator_config = {
 537         .supply_name            = "vbus2",
 538         .microvolts             = 5000000, /* 5.0V */
 539         .gpio                   = ZEUS_USB2_PWREN_GPIO,
 540         .enable_high            = 1,
 541         .startup_delay          = 0,
 542         .init_data              = &zeus_ohci_regulator_data,
 543 };
 544
 545 static struct platform_device zeus_ohci_regulator_device = {
 546         .name           = "reg-fixed-voltage",
 547         .id             = 1,
 548         .dev = {
 549                 .platform_data = &zeus_ohci_regulator_config,
 550         },
 551 };
 552
 553 static struct pxaohci_platform_data zeus_ohci_platform_data = {
 554         .port_mode      = PMM_NPS_MODE,
 555         /* Clear Power Control Polarity Low and set Power Sense
 556          * Polarity Low. Supply power to USB ports. */
 557         .flags          = ENABLE_PORT_ALL | POWER_SENSE_LOW,
 558 };
 559
 560 static void zeus_register_ohci(void)
 561 {
 562         /* Port 2 is shared between host and client interface. */
 563         UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
 564
 565         pxa_set_ohci_info(&zeus_ohci_platform_data);
 566 }
 567
 568 /*
 569  * Flat Panel
 570  */
 571
 572 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
 573 {
 574         gpio_set_value(ZEUS_LCD_EN_GPIO, on);
 575 }
 576
 577 static void zeus_backlight_power(int on)
 578 {
 579         gpio_set_value(ZEUS_BKLEN_GPIO, on);
 580 }
 581
 582 static int zeus_setup_fb_gpios(void)
 583 {
 584         int err;
 585
 586         if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
 587                 goto out_err;
 588
 589         if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
 590                 goto out_err_lcd;
 591
 592         if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
 593                 goto out_err_lcd;
 594
 595         if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
 596                 goto out_err_bkl;
 597
 598         return 0;
 599
 600 out_err_bkl:
 601         gpio_free(ZEUS_BKLEN_GPIO);
 602 out_err_lcd:
 603         gpio_free(ZEUS_LCD_EN_GPIO);
 604 out_err:
 605         return err;
 606 }
 607
 608 static struct pxafb_mode_info zeus_fb_mode_info[] = {
 609         {
 610                 .pixclock       = 39722,
 611
 612                 .xres           = 640,
 613                 .yres           = 480,
 614
 615                 .bpp            = 16,
 616
 617                 .hsync_len      = 63,
 618                 .left_margin    = 16,
 619                 .right_margin   = 81,
 620
 621                 .vsync_len      = 2,
 622                 .upper_margin   = 12,
 623                 .lower_margin   = 31,
 624
 625                 .sync           = 0,
 626         },
 627 };
 628
 629 static struct pxafb_mach_info zeus_fb_info = {
 630         .modes                  = zeus_fb_mode_info,
 631         .num_modes              = 1,
 632         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
 633         .pxafb_lcd_power        = zeus_lcd_power,
 634         .pxafb_backlight_power  = zeus_backlight_power,
 635 };
 636
 637 /*
 638  * MMC/SD Device
 639  *
 640  * The card detect interrupt isn't debounced so we delay it by 250ms
 641  * to give the card a chance to fully insert/eject.
 642  */
 643
 644 static struct pxamci_platform_data zeus_mci_platform_data = {
 645         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
 646         .detect_delay_ms        = 250,
 647         .gpio_card_detect       = ZEUS_MMC_CD_GPIO,
 648         .gpio_card_ro           = ZEUS_MMC_WP_GPIO,
 649         .gpio_card_ro_invert    = 1,
 650         .gpio_power             = -1
 651 };
 652
 653 /*
 654  * USB Device Controller
 655  */
 656 static void zeus_udc_command(int cmd)
 657 {
 658         switch (cmd) {
 659         case PXA2XX_UDC_CMD_DISCONNECT:
 660                 pr_info("zeus: disconnecting USB client\n");
 661                 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
 662                 break;
 663
 664         case PXA2XX_UDC_CMD_CONNECT:
 665                 pr_info("zeus: connecting USB client\n");
 666                 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
 667                 break;
 668         }
 669 }
 670
 671 static struct pxa2xx_udc_mach_info zeus_udc_info = {
 672         .udc_command = zeus_udc_command,
 673 };
 674
 675 static struct platform_device *zeus_devices[] __initdata = {
 676         &zeus_serial_device,
 677         &zeus_mtd_devices[0],
 678         &zeus_dm9k0_device,
 679         &zeus_dm9k1_device,
 680         &zeus_sram_device,
 681         &zeus_leds_device,
 682         &zeus_pcmcia_device,
 683         &zeus_max6369_device,
 684         &can_regulator_device,
 685         &zeus_ohci_regulator_device,
 686 };
 687
 688 #ifdef CONFIG_PM
 689 static void zeus_power_off(void)
 690 {
 691         local_irq_disable();
 692         cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
 693 }
 694 #else
 695 #define zeus_power_off   NULL
 696 #endif
 697
 698 #ifdef CONFIG_APM_EMULATION
 699 static void zeus_get_power_status(struct apm_power_info *info)
 700 {
 701         /* Power supply is always present */
 702         info->ac_line_status    = APM_AC_ONLINE;
 703         info->battery_status    = APM_BATTERY_STATUS_NOT_PRESENT;
 704         info->battery_flag      = APM_BATTERY_FLAG_NOT_PRESENT;
 705 }
 706
 707 static inline void zeus_setup_apm(void)
 708 {
 709         apm_get_power_status = zeus_get_power_status;
 710 }
 711 #else
 712 static inline void zeus_setup_apm(void)
 713 {
 714 }
 715 #endif
 716
 717 static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
 718                              unsigned ngpio, void *context)
 719 {
 720         int i;
 721         u8 pcb_info = 0;
 722
 723         for (i = 0; i < 8; i++) {
 724                 int pcb_bit = gpio + i + 8;
 725
 726                 if (gpio_request(pcb_bit, "pcb info")) {
 727                         dev_err(&client->dev, "Can't request pcb info %d\n", i);
 728                         continue;
 729                 }
 730
 731                 if (gpio_direction_input(pcb_bit)) {
 732                         dev_err(&client->dev, "Can't read pcb info %d\n", i);
 733                         gpio_free(pcb_bit);
 734                         continue;
 735                 }
 736
 737                 pcb_info |= !!gpio_get_value(pcb_bit) << i;
 738
 739                 gpio_free(pcb_bit);
 740         }
 741
 742         dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
 743                  pcb_info >> 4, pcb_info & 0xf);
 744
 745         return 0;
 746 }
 747
 748 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
 749         [0] = { .gpio_base      = ZEUS_EXT0_GPIO_BASE, },
 750         [1] = {
 751                 .gpio_base      = ZEUS_EXT1_GPIO_BASE,
 752                 .setup          = zeus_get_pcb_info,
 753         },
 754         [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
 755 };
 756
 757 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
 758         {
 759                 I2C_BOARD_INFO("pca9535",       0x21),
 760                 .platform_data  = &zeus_pca953x_pdata[0],
 761         },
 762         {
 763                 I2C_BOARD_INFO("pca9535",       0x22),
 764                 .platform_data  = &zeus_pca953x_pdata[1],
 765         },
 766         {
 767                 I2C_BOARD_INFO("pca9535",       0x20),
 768                 .platform_data  = &zeus_pca953x_pdata[2],
 769                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
 770         },
 771         { I2C_BOARD_INFO("lm75a",       0x48) },
 772         { I2C_BOARD_INFO("24c01",       0x50) },
 773         { I2C_BOARD_INFO("isl1208",     0x6f) },
 774 };
 775
 776 static mfp_cfg_t zeus_pin_config[] __initdata = {
 777         /* AC97 */
 778         GPIO28_AC97_BITCLK,
 779         GPIO29_AC97_SDATA_IN_0,
 780         GPIO30_AC97_SDATA_OUT,
 781         GPIO31_AC97_SYNC,
 782
 783         GPIO15_nCS_1,
 784         GPIO78_nCS_2,
 785         GPIO80_nCS_4,
 786         GPIO33_nCS_5,
 787
 788         GPIO22_GPIO,
 789         GPIO32_MMC_CLK,
 790         GPIO92_MMC_DAT_0,
 791         GPIO109_MMC_DAT_1,
 792         GPIO110_MMC_DAT_2,
 793         GPIO111_MMC_DAT_3,
 794         GPIO112_MMC_CMD,
 795
 796         GPIO88_USBH1_PWR,
 797         GPIO89_USBH1_PEN,
 798         GPIO119_USBH2_PWR,
 799         GPIO120_USBH2_PEN,
 800
 801         GPIO86_LCD_LDD_16,
 802         GPIO87_LCD_LDD_17,
 803
 804         GPIO102_GPIO,
 805         GPIO104_CIF_DD_2,
 806         GPIO105_CIF_DD_1,
 807
 808         GPIO81_SSP3_TXD,
 809         GPIO82_SSP3_RXD,
 810         GPIO83_SSP3_SFRM,
 811         GPIO84_SSP3_SCLK,
 812
 813         GPIO48_nPOE,
 814         GPIO49_nPWE,
 815         GPIO50_nPIOR,
 816         GPIO51_nPIOW,
 817         GPIO85_nPCE_1,
 818         GPIO54_nPCE_2,
 819         GPIO79_PSKTSEL,
 820         GPIO55_nPREG,
 821         GPIO56_nPWAIT,
 822         GPIO57_nIOIS16,
 823         GPIO36_GPIO,            /* CF CD */
 824         GPIO97_GPIO,            /* CF PWREN */
 825         GPIO99_GPIO,            /* CF RDY */
 826 };
 827
 828 /*
 829  * DM9k MSCx settings:  SRAM, 16 bits
 830  *                      17 cycles delay first access
 831  *                       5 cycles delay next access
 832  *                      13 cycles recovery time
 833  *                      faster device
 834  */
 835 #define DM9K_MSC_VALUE          0xe4c9
 836
 837 static void __init zeus_init(void)
 838 {
 839         u16 dm9000_msc = DM9K_MSC_VALUE;
 840         u32 msc0, msc1;
 841
 842         system_rev = __raw_readw(ZEUS_CPLD_VERSION);
 843         pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
 844
 845         /* Fix timings for dm9000s (CS1/CS2)*/
 846         msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
 847         msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
 848         __raw_writel(msc0, MSC0);
 849         __raw_writel(msc1, MSC1);
 850
 851         pm_power_off = zeus_power_off;
 852         zeus_setup_apm();
 853
 854         pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
 855
 856         platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
 857
 858         zeus_register_ohci();
 859
 860         if (zeus_setup_fb_gpios())
 861                 pr_err("Failed to setup fb gpios\n");
 862         else
 863                 pxa_set_fb_info(NULL, &zeus_fb_info);
 864
 865         pxa_set_mci_info(&zeus_mci_platform_data);
 866         pxa_set_udc_info(&zeus_udc_info);
 867         pxa_set_ac97_info(&zeus_ac97_info);
 868         pxa_set_i2c_info(NULL);
 869         i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
 870         pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
 871         spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
 872
 873         regulator_has_full_constraints();
 874 }
 875
 876 static struct map_desc zeus_io_desc[] __initdata = {
 877         {
 878                 .virtual = (unsigned long)ZEUS_CPLD_VERSION,
 879                 .pfn     = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
 880                 .length  = 0x1000,
 881                 .type    = MT_DEVICE,
 882         },
 883         {
 884                 .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
 885                 .pfn     = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
 886                 .length  = 0x1000,
 887                 .type    = MT_DEVICE,
 888         },
 889         {
 890                 .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
 891                 .pfn     = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
 892                 .length  = 0x1000,
 893                 .type    = MT_DEVICE,
 894         },
 895         {
 896                 .virtual = (unsigned long)ZEUS_PC104IO,
 897                 .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
 898                 .length  = 0x00800000,
 899                 .type    = MT_DEVICE,
 900         },
 901 };
 902
 903 static void __init zeus_map_io(void)
 904 {
 905         pxa27x_map_io();
 906
 907         iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
 908
 909         /* Clear PSPR to ensure a full restart on wake-up. */
 910         PMCR = PSPR = 0;
 911
 912         /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
 913         OSCC |= OSCC_OON;
 914
 915         /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
 916          * float chip selects and PCMCIA */
 917         PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
 918 }
 919
 920 MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
 921         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
 922         .atag_offset    = 0x100,
 923         .map_io         = zeus_map_io,
 924         .nr_irqs        = ZEUS_NR_IRQS,
 925         .init_irq       = zeus_init_irq,
 926         .handle_irq     = pxa27x_handle_irq,
 927         .init_time      = pxa_timer_init,
 928         .init_machine   = zeus_init,
 929         .restart        = pxa_restart,
 930 MACHINE_END
 931