arch/arm/mm/alignment.c

   1 /*
   2  *  linux/arch/arm/mm/alignment.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Modifications for ARM processor (c) 1995-2001 Russell King
   6  *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
   7  *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
   8  *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/moduleparam.h>
  15 #include <linux/compiler.h>
  16 #include <linux/kernel.h>
  17 #include <linux/errno.h>
  18 #include <linux/string.h>
  19 #include <linux/proc_fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/init.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24
  25 #include <asm/cp15.h>
  26 #include <asm/system_info.h>
  27 #include <asm/unaligned.h>
  28 #include <asm/opcodes.h>
  29
  30 #include "fault.h"
  31 #include "mm.h"
  32
  33 /*
  34  * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
  35  * /proc/sys/debug/alignment, modified and integrated into
  36  * Linux 2.1 by Russell King
  37  *
  38  * Speed optimisations and better fault handling by Russell King.
  39  *
  40  * *** NOTE ***
  41  * This code is not portable to processors with late data abort handling.
  42  */
  43 #define CODING_BITS(i)  (i & 0x0e000000)
  44 #define COND_BITS(i)    (i & 0xf0000000)
  45
  46 #define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
  47 #define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
  48 #define LDST_U_BIT(i)   (i & (1 << 23))         /* Add offset           */
  49 #define LDST_W_BIT(i)   (i & (1 << 21))         /* Writeback            */
  50 #define LDST_L_BIT(i)   (i & (1 << 20))         /* Load                 */
  51
  52 #define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
  53
  54 #define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
  55 #define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
  56
  57 #define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
  58 #define RD_BITS(i)      ((i >> 12) & 15)        /* Rd                   */
  59 #define RM_BITS(i)      (i & 15)                /* Rm                   */
  60
  61 #define REGMASK_BITS(i) (i & 0xffff)
  62 #define OFFSET_BITS(i)  (i & 0x0fff)
  63
  64 #define IS_SHIFT(i)     (i & 0x0ff0)
  65 #define SHIFT_BITS(i)   ((i >> 7) & 0x1f)
  66 #define SHIFT_TYPE(i)   (i & 0x60)
  67 #define SHIFT_LSL       0x00
  68 #define SHIFT_LSR       0x20
  69 #define SHIFT_ASR       0x40
  70 #define SHIFT_RORRRX    0x60
  71
  72 #define BAD_INSTR       0xdeadc0de
  73
  74 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
  75 #define IS_T32(hi16) \
  76         (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
  77
  78 static unsigned long ai_user;
  79 static unsigned long ai_sys;
  80 static void *ai_sys_last_pc;
  81 static unsigned long ai_skipped;
  82 static unsigned long ai_half;
  83 static unsigned long ai_word;
  84 static unsigned long ai_dword;
  85 static unsigned long ai_multi;
  86 static int ai_usermode;
  87 static unsigned long cr_no_alignment;
  88
  89 core_param(alignment, ai_usermode, int, 0600);
  90
  91 #define UM_WARN         (1 << 0)
  92 #define UM_FIXUP        (1 << 1)
  93 #define UM_SIGNAL       (1 << 2)
  94
  95 /* Return true if and only if the ARMv6 unaligned access model is in use. */
  96 static bool cpu_is_v6_unaligned(void)
  97 {
  98         return cpu_architecture() >= CPU_ARCH_ARMv6 && get_cr() & CR_U;
  99 }
 100
 101 static int safe_usermode(int new_usermode, bool warn)
 102 {
 103         /*
 104          * ARMv6 and later CPUs can perform unaligned accesses for
 105          * most single load and store instructions up to word size.
 106          * LDM, STM, LDRD and STRD still need to be handled.
 107          *
 108          * Ignoring the alignment fault is not an option on these
 109          * CPUs since we spin re-faulting the instruction without
 110          * making any progress.
 111          */
 112         if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
 113                 new_usermode |= UM_FIXUP;
 114
 115                 if (warn)
 116                         pr_warn("alignment: ignoring faults is unsafe on this CPU.  Defaulting to fixup mode.\n");
 117         }
 118
 119         return new_usermode;
 120 }
 121
 122 #ifdef CONFIG_PROC_FS
 123 static const char *usermode_action[] = {
 124         "ignored",
 125         "warn",
 126         "fixup",
 127         "fixup+warn",
 128         "signal",
 129         "signal+warn"
 130 };
 131
 132 static int alignment_proc_show(struct seq_file *m, void *v)
 133 {
 134         seq_printf(m, "User:\t\t%lu\n", ai_user);
 135         seq_printf(m, "System:\t\t%lu (%pF)\n", ai_sys, ai_sys_last_pc);
 136         seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
 137         seq_printf(m, "Half:\t\t%lu\n", ai_half);
 138         seq_printf(m, "Word:\t\t%lu\n", ai_word);
 139         if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
 140                 seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
 141         seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
 142         seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
 143                         usermode_action[ai_usermode]);
 144
 145         return 0;
 146 }
 147
 148 static int alignment_proc_open(struct inode *inode, struct file *file)
 149 {
 150         return single_open(file, alignment_proc_show, NULL);
 151 }
 152
 153 static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
 154                                     size_t count, loff_t *pos)
 155 {
 156         char mode;
 157
 158         if (count > 0) {
 159                 if (get_user(mode, buffer))
 160                         return -EFAULT;
 161                 if (mode >= '0' && mode <= '5')
 162                         ai_usermode = safe_usermode(mode - '0', true);
 163         }
 164         return count;
 165 }
 166
 167 static const struct file_operations alignment_proc_fops = {
 168         .open           = alignment_proc_open,
 169         .read           = seq_read,
 170         .llseek         = seq_lseek,
 171         .release        = single_release,
 172         .write          = alignment_proc_write,
 173 };
 174 #endif /* CONFIG_PROC_FS */
 175
 176 union offset_union {
 177         unsigned long un;
 178           signed long sn;
 179 };
 180
 181 #define TYPE_ERROR      0
 182 #define TYPE_FAULT      1
 183 #define TYPE_LDST       2
 184 #define TYPE_DONE       3
 185
 186 #ifdef __ARMEB__
 187 #define BE              1
 188 #define FIRST_BYTE_16   "mov    %1, %1, ror #8\n"
 189 #define FIRST_BYTE_32   "mov    %1, %1, ror #24\n"
 190 #define NEXT_BYTE       "ror #24"
 191 #else
 192 #define BE              0
 193 #define FIRST_BYTE_16
 194 #define FIRST_BYTE_32
 195 #define NEXT_BYTE       "lsr #8"
 196 #endif
 197
 198 #define __get8_unaligned_check(ins,val,addr,err)        \
 199         __asm__(                                        \
 200  ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 201  THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 202  THUMB( "       add     %2, %2, #1\n"   )               \
 203         "2:\n"                                          \
 204         "       .pushsection .text.fixup,\"ax\"\n"      \
 205         "       .align  2\n"                            \
 206         "3:     mov     %0, #1\n"                       \
 207         "       b       2b\n"                           \
 208         "       .popsection\n"                          \
 209         "       .pushsection __ex_table,\"a\"\n"        \
 210         "       .align  3\n"                            \
 211         "       .long   1b, 3b\n"                       \
 212         "       .popsection\n"                          \
 213         : "=r" (err), "=&r" (val), "=r" (addr)          \
 214         : "0" (err), "2" (addr))
 215
 216 #define __get16_unaligned_check(ins,val,addr)                   \
 217         do {                                                    \
 218                 unsigned int err = 0, v, a = addr;              \
 219                 __get8_unaligned_check(ins,v,a,err);            \
 220                 val =  v << ((BE) ? 8 : 0);                     \
 221                 __get8_unaligned_check(ins,v,a,err);            \
 222                 val |= v << ((BE) ? 0 : 8);                     \
 223                 if (err)                                        \
 224                         goto fault;                             \
 225         } while (0)
 226
 227 #define get16_unaligned_check(val,addr) \
 228         __get16_unaligned_check("ldrb",val,addr)
 229
 230 #define get16t_unaligned_check(val,addr) \
 231         __get16_unaligned_check("ldrbt",val,addr)
 232
 233 #define __get32_unaligned_check(ins,val,addr)                   \
 234         do {                                                    \
 235                 unsigned int err = 0, v, a = addr;              \
 236                 __get8_unaligned_check(ins,v,a,err);            \
 237                 val =  v << ((BE) ? 24 :  0);                   \
 238                 __get8_unaligned_check(ins,v,a,err);            \
 239                 val |= v << ((BE) ? 16 :  8);                   \
 240                 __get8_unaligned_check(ins,v,a,err);            \
 241                 val |= v << ((BE) ?  8 : 16);                   \
 242                 __get8_unaligned_check(ins,v,a,err);            \
 243                 val |= v << ((BE) ?  0 : 24);                   \
 244                 if (err)                                        \
 245                         goto fault;                             \
 246         } while (0)
 247
 248 #define get32_unaligned_check(val,addr) \
 249         __get32_unaligned_check("ldrb",val,addr)
 250
 251 #define get32t_unaligned_check(val,addr) \
 252         __get32_unaligned_check("ldrbt",val,addr)
 253
 254 #define __put16_unaligned_check(ins,val,addr)                   \
 255         do {                                                    \
 256                 unsigned int err = 0, v = val, a = addr;        \
 257                 __asm__( FIRST_BYTE_16                          \
 258          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 259          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 260          THUMB( "       add     %2, %2, #1\n"   )               \
 261                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 262                 "2:     "ins"   %1, [%2]\n"                     \
 263                 "3:\n"                                          \
 264                 "       .pushsection .text.fixup,\"ax\"\n"      \
 265                 "       .align  2\n"                            \
 266                 "4:     mov     %0, #1\n"                       \
 267                 "       b       3b\n"                           \
 268                 "       .popsection\n"                          \
 269                 "       .pushsection __ex_table,\"a\"\n"        \
 270                 "       .align  3\n"                            \
 271                 "       .long   1b, 4b\n"                       \
 272                 "       .long   2b, 4b\n"                       \
 273                 "       .popsection\n"                          \
 274                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 275                 : "0" (err), "1" (v), "2" (a));                 \
 276                 if (err)                                        \
 277                         goto fault;                             \
 278         } while (0)
 279
 280 #define put16_unaligned_check(val,addr)  \
 281         __put16_unaligned_check("strb",val,addr)
 282
 283 #define put16t_unaligned_check(val,addr) \
 284         __put16_unaligned_check("strbt",val,addr)
 285
 286 #define __put32_unaligned_check(ins,val,addr)                   \
 287         do {                                                    \
 288                 unsigned int err = 0, v = val, a = addr;        \
 289                 __asm__( FIRST_BYTE_32                          \
 290          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 291          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 292          THUMB( "       add     %2, %2, #1\n"   )               \
 293                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 294          ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
 295          THUMB( "2:     "ins"   %1, [%2]\n"     )               \
 296          THUMB( "       add     %2, %2, #1\n"   )               \
 297                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 298          ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
 299          THUMB( "3:     "ins"   %1, [%2]\n"     )               \
 300          THUMB( "       add     %2, %2, #1\n"   )               \
 301                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 302                 "4:     "ins"   %1, [%2]\n"                     \
 303                 "5:\n"                                          \
 304                 "       .pushsection .text.fixup,\"ax\"\n"      \
 305                 "       .align  2\n"                            \
 306                 "6:     mov     %0, #1\n"                       \
 307                 "       b       5b\n"                           \
 308                 "       .popsection\n"                          \
 309                 "       .pushsection __ex_table,\"a\"\n"        \
 310                 "       .align  3\n"                            \
 311                 "       .long   1b, 6b\n"                       \
 312                 "       .long   2b, 6b\n"                       \
 313                 "       .long   3b, 6b\n"                       \
 314                 "       .long   4b, 6b\n"                       \
 315                 "       .popsection\n"                          \
 316                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 317                 : "0" (err), "1" (v), "2" (a));                 \
 318                 if (err)                                        \
 319                         goto fault;                             \
 320         } while (0)
 321
 322 #define put32_unaligned_check(val,addr) \
 323         __put32_unaligned_check("strb", val, addr)
 324
 325 #define put32t_unaligned_check(val,addr) \
 326         __put32_unaligned_check("strbt", val, addr)
 327
 328 static void
 329 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
 330 {
 331         if (!LDST_U_BIT(instr))
 332                 offset.un = -offset.un;
 333
 334         if (!LDST_P_BIT(instr))
 335                 addr += offset.un;
 336
 337         if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
 338                 regs->uregs[RN_BITS(instr)] = addr;
 339 }
 340
 341 static int
 342 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 343 {
 344         unsigned int rd = RD_BITS(instr);
 345
 346         ai_half += 1;
 347
 348         if (user_mode(regs))
 349                 goto user;
 350
 351         if (LDST_L_BIT(instr)) {
 352                 unsigned long val;
 353                 get16_unaligned_check(val, addr);
 354
 355                 /* signed half-word? */
 356                 if (instr & 0x40)
 357                         val = (signed long)((signed short) val);
 358
 359                 regs->uregs[rd] = val;
 360         } else
 361                 put16_unaligned_check(regs->uregs[rd], addr);
 362
 363         return TYPE_LDST;
 364
 365  user:
 366         if (LDST_L_BIT(instr)) {
 367                 unsigned long val;
 368                 get16t_unaligned_check(val, addr);
 369
 370                 /* signed half-word? */
 371                 if (instr & 0x40)
 372                         val = (signed long)((signed short) val);
 373
 374                 regs->uregs[rd] = val;
 375         } else
 376                 put16t_unaligned_check(regs->uregs[rd], addr);
 377
 378         return TYPE_LDST;
 379
 380  fault:
 381         return TYPE_FAULT;
 382 }
 383
 384 static int
 385 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
 386                       struct pt_regs *regs)
 387 {
 388         unsigned int rd = RD_BITS(instr);
 389         unsigned int rd2;
 390         int load;
 391
 392         if ((instr & 0xfe000000) == 0xe8000000) {
 393                 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
 394                 rd2 = (instr >> 8) & 0xf;
 395                 load = !!(LDST_L_BIT(instr));
 396         } else if (((rd & 1) == 1) || (rd == 14))
 397                 goto bad;
 398         else {
 399                 load = ((instr & 0xf0) == 0xd0);
 400                 rd2 = rd + 1;
 401         }
 402
 403         ai_dword += 1;
 404
 405         if (user_mode(regs))
 406                 goto user;
 407
 408         if (load) {
 409                 unsigned long val;
 410                 get32_unaligned_check(val, addr);
 411                 regs->uregs[rd] = val;
 412                 get32_unaligned_check(val, addr + 4);
 413                 regs->uregs[rd2] = val;
 414         } else {
 415                 put32_unaligned_check(regs->uregs[rd], addr);
 416                 put32_unaligned_check(regs->uregs[rd2], addr + 4);
 417         }
 418
 419         return TYPE_LDST;
 420
 421  user:
 422         if (load) {
 423                 unsigned long val;
 424                 get32t_unaligned_check(val, addr);
 425                 regs->uregs[rd] = val;
 426                 get32t_unaligned_check(val, addr + 4);
 427                 regs->uregs[rd2] = val;
 428         } else {
 429                 put32t_unaligned_check(regs->uregs[rd], addr);
 430                 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
 431         }
 432
 433         return TYPE_LDST;
 434  bad:
 435         return TYPE_ERROR;
 436  fault:
 437         return TYPE_FAULT;
 438 }
 439
 440 static int
 441 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 442 {
 443         unsigned int rd = RD_BITS(instr);
 444
 445         ai_word += 1;
 446
 447         if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
 448                 goto trans;
 449
 450         if (LDST_L_BIT(instr)) {
 451                 unsigned int val;
 452                 get32_unaligned_check(val, addr);
 453                 regs->uregs[rd] = val;
 454         } else
 455                 put32_unaligned_check(regs->uregs[rd], addr);
 456         return TYPE_LDST;
 457
 458  trans:
 459         if (LDST_L_BIT(instr)) {
 460                 unsigned int val;
 461                 get32t_unaligned_check(val, addr);
 462                 regs->uregs[rd] = val;
 463         } else
 464                 put32t_unaligned_check(regs->uregs[rd], addr);
 465         return TYPE_LDST;
 466
 467  fault:
 468         return TYPE_FAULT;
 469 }
 470
 471 /*
 472  * LDM/STM alignment handler.
 473  *
 474  * There are 4 variants of this instruction:
 475  *
 476  * B = rn pointer before instruction, A = rn pointer after instruction
 477  *              ------ increasing address ----->
 478  *              |    | r0 | r1 | ... | rx |    |
 479  * PU = 01             B                    A
 480  * PU = 11        B                    A
 481  * PU = 00        A                    B
 482  * PU = 10             A                    B
 483  */
 484 static int
 485 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 486 {
 487         unsigned int rd, rn, correction, nr_regs, regbits;
 488         unsigned long eaddr, newaddr;
 489
 490         if (LDM_S_BIT(instr))
 491                 goto bad;
 492
 493         correction = 4; /* processor implementation defined */
 494         regs->ARM_pc += correction;
 495
 496         ai_multi += 1;
 497
 498         /* count the number of registers in the mask to be transferred */
 499         nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
 500
 501         rn = RN_BITS(instr);
 502         newaddr = eaddr = regs->uregs[rn];
 503
 504         if (!LDST_U_BIT(instr))
 505                 nr_regs = -nr_regs;
 506         newaddr += nr_regs;
 507         if (!LDST_U_BIT(instr))
 508                 eaddr = newaddr;
 509
 510         if (LDST_P_EQ_U(instr)) /* U = P */
 511                 eaddr += 4;
 512
 513         /*
 514          * For alignment faults on the ARM922T/ARM920T the MMU  makes
 515          * the FSR (and hence addr) equal to the updated base address
 516          * of the multiple access rather than the restored value.
 517          * Switch this message off if we've got a ARM92[02], otherwise
 518          * [ls]dm alignment faults are noisy!
 519          */
 520 #if !(defined CONFIG_CPU_ARM922T)  && !(defined CONFIG_CPU_ARM920T)
 521         /*
 522          * This is a "hint" - we already have eaddr worked out by the
 523          * processor for us.
 524          */
 525         if (addr != eaddr) {
 526                 pr_err("LDMSTM: PC = %08lx, instr = %08lx, "
 527                         "addr = %08lx, eaddr = %08lx\n",
 528                          instruction_pointer(regs), instr, addr, eaddr);
 529                 show_regs(regs);
 530         }
 531 #endif
 532
 533         if (user_mode(regs)) {
 534                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 535                      regbits >>= 1, rd += 1)
 536                         if (regbits & 1) {
 537                                 if (LDST_L_BIT(instr)) {
 538                                         unsigned int val;
 539                                         get32t_unaligned_check(val, eaddr);
 540                                         regs->uregs[rd] = val;
 541                                 } else
 542                                         put32t_unaligned_check(regs->uregs[rd], eaddr);
 543                                 eaddr += 4;
 544                         }
 545         } else {
 546                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 547                      regbits >>= 1, rd += 1)
 548                         if (regbits & 1) {
 549                                 if (LDST_L_BIT(instr)) {
 550                                         unsigned int val;
 551                                         get32_unaligned_check(val, eaddr);
 552                                         regs->uregs[rd] = val;
 553                                 } else
 554                                         put32_unaligned_check(regs->uregs[rd], eaddr);
 555                                 eaddr += 4;
 556                         }
 557         }
 558
 559         if (LDST_W_BIT(instr))
 560                 regs->uregs[rn] = newaddr;
 561         if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
 562                 regs->ARM_pc -= correction;
 563         return TYPE_DONE;
 564
 565 fault:
 566         regs->ARM_pc -= correction;
 567         return TYPE_FAULT;
 568
 569 bad:
 570         pr_err("Alignment trap: not handling ldm with s-bit set\n");
 571         return TYPE_ERROR;
 572 }
 573
 574 /*
 575  * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
 576  * we can reuse ARM userland alignment fault fixups for Thumb.
 577  *
 578  * This implementation was initially based on the algorithm found in
 579  * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
 580  * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
 581  *
 582  * NOTES:
 583  * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
 584  * 2. If for some reason we're passed an non-ld/st Thumb instruction to
 585  *    decode, we return 0xdeadc0de. This should never happen under normal
 586  *    circumstances but if it does, we've got other problems to deal with
 587  *    elsewhere and we obviously can't fix those problems here.
 588  */
 589
 590 static unsigned long
 591 thumb2arm(u16 tinstr)
 592 {
 593         u32 L = (tinstr & (1<<11)) >> 11;
 594
 595         switch ((tinstr & 0xf800) >> 11) {
 596         /* 6.5.1 Format 1: */
 597         case 0x6000 >> 11:                              /* 7.1.52 STR(1) */
 598         case 0x6800 >> 11:                              /* 7.1.26 LDR(1) */
 599         case 0x7000 >> 11:                              /* 7.1.55 STRB(1) */
 600         case 0x7800 >> 11:                              /* 7.1.30 LDRB(1) */
 601                 return 0xe5800000 |
 602                         ((tinstr & (1<<12)) << (22-12)) |       /* fixup */
 603                         (L<<20) |                               /* L==1? */
 604                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 605                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 606                         ((tinstr & (31<<6)) >>                  /* immed_5 */
 607                                 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
 608         case 0x8000 >> 11:                              /* 7.1.57 STRH(1) */
 609         case 0x8800 >> 11:                              /* 7.1.32 LDRH(1) */
 610                 return 0xe1c000b0 |
 611                         (L<<20) |                               /* L==1? */
 612                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 613                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 614                         ((tinstr & (7<<6)) >> (6-1)) |   /* immed_5[2:0] */
 615                         ((tinstr & (3<<9)) >> (9-8));    /* immed_5[4:3] */
 616
 617         /* 6.5.1 Format 2: */
 618         case 0x5000 >> 11:
 619         case 0x5800 >> 11:
 620                 {
 621                         static const u32 subset[8] = {
 622                                 0xe7800000,             /* 7.1.53 STR(2) */
 623                                 0xe18000b0,             /* 7.1.58 STRH(2) */
 624                                 0xe7c00000,             /* 7.1.56 STRB(2) */
 625                                 0xe19000d0,             /* 7.1.34 LDRSB */
 626                                 0xe7900000,             /* 7.1.27 LDR(2) */
 627                                 0xe19000b0,             /* 7.1.33 LDRH(2) */
 628                                 0xe7d00000,             /* 7.1.31 LDRB(2) */
 629                                 0xe19000f0              /* 7.1.35 LDRSH */
 630                         };
 631                         return subset[(tinstr & (7<<9)) >> 9] |
 632                             ((tinstr & (7<<0)) << (12-0)) |     /* Rd */
 633                             ((tinstr & (7<<3)) << (16-3)) |     /* Rn */
 634                             ((tinstr & (7<<6)) >> (6-0));       /* Rm */
 635                 }
 636
 637         /* 6.5.1 Format 3: */
 638         case 0x4800 >> 11:                              /* 7.1.28 LDR(3) */
 639                 /* NOTE: This case is not technically possible. We're
 640                  *       loading 32-bit memory data via PC relative
 641                  *       addressing mode. So we can and should eliminate
 642                  *       this case. But I'll leave it here for now.
 643                  */
 644                 return 0xe59f0000 |
 645                     ((tinstr & (7<<8)) << (12-8)) |             /* Rd */
 646                     ((tinstr & 255) << (2-0));                  /* immed_8 */
 647
 648         /* 6.5.1 Format 4: */
 649         case 0x9000 >> 11:                              /* 7.1.54 STR(3) */
 650         case 0x9800 >> 11:                              /* 7.1.29 LDR(4) */
 651                 return 0xe58d0000 |
 652                         (L<<20) |                               /* L==1? */
 653                         ((tinstr & (7<<8)) << (12-8)) |         /* Rd */
 654                         ((tinstr & 255) << 2);                  /* immed_8 */
 655
 656         /* 6.6.1 Format 1: */
 657         case 0xc000 >> 11:                              /* 7.1.51 STMIA */
 658         case 0xc800 >> 11:                              /* 7.1.25 LDMIA */
 659                 {
 660                         u32 Rn = (tinstr & (7<<8)) >> 8;
 661                         u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
 662
 663                         return 0xe8800000 | W | (L<<20) | (Rn<<16) |
 664                                 (tinstr&255);
 665                 }
 666
 667         /* 6.6.1 Format 2: */
 668         case 0xb000 >> 11:                              /* 7.1.48 PUSH */
 669         case 0xb800 >> 11:                              /* 7.1.47 POP */
 670                 if ((tinstr & (3 << 9)) == 0x0400) {
 671                         static const u32 subset[4] = {
 672                                 0xe92d0000,     /* STMDB sp!,{registers} */
 673                                 0xe92d4000,     /* STMDB sp!,{registers,lr} */
 674                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
 675                                 0xe8bd8000      /* LDMIA sp!,{registers,pc} */
 676                         };
 677                         return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
 678                             (tinstr & 255);             /* register_list */
 679                 }
 680                 /* Else fall through for illegal instruction case */
 681
 682         default:
 683                 return BAD_INSTR;
 684         }
 685 }
 686
 687 /*
 688  * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
 689  * handlable by ARM alignment handler, also find the corresponding handler,
 690  * so that we can reuse ARM userland alignment fault fixups for Thumb.
 691  *
 692  * @pinstr: original Thumb-2 instruction; returns new handlable instruction
 693  * @regs: register context.
 694  * @poffset: return offset from faulted addr for later writeback
 695  *
 696  * NOTES:
 697  * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
 698  * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
 699  */
 700 static void *
 701 do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
 702                             union offset_union *poffset)
 703 {
 704         unsigned long instr = *pinstr;
 705         u16 tinst1 = (instr >> 16) & 0xffff;
 706         u16 tinst2 = instr & 0xffff;
 707
 708         switch (tinst1 & 0xffe0) {
 709         /* A6.3.5 Load/Store multiple */
 710         case 0xe880:            /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
 711         case 0xe8a0:            /* ...above writeback version */
 712         case 0xe900:            /* STMDB/STMFD, LDMDB/LDMEA */
 713         case 0xe920:            /* ...above writeback version */
 714                 /* no need offset decision since handler calculates it */
 715                 return do_alignment_ldmstm;
 716
 717         case 0xf840:            /* POP/PUSH T3 (single register) */
 718                 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
 719                         u32 L = !!(LDST_L_BIT(instr));
 720                         const u32 subset[2] = {
 721                                 0xe92d0000,     /* STMDB sp!,{registers} */
 722                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
 723                         };
 724                         *pinstr = subset[L] | (1<<RD_BITS(instr));
 725                         return do_alignment_ldmstm;
 726                 }
 727                 /* Else fall through for illegal instruction case */
 728                 break;
 729
 730         /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
 731         case 0xe860:
 732         case 0xe960:
 733         case 0xe8e0:
 734         case 0xe9e0:
 735                 poffset->un = (tinst2 & 0xff) << 2;
 736         case 0xe940:
 737         case 0xe9c0:
 738                 return do_alignment_ldrdstrd;
 739
 740         /*
 741          * No need to handle load/store instructions up to word size
 742          * since ARMv6 and later CPUs can perform unaligned accesses.
 743          */
 744         default:
 745                 break;
 746         }
 747         return NULL;
 748 }
 749
 750 static int
 751 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 752 {
 753         union offset_union uninitialized_var(offset);
 754         unsigned long instr = 0, instrptr;
 755         int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
 756         unsigned int type;
 757         unsigned int fault;
 758         u16 tinstr = 0;
 759         int isize = 4;
 760         int thumb2_32b = 0;
 761
 762         if (interrupts_enabled(regs))
 763                 local_irq_enable();
 764
 765         instrptr = instruction_pointer(regs);
 766
 767         if (thumb_mode(regs)) {
 768                 u16 *ptr = (u16 *)(instrptr & ~1);
 769                 fault = probe_kernel_address(ptr, tinstr);
 770                 tinstr = __mem_to_opcode_thumb16(tinstr);
 771                 if (!fault) {
 772                         if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
 773                             IS_T32(tinstr)) {
 774                                 /* Thumb-2 32-bit */
 775                                 u16 tinst2 = 0;
 776                                 fault = probe_kernel_address(ptr + 1, tinst2);
 777                                 tinst2 = __mem_to_opcode_thumb16(tinst2);
 778                                 instr = __opcode_thumb32_compose(tinstr, tinst2);
 779                                 thumb2_32b = 1;
 780                         } else {
 781                                 isize = 2;
 782                                 instr = thumb2arm(tinstr);
 783                         }
 784                 }
 785         } else {
 786                 fault = probe_kernel_address(instrptr, instr);
 787                 instr = __mem_to_opcode_arm(instr);
 788         }
 789
 790         if (fault) {
 791                 type = TYPE_FAULT;
 792                 goto bad_or_fault;
 793         }
 794
 795         if (user_mode(regs))
 796                 goto user;
 797
 798         ai_sys += 1;
 799         ai_sys_last_pc = (void *)instruction_pointer(regs);
 800
 801  fixup:
 802
 803         regs->ARM_pc += isize;
 804
 805         switch (CODING_BITS(instr)) {
 806         case 0x00000000:        /* 3.13.4 load/store instruction extensions */
 807                 if (LDSTHD_I_BIT(instr))
 808                         offset.un = (instr & 0xf00) >> 4 | (instr & 15);
 809                 else
 810                         offset.un = regs->uregs[RM_BITS(instr)];
 811
 812                 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
 813                     (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
 814                         handler = do_alignment_ldrhstrh;
 815                 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
 816                          (instr & 0x001000f0) == 0x000000f0)   /* STRD */
 817                         handler = do_alignment_ldrdstrd;
 818                 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
 819                         goto swp;
 820                 else
 821                         goto bad;
 822                 break;
 823
 824         case 0x04000000:        /* ldr or str immediate */
 825                 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
 826                         goto bad;
 827                 offset.un = OFFSET_BITS(instr);
 828                 handler = do_alignment_ldrstr;
 829                 break;
 830
 831         case 0x06000000:        /* ldr or str register */
 832                 offset.un = regs->uregs[RM_BITS(instr)];
 833
 834                 if (IS_SHIFT(instr)) {
 835                         unsigned int shiftval = SHIFT_BITS(instr);
 836
 837                         switch(SHIFT_TYPE(instr)) {
 838                         case SHIFT_LSL:
 839                                 offset.un <<= shiftval;
 840                                 break;
 841
 842                         case SHIFT_LSR:
 843                                 offset.un >>= shiftval;
 844                                 break;
 845
 846                         case SHIFT_ASR:
 847                                 offset.sn >>= shiftval;
 848                                 break;
 849
 850                         case SHIFT_RORRRX:
 851                                 if (shiftval == 0) {
 852                                         offset.un >>= 1;
 853                                         if (regs->ARM_cpsr & PSR_C_BIT)
 854                                                 offset.un |= 1 << 31;
 855                                 } else
 856                                         offset.un = offset.un >> shiftval |
 857                                                           offset.un << (32 - shiftval);
 858                                 break;
 859                         }
 860                 }
 861                 handler = do_alignment_ldrstr;
 862                 break;
 863
 864         case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
 865                 if (thumb2_32b) {
 866                         offset.un = 0;
 867                         handler = do_alignment_t32_to_handler(&instr, regs, &offset);
 868                 } else {
 869                         offset.un = 0;
 870                         handler = do_alignment_ldmstm;
 871                 }
 872                 break;
 873
 874         default:
 875                 goto bad;
 876         }
 877
 878         if (!handler)
 879                 goto bad;
 880         type = handler(addr, instr, regs);
 881
 882         if (type == TYPE_ERROR || type == TYPE_FAULT) {
 883                 regs->ARM_pc -= isize;
 884                 goto bad_or_fault;
 885         }
 886
 887         if (type == TYPE_LDST)
 888                 do_alignment_finish_ldst(addr, instr, regs, offset);
 889
 890         return 0;
 891
 892  bad_or_fault:
 893         if (type == TYPE_ERROR)
 894                 goto bad;
 895         /*
 896          * We got a fault - fix it up, or die.
 897          */
 898         do_bad_area(addr, fsr, regs);
 899         return 0;
 900
 901  swp:
 902         pr_err("Alignment trap: not handling swp instruction\n");
 903
 904  bad:
 905         /*
 906          * Oops, we didn't handle the instruction.
 907          */
 908         pr_err("Alignment trap: not handling instruction "
 909                 "%0*lx at [<%08lx>]\n",
 910                 isize << 1,
 911                 isize == 2 ? tinstr : instr, instrptr);
 912         ai_skipped += 1;
 913         return 1;
 914
 915  user:
 916         ai_user += 1;
 917
 918         if (ai_usermode & UM_WARN)
 919                 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
 920                        "Address=0x%08lx FSR 0x%03x\n", current->comm,
 921                         task_pid_nr(current), instrptr,
 922                         isize << 1,
 923                         isize == 2 ? tinstr : instr,
 924                         addr, fsr);
 925
 926         if (ai_usermode & UM_FIXUP)
 927                 goto fixup;
 928
 929         if (ai_usermode & UM_SIGNAL) {
 930                 siginfo_t si;
 931
 932                 si.si_signo = SIGBUS;
 933                 si.si_errno = 0;
 934                 si.si_code = BUS_ADRALN;
 935                 si.si_addr = (void __user *)addr;
 936
 937                 force_sig_info(si.si_signo, &si, current);
 938         } else {
 939                 /*
 940                  * We're about to disable the alignment trap and return to
 941                  * user space.  But if an interrupt occurs before actually
 942                  * reaching user space, then the IRQ vector entry code will
 943                  * notice that we were still in kernel space and therefore
 944                  * the alignment trap won't be re-enabled in that case as it
 945                  * is presumed to be always on from kernel space.
 946                  * Let's prevent that race by disabling interrupts here (they
 947                  * are disabled on the way back to user space anyway in
 948                  * entry-common.S) and disable the alignment trap only if
 949                  * there is no work pending for this thread.
 950                  */
 951                 raw_local_irq_disable();
 952                 if (!(current_thread_info()->flags & _TIF_WORK_MASK))
 953                         set_cr(cr_no_alignment);
 954         }
 955
 956         return 0;
 957 }
 958
 959 static int __init noalign_setup(char *__unused)
 960 {
 961         set_cr(__clear_cr(CR_A));
 962         return 1;
 963 }
 964 __setup("noalign", noalign_setup);
 965
 966 /*
 967  * This needs to be done after sysctl_init, otherwise sys/ will be
 968  * overwritten.  Actually, this shouldn't be in sys/ at all since
 969  * it isn't a sysctl, and it doesn't contain sysctl information.
 970  * We now locate it in /proc/cpu/alignment instead.
 971  */
 972 static int __init alignment_init(void)
 973 {
 974 #ifdef CONFIG_PROC_FS
 975         struct proc_dir_entry *res;
 976
 977         res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
 978                           &alignment_proc_fops);
 979         if (!res)
 980                 return -ENOMEM;
 981 #endif
 982
 983         if (cpu_is_v6_unaligned()) {
 984                 set_cr(__clear_cr(CR_A));
 985                 ai_usermode = safe_usermode(ai_usermode, false);
 986         }
 987
 988         cr_no_alignment = get_cr() & ~CR_A;
 989
 990         hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
 991                         "alignment exception");
 992
 993         /*
 994          * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
 995          * fault, not as alignment error.
 996          *
 997          * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
 998          * needed.
 999          */
1000         if (cpu_architecture() <= CPU_ARCH_ARMv6) {
1001                 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
1002                                 "alignment exception");
1003         }
1004
1005         return 0;
1006 }
1007
1008 fs_initcall(alignment_init);