arch/arm/mm/cache-l2x0.c

   1 /*
   2  * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
   3  *
   4  * Copyright (C) 2007 ARM Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18  */
  19 #include <linux/cpu.h>
  20 #include <linux/err.h>
  21 #include <linux/init.h>
  22 #include <linux/smp.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/log2.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28
  29 #include <asm/cacheflush.h>
  30 #include <asm/cp15.h>
  31 #include <asm/cputype.h>
  32 #include <asm/hardware/cache-l2x0.h>
  33 #include "cache-tauros3.h"
  34 #include "cache-aurora-l2.h"
  35
  36 struct l2c_init_data {
  37         const char *type;
  38         unsigned way_size_0;
  39         unsigned num_lock;
  40         void (*of_parse)(const struct device_node *, u32 *, u32 *);
  41         void (*enable)(void __iomem *, unsigned);
  42         void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
  43         void (*save)(void __iomem *);
  44         void (*configure)(void __iomem *);
  45         void (*unlock)(void __iomem *, unsigned);
  46         struct outer_cache_fns outer_cache;
  47 };
  48
  49 #define CACHE_LINE_SIZE         32
  50
  51 static void __iomem *l2x0_base;
  52 static const struct l2c_init_data *l2x0_data;
  53 static DEFINE_RAW_SPINLOCK(l2x0_lock);
  54 static u32 l2x0_way_mask;       /* Bitmask of active ways */
  55 static u32 l2x0_size;
  56 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
  57
  58 struct l2x0_regs l2x0_saved_regs;
  59
  60 /*
  61  * Common code for all cache controllers.
  62  */
  63 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask)
  64 {
  65         /* wait for cache operation by line or way to complete */
  66         while (readl_relaxed(reg) & mask)
  67                 cpu_relax();
  68 }
  69
  70 /*
  71  * By default, we write directly to secure registers.  Platforms must
  72  * override this if they are running non-secure.
  73  */
  74 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg)
  75 {
  76         if (val == readl_relaxed(base + reg))
  77                 return;
  78         if (outer_cache.write_sec)
  79                 outer_cache.write_sec(val, reg);
  80         else
  81                 writel_relaxed(val, base + reg);
  82 }
  83
  84 /*
  85  * This should only be called when we have a requirement that the
  86  * register be written due to a work-around, as platforms running
  87  * in non-secure mode may not be able to access this register.
  88  */
  89 static inline void l2c_set_debug(void __iomem *base, unsigned long val)
  90 {
  91         l2c_write_sec(val, base, L2X0_DEBUG_CTRL);
  92 }
  93
  94 static void __l2c_op_way(void __iomem *reg)
  95 {
  96         writel_relaxed(l2x0_way_mask, reg);
  97         l2c_wait_mask(reg, l2x0_way_mask);
  98 }
  99
 100 static inline void l2c_unlock(void __iomem *base, unsigned num)
 101 {
 102         unsigned i;
 103
 104         for (i = 0; i < num; i++) {
 105                 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
 106                                i * L2X0_LOCKDOWN_STRIDE);
 107                 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
 108                                i * L2X0_LOCKDOWN_STRIDE);
 109         }
 110 }
 111
 112 static void l2c_configure(void __iomem *base)
 113 {
 114         l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
 115 }
 116
 117 /*
 118  * Enable the L2 cache controller.  This function must only be
 119  * called when the cache controller is known to be disabled.
 120  */
 121 static void l2c_enable(void __iomem *base, unsigned num_lock)
 122 {
 123         unsigned long flags;
 124
 125         if (outer_cache.configure)
 126                 outer_cache.configure(&l2x0_saved_regs);
 127         else
 128                 l2x0_data->configure(base);
 129
 130         l2x0_data->unlock(base, num_lock);
 131
 132         local_irq_save(flags);
 133         __l2c_op_way(base + L2X0_INV_WAY);
 134         writel_relaxed(0, base + sync_reg_offset);
 135         l2c_wait_mask(base + sync_reg_offset, 1);
 136         local_irq_restore(flags);
 137
 138         l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL);
 139 }
 140
 141 static void l2c_disable(void)
 142 {
 143         void __iomem *base = l2x0_base;
 144
 145         outer_cache.flush_all();
 146         l2c_write_sec(0, base, L2X0_CTRL);
 147         dsb(st);
 148 }
 149
 150 static void l2c_save(void __iomem *base)
 151 {
 152         l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 153 }
 154
 155 static void l2c_resume(void)
 156 {
 157         void __iomem *base = l2x0_base;
 158
 159         /* Do not touch the controller if already enabled. */
 160         if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
 161                 l2c_enable(base, l2x0_data->num_lock);
 162 }
 163
 164 /*
 165  * L2C-210 specific code.
 166  *
 167  * The L2C-2x0 PA, set/way and sync operations are atomic, but we must
 168  * ensure that no background operation is running.  The way operations
 169  * are all background tasks.
 170  *
 171  * While a background operation is in progress, any new operation is
 172  * ignored (unspecified whether this causes an error.)  Thankfully, not
 173  * used on SMP.
 174  *
 175  * Never has a different sync register other than L2X0_CACHE_SYNC, but
 176  * we use sync_reg_offset here so we can share some of this with L2C-310.
 177  */
 178 static void __l2c210_cache_sync(void __iomem *base)
 179 {
 180         writel_relaxed(0, base + sync_reg_offset);
 181 }
 182
 183 static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start,
 184         unsigned long end)
 185 {
 186         while (start < end) {
 187                 writel_relaxed(start, reg);
 188                 start += CACHE_LINE_SIZE;
 189         }
 190 }
 191
 192 static void l2c210_inv_range(unsigned long start, unsigned long end)
 193 {
 194         void __iomem *base = l2x0_base;
 195
 196         if (start & (CACHE_LINE_SIZE - 1)) {
 197                 start &= ~(CACHE_LINE_SIZE - 1);
 198                 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
 199                 start += CACHE_LINE_SIZE;
 200         }
 201
 202         if (end & (CACHE_LINE_SIZE - 1)) {
 203                 end &= ~(CACHE_LINE_SIZE - 1);
 204                 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
 205         }
 206
 207         __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
 208         __l2c210_cache_sync(base);
 209 }
 210
 211 static void l2c210_clean_range(unsigned long start, unsigned long end)
 212 {
 213         void __iomem *base = l2x0_base;
 214
 215         start &= ~(CACHE_LINE_SIZE - 1);
 216         __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end);
 217         __l2c210_cache_sync(base);
 218 }
 219
 220 static void l2c210_flush_range(unsigned long start, unsigned long end)
 221 {
 222         void __iomem *base = l2x0_base;
 223
 224         start &= ~(CACHE_LINE_SIZE - 1);
 225         __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end);
 226         __l2c210_cache_sync(base);
 227 }
 228
 229 static void l2c210_flush_all(void)
 230 {
 231         void __iomem *base = l2x0_base;
 232
 233         BUG_ON(!irqs_disabled());
 234
 235         __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
 236         __l2c210_cache_sync(base);
 237 }
 238
 239 static void l2c210_sync(void)
 240 {
 241         __l2c210_cache_sync(l2x0_base);
 242 }
 243
 244 static const struct l2c_init_data l2c210_data __initconst = {
 245         .type = "L2C-210",
 246         .way_size_0 = SZ_8K,
 247         .num_lock = 1,
 248         .enable = l2c_enable,
 249         .save = l2c_save,
 250         .configure = l2c_configure,
 251         .unlock = l2c_unlock,
 252         .outer_cache = {
 253                 .inv_range = l2c210_inv_range,
 254                 .clean_range = l2c210_clean_range,
 255                 .flush_range = l2c210_flush_range,
 256                 .flush_all = l2c210_flush_all,
 257                 .disable = l2c_disable,
 258                 .sync = l2c210_sync,
 259                 .resume = l2c_resume,
 260         },
 261 };
 262
 263 /*
 264  * L2C-220 specific code.
 265  *
 266  * All operations are background operations: they have to be waited for.
 267  * Conflicting requests generate a slave error (which will cause an
 268  * imprecise abort.)  Never uses sync_reg_offset, so we hard-code the
 269  * sync register here.
 270  *
 271  * However, we can re-use the l2c210_resume call.
 272  */
 273 static inline void __l2c220_cache_sync(void __iomem *base)
 274 {
 275         writel_relaxed(0, base + L2X0_CACHE_SYNC);
 276         l2c_wait_mask(base + L2X0_CACHE_SYNC, 1);
 277 }
 278
 279 static void l2c220_op_way(void __iomem *base, unsigned reg)
 280 {
 281         unsigned long flags;
 282
 283         raw_spin_lock_irqsave(&l2x0_lock, flags);
 284         __l2c_op_way(base + reg);
 285         __l2c220_cache_sync(base);
 286         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 287 }
 288
 289 static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
 290         unsigned long end, unsigned long flags)
 291 {
 292         raw_spinlock_t *lock = &l2x0_lock;
 293
 294         while (start < end) {
 295                 unsigned long blk_end = start + min(end - start, 4096UL);
 296
 297                 while (start < blk_end) {
 298                         l2c_wait_mask(reg, 1);
 299                         writel_relaxed(start, reg);
 300                         start += CACHE_LINE_SIZE;
 301                 }
 302
 303                 if (blk_end < end) {
 304                         raw_spin_unlock_irqrestore(lock, flags);
 305                         raw_spin_lock_irqsave(lock, flags);
 306                 }
 307         }
 308
 309         return flags;
 310 }
 311
 312 static void l2c220_inv_range(unsigned long start, unsigned long end)
 313 {
 314         void __iomem *base = l2x0_base;
 315         unsigned long flags;
 316
 317         raw_spin_lock_irqsave(&l2x0_lock, flags);
 318         if ((start | end) & (CACHE_LINE_SIZE - 1)) {
 319                 if (start & (CACHE_LINE_SIZE - 1)) {
 320                         start &= ~(CACHE_LINE_SIZE - 1);
 321                         writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
 322                         start += CACHE_LINE_SIZE;
 323                 }
 324
 325                 if (end & (CACHE_LINE_SIZE - 1)) {
 326                         end &= ~(CACHE_LINE_SIZE - 1);
 327                         l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
 328                         writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
 329                 }
 330         }
 331
 332         flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA,
 333                                    start, end, flags);
 334         l2c_wait_mask(base + L2X0_INV_LINE_PA, 1);
 335         __l2c220_cache_sync(base);
 336         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 337 }
 338
 339 static void l2c220_clean_range(unsigned long start, unsigned long end)
 340 {
 341         void __iomem *base = l2x0_base;
 342         unsigned long flags;
 343
 344         start &= ~(CACHE_LINE_SIZE - 1);
 345         if ((end - start) >= l2x0_size) {
 346                 l2c220_op_way(base, L2X0_CLEAN_WAY);
 347                 return;
 348         }
 349
 350         raw_spin_lock_irqsave(&l2x0_lock, flags);
 351         flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA,
 352                                    start, end, flags);
 353         l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
 354         __l2c220_cache_sync(base);
 355         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 356 }
 357
 358 static void l2c220_flush_range(unsigned long start, unsigned long end)
 359 {
 360         void __iomem *base = l2x0_base;
 361         unsigned long flags;
 362
 363         start &= ~(CACHE_LINE_SIZE - 1);
 364         if ((end - start) >= l2x0_size) {
 365                 l2c220_op_way(base, L2X0_CLEAN_INV_WAY);
 366                 return;
 367         }
 368
 369         raw_spin_lock_irqsave(&l2x0_lock, flags);
 370         flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA,
 371                                    start, end, flags);
 372         l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
 373         __l2c220_cache_sync(base);
 374         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 375 }
 376
 377 static void l2c220_flush_all(void)
 378 {
 379         l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY);
 380 }
 381
 382 static void l2c220_sync(void)
 383 {
 384         unsigned long flags;
 385
 386         raw_spin_lock_irqsave(&l2x0_lock, flags);
 387         __l2c220_cache_sync(l2x0_base);
 388         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 389 }
 390
 391 static void l2c220_enable(void __iomem *base, unsigned num_lock)
 392 {
 393         /*
 394          * Always enable non-secure access to the lockdown registers -
 395          * we write to them as part of the L2C enable sequence so they
 396          * need to be accessible.
 397          */
 398         l2x0_saved_regs.aux_ctrl |= L220_AUX_CTRL_NS_LOCKDOWN;
 399
 400         l2c_enable(base, num_lock);
 401 }
 402
 403 static void l2c220_unlock(void __iomem *base, unsigned num_lock)
 404 {
 405         if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN)
 406                 l2c_unlock(base, num_lock);
 407 }
 408
 409 static const struct l2c_init_data l2c220_data = {
 410         .type = "L2C-220",
 411         .way_size_0 = SZ_8K,
 412         .num_lock = 1,
 413         .enable = l2c220_enable,
 414         .save = l2c_save,
 415         .configure = l2c_configure,
 416         .unlock = l2c220_unlock,
 417         .outer_cache = {
 418                 .inv_range = l2c220_inv_range,
 419                 .clean_range = l2c220_clean_range,
 420                 .flush_range = l2c220_flush_range,
 421                 .flush_all = l2c220_flush_all,
 422                 .disable = l2c_disable,
 423                 .sync = l2c220_sync,
 424                 .resume = l2c_resume,
 425         },
 426 };
 427
 428 /*
 429  * L2C-310 specific code.
 430  *
 431  * Very similar to L2C-210, the PA, set/way and sync operations are atomic,
 432  * and the way operations are all background tasks.  However, issuing an
 433  * operation while a background operation is in progress results in a
 434  * SLVERR response.  We can reuse:
 435  *
 436  *  __l2c210_cache_sync (using sync_reg_offset)
 437  *  l2c210_sync
 438  *  l2c210_inv_range (if 588369 is not applicable)
 439  *  l2c210_clean_range
 440  *  l2c210_flush_range (if 588369 is not applicable)
 441  *  l2c210_flush_all (if 727915 is not applicable)
 442  *
 443  * Errata:
 444  * 588369: PL310 R0P0->R1P0, fixed R2P0.
 445  *      Affects: all clean+invalidate operations
 446  *      clean and invalidate skips the invalidate step, so we need to issue
 447  *      separate operations.  We also require the above debug workaround
 448  *      enclosing this code fragment on affected parts.  On unaffected parts,
 449  *      we must not use this workaround without the debug register writes
 450  *      to avoid exposing a problem similar to 727915.
 451  *
 452  * 727915: PL310 R2P0->R3P0, fixed R3P1.
 453  *      Affects: clean+invalidate by way
 454  *      clean and invalidate by way runs in the background, and a store can
 455  *      hit the line between the clean operation and invalidate operation,
 456  *      resulting in the store being lost.
 457  *
 458  * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2.
 459  *      Affects: 8x64-bit (double fill) line fetches
 460  *      double fill line fetches can fail to cause dirty data to be evicted
 461  *      from the cache before the new data overwrites the second line.
 462  *
 463  * 753970: PL310 R3P0, fixed R3P1.
 464  *      Affects: sync
 465  *      prevents merging writes after the sync operation, until another L2C
 466  *      operation is performed (or a number of other conditions.)
 467  *
 468  * 769419: PL310 R0P0->R3P1, fixed R3P2.
 469  *      Affects: store buffer
 470  *      store buffer is not automatically drained.
 471  */
 472 static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)
 473 {
 474         void __iomem *base = l2x0_base;
 475
 476         if ((start | end) & (CACHE_LINE_SIZE - 1)) {
 477                 unsigned long flags;
 478
 479                 /* Erratum 588369 for both clean+invalidate operations */
 480                 raw_spin_lock_irqsave(&l2x0_lock, flags);
 481                 l2c_set_debug(base, 0x03);
 482
 483                 if (start & (CACHE_LINE_SIZE - 1)) {
 484                         start &= ~(CACHE_LINE_SIZE - 1);
 485                         writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
 486                         writel_relaxed(start, base + L2X0_INV_LINE_PA);
 487                         start += CACHE_LINE_SIZE;
 488                 }
 489
 490                 if (end & (CACHE_LINE_SIZE - 1)) {
 491                         end &= ~(CACHE_LINE_SIZE - 1);
 492                         writel_relaxed(end, base + L2X0_CLEAN_LINE_PA);
 493                         writel_relaxed(end, base + L2X0_INV_LINE_PA);
 494                 }
 495
 496                 l2c_set_debug(base, 0x00);
 497                 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 498         }
 499
 500         __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
 501         __l2c210_cache_sync(base);
 502 }
 503
 504 static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
 505 {
 506         raw_spinlock_t *lock = &l2x0_lock;
 507         unsigned long flags;
 508         void __iomem *base = l2x0_base;
 509
 510         raw_spin_lock_irqsave(lock, flags);
 511         while (start < end) {
 512                 unsigned long blk_end = start + min(end - start, 4096UL);
 513
 514                 l2c_set_debug(base, 0x03);
 515                 while (start < blk_end) {
 516                         writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
 517                         writel_relaxed(start, base + L2X0_INV_LINE_PA);
 518                         start += CACHE_LINE_SIZE;
 519                 }
 520                 l2c_set_debug(base, 0x00);
 521
 522                 if (blk_end < end) {
 523                         raw_spin_unlock_irqrestore(lock, flags);
 524                         raw_spin_lock_irqsave(lock, flags);
 525                 }
 526         }
 527         raw_spin_unlock_irqrestore(lock, flags);
 528         __l2c210_cache_sync(base);
 529 }
 530
 531 static void l2c310_flush_all_erratum(void)
 532 {
 533         void __iomem *base = l2x0_base;
 534         unsigned long flags;
 535
 536         raw_spin_lock_irqsave(&l2x0_lock, flags);
 537         l2c_set_debug(base, 0x03);
 538         __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
 539         l2c_set_debug(base, 0x00);
 540         __l2c210_cache_sync(base);
 541         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 542 }
 543
 544 static void __init l2c310_save(void __iomem *base)
 545 {
 546         unsigned revision;
 547
 548         l2c_save(base);
 549
 550         l2x0_saved_regs.tag_latency = readl_relaxed(base +
 551                 L310_TAG_LATENCY_CTRL);
 552         l2x0_saved_regs.data_latency = readl_relaxed(base +
 553                 L310_DATA_LATENCY_CTRL);
 554         l2x0_saved_regs.filter_end = readl_relaxed(base +
 555                 L310_ADDR_FILTER_END);
 556         l2x0_saved_regs.filter_start = readl_relaxed(base +
 557                 L310_ADDR_FILTER_START);
 558
 559         revision = readl_relaxed(base + L2X0_CACHE_ID) &
 560                         L2X0_CACHE_ID_RTL_MASK;
 561
 562         /* From r2p0, there is Prefetch offset/control register */
 563         if (revision >= L310_CACHE_ID_RTL_R2P0)
 564                 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
 565                                                         L310_PREFETCH_CTRL);
 566
 567         /* From r3p0, there is Power control register */
 568         if (revision >= L310_CACHE_ID_RTL_R3P0)
 569                 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
 570                                                         L310_POWER_CTRL);
 571 }
 572
 573 static void l2c310_configure(void __iomem *base)
 574 {
 575         unsigned revision;
 576
 577         l2c_configure(base);
 578
 579         /* restore pl310 setup */
 580         l2c_write_sec(l2x0_saved_regs.tag_latency, base,
 581                       L310_TAG_LATENCY_CTRL);
 582         l2c_write_sec(l2x0_saved_regs.data_latency, base,
 583                       L310_DATA_LATENCY_CTRL);
 584         l2c_write_sec(l2x0_saved_regs.filter_end, base,
 585                       L310_ADDR_FILTER_END);
 586         l2c_write_sec(l2x0_saved_regs.filter_start, base,
 587                       L310_ADDR_FILTER_START);
 588
 589         revision = readl_relaxed(base + L2X0_CACHE_ID) &
 590                                  L2X0_CACHE_ID_RTL_MASK;
 591
 592         if (revision >= L310_CACHE_ID_RTL_R2P0)
 593                 l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
 594                               L310_PREFETCH_CTRL);
 595         if (revision >= L310_CACHE_ID_RTL_R3P0)
 596                 l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
 597                               L310_POWER_CTRL);
 598 }
 599
 600 static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data)
 601 {
 602         switch (act & ~CPU_TASKS_FROZEN) {
 603         case CPU_STARTING:
 604                 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
 605                 break;
 606         case CPU_DYING:
 607                 set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
 608                 break;
 609         }
 610         return NOTIFY_OK;
 611 }
 612
 613 static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
 614 {
 615         unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK;
 616         bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9;
 617         u32 aux = l2x0_saved_regs.aux_ctrl;
 618
 619         if (rev >= L310_CACHE_ID_RTL_R2P0) {
 620                 if (cortex_a9) {
 621                         aux |= L310_AUX_CTRL_EARLY_BRESP;
 622                         pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
 623                 } else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
 624                         pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n");
 625                         aux &= ~L310_AUX_CTRL_EARLY_BRESP;
 626                 }
 627         }
 628
 629         if (cortex_a9) {
 630                 u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);
 631                 u32 acr = get_auxcr();
 632
 633                 pr_debug("Cortex-A9 ACR=0x%08x\n", acr);
 634
 635                 if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO))
 636                         pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n");
 637
 638                 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3)))
 639                         pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n");
 640
 641                 if (!(aux & L310_AUX_CTRL_FULL_LINE_ZERO) && !outer_cache.write_sec) {
 642                         aux |= L310_AUX_CTRL_FULL_LINE_ZERO;
 643                         pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n");
 644                 }
 645         } else if (aux & (L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP)) {
 646                 pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n");
 647                 aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP);
 648         }
 649
 650         /* r3p0 or later has power control register */
 651         if (rev >= L310_CACHE_ID_RTL_R3P0)
 652                 l2x0_saved_regs.pwr_ctrl = L310_DYNAMIC_CLK_GATING_EN |
 653                                                 L310_STNDBY_MODE_EN;
 654
 655         /*
 656          * Always enable non-secure access to the lockdown registers -
 657          * we write to them as part of the L2C enable sequence so they
 658          * need to be accessible.
 659          */
 660         l2x0_saved_regs.aux_ctrl = aux | L310_AUX_CTRL_NS_LOCKDOWN;
 661
 662         l2c_enable(base, num_lock);
 663
 664         /* Read back resulting AUX_CTRL value as it could have been altered. */
 665         aux = readl_relaxed(base + L2X0_AUX_CTRL);
 666
 667         if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) {
 668                 u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL);
 669
 670                 pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n",
 671                         aux & L310_AUX_CTRL_INSTR_PREFETCH ? "I" : "",
 672                         aux & L310_AUX_CTRL_DATA_PREFETCH ? "D" : "",
 673                         1 + (prefetch & L310_PREFETCH_CTRL_OFFSET_MASK));
 674         }
 675
 676         /* r3p0 or later has power control register */
 677         if (rev >= L310_CACHE_ID_RTL_R3P0) {
 678                 u32 power_ctrl;
 679
 680                 power_ctrl = readl_relaxed(base + L310_POWER_CTRL);
 681                 pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n",
 682                         power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis",
 683                         power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis");
 684         }
 685
 686         if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) {
 687                 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
 688                 cpu_notifier(l2c310_cpu_enable_flz, 0);
 689         }
 690 }
 691
 692 static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
 693         struct outer_cache_fns *fns)
 694 {
 695         unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK;
 696         const char *errata[8];
 697         unsigned n = 0;
 698
 699         if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) &&
 700             revision < L310_CACHE_ID_RTL_R2P0 &&
 701             /* For bcm compatibility */
 702             fns->inv_range == l2c210_inv_range) {
 703                 fns->inv_range = l2c310_inv_range_erratum;
 704                 fns->flush_range = l2c310_flush_range_erratum;
 705                 errata[n++] = "588369";
 706         }
 707
 708         if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) &&
 709             revision >= L310_CACHE_ID_RTL_R2P0 &&
 710             revision < L310_CACHE_ID_RTL_R3P1) {
 711                 fns->flush_all = l2c310_flush_all_erratum;
 712                 errata[n++] = "727915";
 713         }
 714
 715         if (revision >= L310_CACHE_ID_RTL_R3P0 &&
 716             revision < L310_CACHE_ID_RTL_R3P2) {
 717                 u32 val = l2x0_saved_regs.prefetch_ctrl;
 718                 /* I don't think bit23 is required here... but iMX6 does so */
 719                 if (val & (BIT(30) | BIT(23))) {
 720                         val &= ~(BIT(30) | BIT(23));
 721                         l2x0_saved_regs.prefetch_ctrl = val;
 722                         errata[n++] = "752271";
 723                 }
 724         }
 725
 726         if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) &&
 727             revision == L310_CACHE_ID_RTL_R3P0) {
 728                 sync_reg_offset = L2X0_DUMMY_REG;
 729                 errata[n++] = "753970";
 730         }
 731
 732         if (IS_ENABLED(CONFIG_PL310_ERRATA_769419))
 733                 errata[n++] = "769419";
 734
 735         if (n) {
 736                 unsigned i;
 737
 738                 pr_info("L2C-310 errat%s", n > 1 ? "a" : "um");
 739                 for (i = 0; i < n; i++)
 740                         pr_cont(" %s", errata[i]);
 741                 pr_cont(" enabled\n");
 742         }
 743 }
 744
 745 static void l2c310_disable(void)
 746 {
 747         /*
 748          * If full-line-of-zeros is enabled, we must first disable it in the
 749          * Cortex-A9 auxiliary control register before disabling the L2 cache.
 750          */
 751         if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
 752                 set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
 753
 754         l2c_disable();
 755 }
 756
 757 static void l2c310_resume(void)
 758 {
 759         l2c_resume();
 760
 761         /* Re-enable full-line-of-zeros for Cortex-A9 */
 762         if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
 763                 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
 764 }
 765
 766 static void l2c310_unlock(void __iomem *base, unsigned num_lock)
 767 {
 768         if (readl_relaxed(base + L2X0_AUX_CTRL) & L310_AUX_CTRL_NS_LOCKDOWN)
 769                 l2c_unlock(base, num_lock);
 770 }
 771
 772 static const struct l2c_init_data l2c310_init_fns __initconst = {
 773         .type = "L2C-310",
 774         .way_size_0 = SZ_8K,
 775         .num_lock = 8,
 776         .enable = l2c310_enable,
 777         .fixup = l2c310_fixup,
 778         .save = l2c310_save,
 779         .configure = l2c310_configure,
 780         .unlock = l2c310_unlock,
 781         .outer_cache = {
 782                 .inv_range = l2c210_inv_range,
 783                 .clean_range = l2c210_clean_range,
 784                 .flush_range = l2c210_flush_range,
 785                 .flush_all = l2c210_flush_all,
 786                 .disable = l2c310_disable,
 787                 .sync = l2c210_sync,
 788                 .resume = l2c310_resume,
 789         },
 790 };
 791
 792 static int __init __l2c_init(const struct l2c_init_data *data,
 793                              u32 aux_val, u32 aux_mask, u32 cache_id)
 794 {
 795         struct outer_cache_fns fns;
 796         unsigned way_size_bits, ways;
 797         u32 aux, old_aux;
 798
 799         /*
 800          * Save the pointer globally so that callbacks which do not receive
 801          * context from callers can access the structure.
 802          */
 803         l2x0_data = kmemdup(data, sizeof(*data), GFP_KERNEL);
 804         if (!l2x0_data)
 805                 return -ENOMEM;
 806
 807         /*
 808          * Sanity check the aux values.  aux_mask is the bits we preserve
 809          * from reading the hardware register, and aux_val is the bits we
 810          * set.
 811          */
 812         if (aux_val & aux_mask)
 813                 pr_alert("L2C: platform provided aux values permit register corruption.\n");
 814
 815         old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 816         aux &= aux_mask;
 817         aux |= aux_val;
 818
 819         if (old_aux != aux)
 820                 pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n",
 821                         old_aux, aux);
 822
 823         /* Determine the number of ways */
 824         switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
 825         case L2X0_CACHE_ID_PART_L310:
 826                 if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16))
 827                         pr_warn("L2C: DT/platform tries to modify or specify cache size\n");
 828                 if (aux & (1 << 16))
 829                         ways = 16;
 830                 else
 831                         ways = 8;
 832                 break;
 833
 834         case L2X0_CACHE_ID_PART_L210:
 835         case L2X0_CACHE_ID_PART_L220:
 836                 ways = (aux >> 13) & 0xf;
 837                 break;
 838
 839         case AURORA_CACHE_ID:
 840                 ways = (aux >> 13) & 0xf;
 841                 ways = 2 << ((ways + 1) >> 2);
 842                 break;
 843
 844         default:
 845                 /* Assume unknown chips have 8 ways */
 846                 ways = 8;
 847                 break;
 848         }
 849
 850         l2x0_way_mask = (1 << ways) - 1;
 851
 852         /*
 853          * way_size_0 is the size that a way_size value of zero would be
 854          * given the calculation: way_size = way_size_0 << way_size_bits.
 855          * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k,
 856          * then way_size_0 would be 8k.
 857          *
 858          * L2 cache size = number of ways * way size.
 859          */
 860         way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >>
 861                         L2C_AUX_CTRL_WAY_SIZE_SHIFT;
 862         l2x0_size = ways * (data->way_size_0 << way_size_bits);
 863
 864         fns = data->outer_cache;
 865         fns.write_sec = outer_cache.write_sec;
 866         fns.configure = outer_cache.configure;
 867         if (data->fixup)
 868                 data->fixup(l2x0_base, cache_id, &fns);
 869
 870         /*
 871          * Check if l2x0 controller is already enabled.  If we are booting
 872          * in non-secure mode accessing the below registers will fault.
 873          */
 874         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 875                 l2x0_saved_regs.aux_ctrl = aux;
 876
 877                 data->enable(l2x0_base, data->num_lock);
 878         }
 879
 880         outer_cache = fns;
 881
 882         /*
 883          * It is strange to save the register state before initialisation,
 884          * but hey, this is what the DT implementations decided to do.
 885          */
 886         if (data->save)
 887                 data->save(l2x0_base);
 888
 889         /* Re-read it in case some bits are reserved. */
 890         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 891
 892         pr_info("%s cache controller enabled, %d ways, %d kB\n",
 893                 data->type, ways, l2x0_size >> 10);
 894         pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
 895                 data->type, cache_id, aux);
 896
 897         return 0;
 898 }
 899
 900 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 901 {
 902         const struct l2c_init_data *data;
 903         u32 cache_id;
 904
 905         l2x0_base = base;
 906
 907         cache_id = readl_relaxed(base + L2X0_CACHE_ID);
 908
 909         switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
 910         default:
 911         case L2X0_CACHE_ID_PART_L210:
 912                 data = &l2c210_data;
 913                 break;
 914
 915         case L2X0_CACHE_ID_PART_L220:
 916                 data = &l2c220_data;
 917                 break;
 918
 919         case L2X0_CACHE_ID_PART_L310:
 920                 data = &l2c310_init_fns;
 921                 break;
 922         }
 923
 924         /* Read back current (default) hardware configuration */
 925         if (data->save)
 926                 data->save(l2x0_base);
 927
 928         __l2c_init(data, aux_val, aux_mask, cache_id);
 929 }
 930
 931 #ifdef CONFIG_OF
 932 static int l2_wt_override;
 933
 934 /* Aurora don't have the cache ID register available, so we have to
 935  * pass it though the device tree */
 936 static u32 cache_id_part_number_from_dt;
 937
 938 /**
 939  * l2x0_cache_size_of_parse() - read cache size parameters from DT
 940  * @np: the device tree node for the l2 cache
 941  * @aux_val: pointer to machine-supplied auxilary register value, to
 942  * be augmented by the call (bits to be set to 1)
 943  * @aux_mask: pointer to machine-supplied auxilary register mask, to
 944  * be augmented by the call (bits to be set to 0)
 945  * @associativity: variable to return the calculated associativity in
 946  * @max_way_size: the maximum size in bytes for the cache ways
 947  */
 948 static int __init l2x0_cache_size_of_parse(const struct device_node *np,
 949                                             u32 *aux_val, u32 *aux_mask,
 950                                             u32 *associativity,
 951                                             u32 max_way_size)
 952 {
 953         u32 mask = 0, val = 0;
 954         u32 cache_size = 0, sets = 0;
 955         u32 way_size_bits = 1;
 956         u32 way_size = 0;
 957         u32 block_size = 0;
 958         u32 line_size = 0;
 959
 960         of_property_read_u32(np, "cache-size", &cache_size);
 961         of_property_read_u32(np, "cache-sets", &sets);
 962         of_property_read_u32(np, "cache-block-size", &block_size);
 963         of_property_read_u32(np, "cache-line-size", &line_size);
 964
 965         if (!cache_size || !sets)
 966                 return -ENODEV;
 967
 968         /* All these l2 caches have the same line = block size actually */
 969         if (!line_size) {
 970                 if (block_size) {
 971                         /* If linesize is not given, it is equal to blocksize */
 972                         line_size = block_size;
 973                 } else {
 974                         /* Fall back to known size */
 975                         pr_warn("L2C OF: no cache block/line size given: "
 976                                 "falling back to default size %d bytes\n",
 977                                 CACHE_LINE_SIZE);
 978                         line_size = CACHE_LINE_SIZE;
 979                 }
 980         }
 981
 982         if (line_size != CACHE_LINE_SIZE)
 983                 pr_warn("L2C OF: DT supplied line size %d bytes does "
 984                         "not match hardware line size of %d bytes\n",
 985                         line_size,
 986                         CACHE_LINE_SIZE);
 987
 988         /*
 989          * Since:
 990          * set size = cache size / sets
 991          * ways = cache size / (sets * line size)
 992          * way size = cache size / (cache size / (sets * line size))
 993          * way size = sets * line size
 994          * associativity = ways = cache size / way size
 995          */
 996         way_size = sets * line_size;
 997         *associativity = cache_size / way_size;
 998
 999         if (way_size > max_way_size) {
1000                 pr_err("L2C OF: set size %dKB is too large\n", way_size);
1001                 return -EINVAL;
1002         }
1003
1004         pr_info("L2C OF: override cache size: %d bytes (%dKB)\n",
1005                 cache_size, cache_size >> 10);
1006         pr_info("L2C OF: override line size: %d bytes\n", line_size);
1007         pr_info("L2C OF: override way size: %d bytes (%dKB)\n",
1008                 way_size, way_size >> 10);
1009         pr_info("L2C OF: override associativity: %d\n", *associativity);
1010
1011         /*
1012          * Calculates the bits 17:19 to set for way size:
1013          * 512KB -> 6, 256KB -> 5, ... 16KB -> 1
1014          */
1015         way_size_bits = ilog2(way_size >> 10) - 3;
1016         if (way_size_bits < 1 || way_size_bits > 6) {
1017                 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n",
1018                        way_size);
1019                 return -EINVAL;
1020         }
1021
1022         mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
1023         val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT);
1024
1025         *aux_val &= ~mask;
1026         *aux_val |= val;
1027         *aux_mask &= ~mask;
1028
1029         return 0;
1030 }
1031
1032 static void __init l2x0_of_parse(const struct device_node *np,
1033                                  u32 *aux_val, u32 *aux_mask)
1034 {
1035         u32 data[2] = { 0, 0 };
1036         u32 tag = 0;
1037         u32 dirty = 0;
1038         u32 val = 0, mask = 0;
1039         u32 assoc;
1040         int ret;
1041
1042         of_property_read_u32(np, "arm,tag-latency", &tag);
1043         if (tag) {
1044                 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
1045                 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
1046         }
1047
1048         of_property_read_u32_array(np, "arm,data-latency",
1049                                    data, ARRAY_SIZE(data));
1050         if (data[0] && data[1]) {
1051                 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
1052                         L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
1053                 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
1054                        ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
1055         }
1056
1057         of_property_read_u32(np, "arm,dirty-latency", &dirty);
1058         if (dirty) {
1059                 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
1060                 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
1061         }
1062
1063         ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
1064         if (ret)
1065                 return;
1066
1067         if (assoc > 8) {
1068                 pr_err("l2x0 of: cache setting yield too high associativity\n");
1069                 pr_err("l2x0 of: %d calculated, max 8\n", assoc);
1070         } else {
1071                 mask |= L2X0_AUX_CTRL_ASSOC_MASK;
1072                 val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT);
1073         }
1074
1075         *aux_val &= ~mask;
1076         *aux_val |= val;
1077         *aux_mask &= ~mask;
1078 }
1079
1080 static const struct l2c_init_data of_l2c210_data __initconst = {
1081         .type = "L2C-210",
1082         .way_size_0 = SZ_8K,
1083         .num_lock = 1,
1084         .of_parse = l2x0_of_parse,
1085         .enable = l2c_enable,
1086         .save = l2c_save,
1087         .configure = l2c_configure,
1088         .unlock = l2c_unlock,
1089         .outer_cache = {
1090                 .inv_range   = l2c210_inv_range,
1091                 .clean_range = l2c210_clean_range,
1092                 .flush_range = l2c210_flush_range,
1093                 .flush_all   = l2c210_flush_all,
1094                 .disable     = l2c_disable,
1095                 .sync        = l2c210_sync,
1096                 .resume      = l2c_resume,
1097         },
1098 };
1099
1100 static const struct l2c_init_data of_l2c220_data __initconst = {
1101         .type = "L2C-220",
1102         .way_size_0 = SZ_8K,
1103         .num_lock = 1,
1104         .of_parse = l2x0_of_parse,
1105         .enable = l2c220_enable,
1106         .save = l2c_save,
1107         .configure = l2c_configure,
1108         .unlock = l2c220_unlock,
1109         .outer_cache = {
1110                 .inv_range   = l2c220_inv_range,
1111                 .clean_range = l2c220_clean_range,
1112                 .flush_range = l2c220_flush_range,
1113                 .flush_all   = l2c220_flush_all,
1114                 .disable     = l2c_disable,
1115                 .sync        = l2c220_sync,
1116                 .resume      = l2c_resume,
1117         },
1118 };
1119
1120 static void __init l2c310_of_parse(const struct device_node *np,
1121         u32 *aux_val, u32 *aux_mask)
1122 {
1123         u32 data[3] = { 0, 0, 0 };
1124         u32 tag[3] = { 0, 0, 0 };
1125         u32 filter[2] = { 0, 0 };
1126         u32 assoc;
1127         u32 prefetch;
1128         u32 val;
1129         int ret;
1130
1131         of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
1132         if (tag[0] && tag[1] && tag[2])
1133                 l2x0_saved_regs.tag_latency =
1134                         L310_LATENCY_CTRL_RD(tag[0] - 1) |
1135                         L310_LATENCY_CTRL_WR(tag[1] - 1) |
1136                         L310_LATENCY_CTRL_SETUP(tag[2] - 1);
1137
1138         of_property_read_u32_array(np, "arm,data-latency",
1139                                    data, ARRAY_SIZE(data));
1140         if (data[0] && data[1] && data[2])
1141                 l2x0_saved_regs.data_latency =
1142                         L310_LATENCY_CTRL_RD(data[0] - 1) |
1143                         L310_LATENCY_CTRL_WR(data[1] - 1) |
1144                         L310_LATENCY_CTRL_SETUP(data[2] - 1);
1145
1146         of_property_read_u32_array(np, "arm,filter-ranges",
1147                                    filter, ARRAY_SIZE(filter));
1148         if (filter[1]) {
1149                 l2x0_saved_regs.filter_end =
1150                                         ALIGN(filter[0] + filter[1], SZ_1M);
1151                 l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1))
1152                                         | L310_ADDR_FILTER_EN;
1153         }
1154
1155         ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
1156         if (!ret) {
1157                 switch (assoc) {
1158                 case 16:
1159                         *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1160                         *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16;
1161                         *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1162                         break;
1163                 case 8:
1164                         *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1165                         *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1166                         break;
1167                 default:
1168                         pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n",
1169                                assoc);
1170                         break;
1171                 }
1172         }
1173
1174         if (of_property_read_bool(np, "arm,shared-override")) {
1175                 *aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
1176                 *aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
1177         }
1178
1179         prefetch = l2x0_saved_regs.prefetch_ctrl;
1180
1181         ret = of_property_read_u32(np, "arm,double-linefill", &val);
1182         if (ret == 0) {
1183                 if (val)
1184                         prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
1185                 else
1186                         prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
1187         } else if (ret != -EINVAL) {
1188                 pr_err("L2C-310 OF arm,double-linefill property value is missing\n");
1189         }
1190
1191         ret = of_property_read_u32(np, "arm,double-linefill-incr", &val);
1192         if (ret == 0) {
1193                 if (val)
1194                         prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
1195                 else
1196                         prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
1197         } else if (ret != -EINVAL) {
1198                 pr_err("L2C-310 OF arm,double-linefill-incr property value is missing\n");
1199         }
1200
1201         ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val);
1202         if (ret == 0) {
1203                 if (!val)
1204                         prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
1205                 else
1206                         prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
1207         } else if (ret != -EINVAL) {
1208                 pr_err("L2C-310 OF arm,double-linefill-wrap property value is missing\n");
1209         }
1210
1211         ret = of_property_read_u32(np, "arm,prefetch-drop", &val);
1212         if (ret == 0) {
1213                 if (val)
1214                         prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
1215                 else
1216                         prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP;
1217         } else if (ret != -EINVAL) {
1218                 pr_err("L2C-310 OF arm,prefetch-drop property value is missing\n");
1219         }
1220
1221         ret = of_property_read_u32(np, "arm,prefetch-offset", &val);
1222         if (ret == 0) {
1223                 prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
1224                 prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK;
1225         } else if (ret != -EINVAL) {
1226                 pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n");
1227         }
1228
1229         ret = of_property_read_u32(np, "prefetch-data", &val);
1230         if (ret == 0) {
1231                 if (val)
1232                         prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH;
1233                 else
1234                         prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH;
1235         } else if (ret != -EINVAL) {
1236                 pr_err("L2C-310 OF prefetch-data property value is missing\n");
1237         }
1238
1239         ret = of_property_read_u32(np, "prefetch-instr", &val);
1240         if (ret == 0) {
1241                 if (val)
1242                         prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH;
1243                 else
1244                         prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH;
1245         } else if (ret != -EINVAL) {
1246                 pr_err("L2C-310 OF prefetch-instr property value is missing\n");
1247         }
1248
1249         l2x0_saved_regs.prefetch_ctrl = prefetch;
1250 }
1251
1252 static const struct l2c_init_data of_l2c310_data __initconst = {
1253         .type = "L2C-310",
1254         .way_size_0 = SZ_8K,
1255         .num_lock = 8,
1256         .of_parse = l2c310_of_parse,
1257         .enable = l2c310_enable,
1258         .fixup = l2c310_fixup,
1259         .save  = l2c310_save,
1260         .configure = l2c310_configure,
1261         .unlock = l2c310_unlock,
1262         .outer_cache = {
1263                 .inv_range   = l2c210_inv_range,
1264                 .clean_range = l2c210_clean_range,
1265                 .flush_range = l2c210_flush_range,
1266                 .flush_all   = l2c210_flush_all,
1267                 .disable     = l2c310_disable,
1268                 .sync        = l2c210_sync,
1269                 .resume      = l2c310_resume,
1270         },
1271 };
1272
1273 /*
1274  * This is a variant of the of_l2c310_data with .sync set to
1275  * NULL. Outer sync operations are not needed when the system is I/O
1276  * coherent, and potentially harmful in certain situations (PCIe/PL310
1277  * deadlock on Armada 375/38x due to hardware I/O coherency). The
1278  * other operations are kept because they are infrequent (therefore do
1279  * not cause the deadlock in practice) and needed for secondary CPU
1280  * boot and other power management activities.
1281  */
1282 static const struct l2c_init_data of_l2c310_coherent_data __initconst = {
1283         .type = "L2C-310 Coherent",
1284         .way_size_0 = SZ_8K,
1285         .num_lock = 8,
1286         .of_parse = l2c310_of_parse,
1287         .enable = l2c310_enable,
1288         .fixup = l2c310_fixup,
1289         .save  = l2c310_save,
1290         .configure = l2c310_configure,
1291         .unlock = l2c310_unlock,
1292         .outer_cache = {
1293                 .inv_range   = l2c210_inv_range,
1294                 .clean_range = l2c210_clean_range,
1295                 .flush_range = l2c210_flush_range,
1296                 .flush_all   = l2c210_flush_all,
1297                 .disable     = l2c310_disable,
1298                 .resume      = l2c310_resume,
1299         },
1300 };
1301
1302 /*
1303  * Note that the end addresses passed to Linux primitives are
1304  * noninclusive, while the hardware cache range operations use
1305  * inclusive start and end addresses.
1306  */
1307 static unsigned long aurora_range_end(unsigned long start, unsigned long end)
1308 {
1309         /*
1310          * Limit the number of cache lines processed at once,
1311          * since cache range operations stall the CPU pipeline
1312          * until completion.
1313          */
1314         if (end > start + MAX_RANGE_SIZE)
1315                 end = start + MAX_RANGE_SIZE;
1316
1317         /*
1318          * Cache range operations can't straddle a page boundary.
1319          */
1320         if (end > PAGE_ALIGN(start+1))
1321                 end = PAGE_ALIGN(start+1);
1322
1323         return end;
1324 }
1325
1326 static void aurora_pa_range(unsigned long start, unsigned long end,
1327                             unsigned long offset)
1328 {
1329         void __iomem *base = l2x0_base;
1330         unsigned long range_end;
1331         unsigned long flags;
1332
1333         /*
1334          * round start and end adresses up to cache line size
1335          */
1336         start &= ~(CACHE_LINE_SIZE - 1);
1337         end = ALIGN(end, CACHE_LINE_SIZE);
1338
1339         /*
1340          * perform operation on all full cache lines between 'start' and 'end'
1341          */
1342         while (start < end) {
1343                 range_end = aurora_range_end(start, end);
1344
1345                 raw_spin_lock_irqsave(&l2x0_lock, flags);
1346                 writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG);
1347                 writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset);
1348                 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1349
1350                 writel_relaxed(0, base + AURORA_SYNC_REG);
1351                 start = range_end;
1352         }
1353 }
1354 static void aurora_inv_range(unsigned long start, unsigned long end)
1355 {
1356         aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
1357 }
1358
1359 static void aurora_clean_range(unsigned long start, unsigned long end)
1360 {
1361         /*
1362          * If L2 is forced to WT, the L2 will always be clean and we
1363          * don't need to do anything here.
1364          */
1365         if (!l2_wt_override)
1366                 aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG);
1367 }
1368
1369 static void aurora_flush_range(unsigned long start, unsigned long end)
1370 {
1371         if (l2_wt_override)
1372                 aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
1373         else
1374                 aurora_pa_range(start, end, AURORA_FLUSH_RANGE_REG);
1375 }
1376
1377 static void aurora_flush_all(void)
1378 {
1379         void __iomem *base = l2x0_base;
1380         unsigned long flags;
1381
1382         /* clean all ways */
1383         raw_spin_lock_irqsave(&l2x0_lock, flags);
1384         __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
1385         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1386
1387         writel_relaxed(0, base + AURORA_SYNC_REG);
1388 }
1389
1390 static void aurora_cache_sync(void)
1391 {
1392         writel_relaxed(0, l2x0_base + AURORA_SYNC_REG);
1393 }
1394
1395 static void aurora_disable(void)
1396 {
1397         void __iomem *base = l2x0_base;
1398         unsigned long flags;
1399
1400         raw_spin_lock_irqsave(&l2x0_lock, flags);
1401         __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
1402         writel_relaxed(0, base + AURORA_SYNC_REG);
1403         l2c_write_sec(0, base, L2X0_CTRL);
1404         dsb(st);
1405         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1406 }
1407
1408 static void aurora_save(void __iomem *base)
1409 {
1410         l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
1411         l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL);
1412 }
1413
1414 /*
1415  * For Aurora cache in no outer mode, enable via the CP15 coprocessor
1416  * broadcasting of cache commands to L2.
1417  */
1418 static void __init aurora_enable_no_outer(void __iomem *base,
1419         unsigned num_lock)
1420 {
1421         u32 u;
1422
1423         asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
1424         u |= AURORA_CTRL_FW;            /* Set the FW bit */
1425         asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
1426
1427         isb();
1428
1429         l2c_enable(base, num_lock);
1430 }
1431
1432 static void __init aurora_fixup(void __iomem *base, u32 cache_id,
1433         struct outer_cache_fns *fns)
1434 {
1435         sync_reg_offset = AURORA_SYNC_REG;
1436 }
1437
1438 static void __init aurora_of_parse(const struct device_node *np,
1439                                 u32 *aux_val, u32 *aux_mask)
1440 {
1441         u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
1442         u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
1443
1444         of_property_read_u32(np, "cache-id-part",
1445                         &cache_id_part_number_from_dt);
1446
1447         /* Determine and save the write policy */
1448         l2_wt_override = of_property_read_bool(np, "wt-override");
1449
1450         if (l2_wt_override) {
1451                 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
1452                 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
1453         }
1454
1455         *aux_val &= ~mask;
1456         *aux_val |= val;
1457         *aux_mask &= ~mask;
1458 }
1459
1460 static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
1461         .type = "Aurora",
1462         .way_size_0 = SZ_4K,
1463         .num_lock = 4,
1464         .of_parse = aurora_of_parse,
1465         .enable = l2c_enable,
1466         .fixup = aurora_fixup,
1467         .save  = aurora_save,
1468         .configure = l2c_configure,
1469         .unlock = l2c_unlock,
1470         .outer_cache = {
1471                 .inv_range   = aurora_inv_range,
1472                 .clean_range = aurora_clean_range,
1473                 .flush_range = aurora_flush_range,
1474                 .flush_all   = aurora_flush_all,
1475                 .disable     = aurora_disable,
1476                 .sync        = aurora_cache_sync,
1477                 .resume      = l2c_resume,
1478         },
1479 };
1480
1481 static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
1482         .type = "Aurora",
1483         .way_size_0 = SZ_4K,
1484         .num_lock = 4,
1485         .of_parse = aurora_of_parse,
1486         .enable = aurora_enable_no_outer,
1487         .fixup = aurora_fixup,
1488         .save  = aurora_save,
1489         .configure = l2c_configure,
1490         .unlock = l2c_unlock,
1491         .outer_cache = {
1492                 .resume      = l2c_resume,
1493         },
1494 };
1495
1496 /*
1497  * For certain Broadcom SoCs, depending on the address range, different offsets
1498  * need to be added to the address before passing it to L2 for
1499  * invalidation/clean/flush
1500  *
1501  * Section Address Range              Offset        EMI
1502  *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
1503  *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
1504  *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC
1505  *
1506  * When the start and end addresses have crossed two different sections, we
1507  * need to break the L2 operation into two, each within its own section.
1508  * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
1509  * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
1510  * 0xC0000000 - 0xC0001000
1511  *
1512  * Note 1:
1513  * By breaking a single L2 operation into two, we may potentially suffer some
1514  * performance hit, but keep in mind the cross section case is very rare
1515  *
1516  * Note 2:
1517  * We do not need to handle the case when the start address is in
1518  * Section 1 and the end address is in Section 3, since it is not a valid use
1519  * case
1520  *
1521  * Note 3:
1522  * Section 1 in practical terms can no longer be used on rev A2. Because of
1523  * that the code does not need to handle section 1 at all.
1524  *
1525  */
1526 #define BCM_SYS_EMI_START_ADDR        0x40000000UL
1527 #define BCM_VC_EMI_SEC3_START_ADDR    0xC0000000UL
1528
1529 #define BCM_SYS_EMI_OFFSET            0x40000000UL
1530 #define BCM_VC_EMI_OFFSET             0x80000000UL
1531
1532 static inline int bcm_addr_is_sys_emi(unsigned long addr)
1533 {
1534         return (addr >= BCM_SYS_EMI_START_ADDR) &&
1535                 (addr < BCM_VC_EMI_SEC3_START_ADDR);
1536 }
1537
1538 static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
1539 {
1540         if (bcm_addr_is_sys_emi(addr))
1541                 return addr + BCM_SYS_EMI_OFFSET;
1542         else
1543                 return addr + BCM_VC_EMI_OFFSET;
1544 }
1545
1546 static void bcm_inv_range(unsigned long start, unsigned long end)
1547 {
1548         unsigned long new_start, new_end;
1549
1550         BUG_ON(start < BCM_SYS_EMI_START_ADDR);
1551
1552         if (unlikely(end <= start))
1553                 return;
1554
1555         new_start = bcm_l2_phys_addr(start);
1556         new_end = bcm_l2_phys_addr(end);
1557
1558         /* normal case, no cross section between start and end */
1559         if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
1560                 l2c210_inv_range(new_start, new_end);
1561                 return;
1562         }
1563
1564         /* They cross sections, so it can only be a cross from section
1565          * 2 to section 3
1566          */
1567         l2c210_inv_range(new_start,
1568                 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
1569         l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
1570                 new_end);
1571 }
1572
1573 static void bcm_clean_range(unsigned long start, unsigned long end)
1574 {
1575         unsigned long new_start, new_end;
1576
1577         BUG_ON(start < BCM_SYS_EMI_START_ADDR);
1578
1579         if (unlikely(end <= start))
1580                 return;
1581
1582         new_start = bcm_l2_phys_addr(start);
1583         new_end = bcm_l2_phys_addr(end);
1584
1585         /* normal case, no cross section between start and end */
1586         if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
1587                 l2c210_clean_range(new_start, new_end);
1588                 return;
1589         }
1590
1591         /* They cross sections, so it can only be a cross from section
1592          * 2 to section 3
1593          */
1594         l2c210_clean_range(new_start,
1595                 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
1596         l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
1597                 new_end);
1598 }
1599
1600 static void bcm_flush_range(unsigned long start, unsigned long end)
1601 {
1602         unsigned long new_start, new_end;
1603
1604         BUG_ON(start < BCM_SYS_EMI_START_ADDR);
1605
1606         if (unlikely(end <= start))
1607                 return;
1608
1609         if ((end - start) >= l2x0_size) {
1610                 outer_cache.flush_all();
1611                 return;
1612         }
1613
1614         new_start = bcm_l2_phys_addr(start);
1615         new_end = bcm_l2_phys_addr(end);
1616
1617         /* normal case, no cross section between start and end */
1618         if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
1619                 l2c210_flush_range(new_start, new_end);
1620                 return;
1621         }
1622
1623         /* They cross sections, so it can only be a cross from section
1624          * 2 to section 3
1625          */
1626         l2c210_flush_range(new_start,
1627                 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
1628         l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
1629                 new_end);
1630 }
1631
1632 /* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */
1633 static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
1634         .type = "BCM-L2C-310",
1635         .way_size_0 = SZ_8K,
1636         .num_lock = 8,
1637         .of_parse = l2c310_of_parse,
1638         .enable = l2c310_enable,
1639         .save  = l2c310_save,
1640         .configure = l2c310_configure,
1641         .unlock = l2c310_unlock,
1642         .outer_cache = {
1643                 .inv_range   = bcm_inv_range,
1644                 .clean_range = bcm_clean_range,
1645                 .flush_range = bcm_flush_range,
1646                 .flush_all   = l2c210_flush_all,
1647                 .disable     = l2c310_disable,
1648                 .sync        = l2c210_sync,
1649                 .resume      = l2c310_resume,
1650         },
1651 };
1652
1653 static void __init tauros3_save(void __iomem *base)
1654 {
1655         l2c_save(base);
1656
1657         l2x0_saved_regs.aux2_ctrl =
1658                 readl_relaxed(base + TAUROS3_AUX2_CTRL);
1659         l2x0_saved_regs.prefetch_ctrl =
1660                 readl_relaxed(base + L310_PREFETCH_CTRL);
1661 }
1662
1663 static void tauros3_configure(void __iomem *base)
1664 {
1665         l2c_configure(base);
1666         writel_relaxed(l2x0_saved_regs.aux2_ctrl,
1667                        base + TAUROS3_AUX2_CTRL);
1668         writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
1669                        base + L310_PREFETCH_CTRL);
1670 }
1671
1672 static const struct l2c_init_data of_tauros3_data __initconst = {
1673         .type = "Tauros3",
1674         .way_size_0 = SZ_8K,
1675         .num_lock = 8,
1676         .enable = l2c_enable,
1677         .save  = tauros3_save,
1678         .configure = tauros3_configure,
1679         .unlock = l2c_unlock,
1680         /* Tauros3 broadcasts L1 cache operations to L2 */
1681         .outer_cache = {
1682                 .resume      = l2c_resume,
1683         },
1684 };
1685
1686 #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns }
1687 static const struct of_device_id l2x0_ids[] __initconst = {
1688         L2C_ID("arm,l210-cache", of_l2c210_data),
1689         L2C_ID("arm,l220-cache", of_l2c220_data),
1690         L2C_ID("arm,pl310-cache", of_l2c310_data),
1691         L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
1692         L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data),
1693         L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data),
1694         L2C_ID("marvell,tauros3-cache", of_tauros3_data),
1695         /* Deprecated IDs */
1696         L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
1697         {}
1698 };
1699
1700 int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
1701 {
1702         const struct l2c_init_data *data;
1703         struct device_node *np;
1704         struct resource res;
1705         u32 cache_id, old_aux;
1706         u32 cache_level = 2;
1707
1708         np = of_find_matching_node(NULL, l2x0_ids);
1709         if (!np)
1710                 return -ENODEV;
1711
1712         if (of_address_to_resource(np, 0, &res))
1713                 return -ENODEV;
1714
1715         l2x0_base = ioremap(res.start, resource_size(&res));
1716         if (!l2x0_base)
1717                 return -ENOMEM;
1718
1719         l2x0_saved_regs.phy_base = res.start;
1720
1721         data = of_match_node(l2x0_ids, np)->data;
1722
1723         if (of_device_is_compatible(np, "arm,pl310-cache") &&
1724             of_property_read_bool(np, "arm,io-coherent"))
1725                 data = &of_l2c310_coherent_data;
1726
1727         old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
1728         if (old_aux != ((old_aux & aux_mask) | aux_val)) {
1729                 pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n",
1730                         old_aux, (old_aux & aux_mask) | aux_val);
1731         } else if (aux_mask != ~0U && aux_val != 0) {
1732                 pr_alert("L2C: platform provided aux values match the hardware, so have no effect.  Please remove them.\n");
1733         }
1734
1735         /* All L2 caches are unified, so this property should be specified */
1736         if (!of_property_read_bool(np, "cache-unified"))
1737                 pr_err("L2C: device tree omits to specify unified cache\n");
1738
1739         if (of_property_read_u32(np, "cache-level", &cache_level))
1740                 pr_err("L2C: device tree omits to specify cache-level\n");
1741
1742         if (cache_level != 2)
1743                 pr_err("L2C: device tree specifies invalid cache level\n");
1744
1745         /* Read back current (default) hardware configuration */
1746         if (data->save)
1747                 data->save(l2x0_base);
1748
1749         /* L2 configuration can only be changed if the cache is disabled */
1750         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
1751                 if (data->of_parse)
1752                         data->of_parse(np, &aux_val, &aux_mask);
1753
1754         if (cache_id_part_number_from_dt)
1755                 cache_id = cache_id_part_number_from_dt;
1756         else
1757                 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
1758
1759         return __l2c_init(data, aux_val, aux_mask, cache_id);
1760 }
1761 #endif