arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h

   1 /* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *      Ben Dooks <ben@simtec.co.uk>
   7  *
   8  * S3C - USB2.0 Highspeed/OtG device PHY registers
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 /* Note, this is a separate header file as some of the clock framework
  16  * needs to touch this if the clk_48m is used as the USB OHCI or other
  17  * peripheral source.
  18 */
  19
  20 #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
  21 #define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
  22
  23 /* S3C64XX_PA_USB_HSPHY */
  24
  25 #define S3C_HSOTG_PHYREG(x)     ((x) + S3C_VA_USB_HSPHY)
  26
  27 #define S3C_PHYPWR                              S3C_HSOTG_PHYREG(0x00)
  28 #define S3C_PHYPWR_NORMAL_MASK                  (0x19 << 0)
  29 #define S3C_PHYPWR_OTG_DISABLE                  (1 << 4)
  30 #define S3C_PHYPWR_ANALOG_POWERDOWN             (1 << 3)
  31 #define SRC_PHYPWR_FORCE_SUSPEND                (1 << 1)
  32
  33 #define S3C_PHYCLK                              S3C_HSOTG_PHYREG(0x04)
  34 #define S3C_PHYCLK_MODE_USB11                   (1 << 6)
  35 #define S3C_PHYCLK_EXT_OSC                      (1 << 5)
  36 #define S3C_PHYCLK_CLK_FORCE                    (1 << 4)
  37 #define S3C_PHYCLK_ID_PULL                      (1 << 2)
  38 #define S3C_PHYCLK_CLKSEL_MASK                  (0x3 << 0)
  39 #define S3C_PHYCLK_CLKSEL_SHIFT                 (0)
  40 #define S3C_PHYCLK_CLKSEL_48M                   (0x0 << 0)
  41 #define S3C_PHYCLK_CLKSEL_12M                   (0x2 << 0)
  42 #define S3C_PHYCLK_CLKSEL_24M                   (0x3 << 0)
  43
  44 #define S3C_RSTCON                              S3C_HSOTG_PHYREG(0x08)
  45 #define S3C_RSTCON_PHYCLK                       (1 << 2)
  46 #define S3C_RSTCON_HCLK                         (1 << 1)
  47 #define S3C_RSTCON_PHY                          (1 << 0)
  48
  49 #define S3C_PHYTUNE                             S3C_HSOTG_PHYREG(0x20)
  50
  51 #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */