3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
30 select GENERIC_ALLOCATOR
31 select GENERIC_CLOCKEVENTS
32 select GENERIC_CLOCKEVENTS_BROADCAST
33 select GENERIC_CPU_AUTOPROBE
34 select GENERIC_EARLY_IOREMAP
35 select GENERIC_IDLE_POLL_SETUP
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select GENERIC_IRQ_SHOW_LEVEL
39 select GENERIC_PCI_IOMAP
40 select GENERIC_SCHED_CLOCK
41 select GENERIC_SMP_IDLE_THREAD
42 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
44 select GENERIC_TIME_VSYSCALL
45 select HANDLE_DOMAIN_IRQ
46 select HARDIRQS_SW_RESEND
47 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
48 select HAVE_ARCH_AUDITSYSCALL
49 select HAVE_ARCH_BITREVERSE
50 select HAVE_ARCH_JUMP_LABEL
52 select HAVE_ARCH_SECCOMP_FILTER
53 select HAVE_ARCH_TRACEHOOK
55 select HAVE_C_RECORDMCOUNT
56 select HAVE_CC_STACKPROTECTOR
57 select HAVE_CMPXCHG_DOUBLE
58 select HAVE_CMPXCHG_LOCAL
59 select HAVE_DEBUG_BUGVERBOSE
60 select HAVE_DEBUG_KMEMLEAK
61 select HAVE_DMA_API_DEBUG
63 select HAVE_DMA_CONTIGUOUS
64 select HAVE_DYNAMIC_FTRACE
65 select HAVE_EFFICIENT_UNALIGNED_ACCESS
66 select HAVE_FTRACE_MCOUNT_RECORD
67 select HAVE_FUNCTION_TRACER
68 select HAVE_FUNCTION_GRAPH_TRACER
69 select HAVE_GENERIC_DMA_COHERENT
70 select HAVE_HW_BREAKPOINT if PERF_EVENTS
72 select HAVE_PATA_PLATFORM
73 select HAVE_PERF_EVENTS
75 select HAVE_PERF_USER_STACK_DUMP
76 select HAVE_RCU_TABLE_FREE
77 select HAVE_SYSCALL_TRACEPOINTS
78 select IOMMU_DMA if IOMMU_SUPPORT
80 select IRQ_FORCED_THREADING
81 select MODULES_USE_ELF_RELA
84 select OF_EARLY_FLATTREE
85 select OF_RESERVED_MEM
86 select PERF_USE_VMALLOC
91 select SYSCTL_EXCEPTION_TRACE
92 select HAVE_CONTEXT_TRACKING
94 ARM 64-bit (AArch64) Linux support.
99 config ARCH_PHYS_ADDR_T_64BIT
108 config STACKTRACE_SUPPORT
111 config ILLEGAL_POINTER_VALUE
113 default 0xdead000000000000
115 config LOCKDEP_SUPPORT
118 config TRACE_IRQFLAGS_SUPPORT
121 config RWSEM_XCHGADD_ALGORITHM
128 config GENERIC_BUG_RELATIVE_POINTERS
130 depends on GENERIC_BUG
132 config GENERIC_HWEIGHT
138 config GENERIC_CALIBRATE_DELAY
144 config HAVE_GENERIC_RCU_GUP
147 config ARCH_DMA_ADDR_T_64BIT
150 config NEED_DMA_MAP_STATE
153 config NEED_SG_DMA_LENGTH
165 config KERNEL_MODE_NEON
168 config FIX_EARLYCON_MEM
171 config PGTABLE_LEVELS
173 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
174 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
175 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
176 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
178 source "init/Kconfig"
180 source "kernel/Kconfig.freezer"
182 source "arch/arm64/Kconfig.platforms"
189 This feature enables support for PCI bus system. If you say Y
190 here, the kernel will include drivers and infrastructure code
191 to support PCI bus devices.
196 config PCI_DOMAINS_GENERIC
202 source "drivers/pci/Kconfig"
203 source "drivers/pci/pcie/Kconfig"
204 source "drivers/pci/hotplug/Kconfig"
208 menu "Kernel Features"
210 menu "ARM errata workarounds via the alternatives framework"
212 config ARM64_ERRATUM_826319
213 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
216 This option adds an alternative code sequence to work around ARM
217 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
218 AXI master interface and an L2 cache.
220 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
221 and is unable to accept a certain write via this interface, it will
222 not progress on read data presented on the read data channel and the
225 The workaround promotes data cache clean instructions to
226 data cache clean-and-invalidate.
227 Please note that this does not necessarily enable the workaround,
228 as it depends on the alternative framework, which will only patch
229 the kernel if an affected CPU is detected.
233 config ARM64_ERRATUM_827319
234 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
237 This option adds an alternative code sequence to work around ARM
238 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
239 master interface and an L2 cache.
241 Under certain conditions this erratum can cause a clean line eviction
242 to occur at the same time as another transaction to the same address
243 on the AMBA 5 CHI interface, which can cause data corruption if the
244 interconnect reorders the two transactions.
246 The workaround promotes data cache clean instructions to
247 data cache clean-and-invalidate.
248 Please note that this does not necessarily enable the workaround,
249 as it depends on the alternative framework, which will only patch
250 the kernel if an affected CPU is detected.
254 config ARM64_ERRATUM_824069
255 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
258 This option adds an alternative code sequence to work around ARM
259 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
260 to a coherent interconnect.
262 If a Cortex-A53 processor is executing a store or prefetch for
263 write instruction at the same time as a processor in another
264 cluster is executing a cache maintenance operation to the same
265 address, then this erratum might cause a clean cache line to be
266 incorrectly marked as dirty.
268 The workaround promotes data cache clean instructions to
269 data cache clean-and-invalidate.
270 Please note that this option does not necessarily enable the
271 workaround, as it depends on the alternative framework, which will
272 only patch the kernel if an affected CPU is detected.
276 config ARM64_ERRATUM_819472
277 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
280 This option adds an alternative code sequence to work around ARM
281 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
282 present when it is connected to a coherent interconnect.
284 If the processor is executing a load and store exclusive sequence at
285 the same time as a processor in another cluster is executing a cache
286 maintenance operation to the same address, then this erratum might
287 cause data corruption.
289 The workaround promotes data cache clean instructions to
290 data cache clean-and-invalidate.
291 Please note that this does not necessarily enable the workaround,
292 as it depends on the alternative framework, which will only patch
293 the kernel if an affected CPU is detected.
297 config ARM64_ERRATUM_832075
298 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
301 This option adds an alternative code sequence to work around ARM
302 erratum 832075 on Cortex-A57 parts up to r1p2.
304 Affected Cortex-A57 parts might deadlock when exclusive load/store
305 instructions to Write-Back memory are mixed with Device loads.
307 The workaround is to promote device loads to use Load-Acquire
309 Please note that this does not necessarily enable the workaround,
310 as it depends on the alternative framework, which will only patch
311 the kernel if an affected CPU is detected.
315 config ARM64_ERRATUM_845719
316 bool "Cortex-A53: 845719: a load might read incorrect data"
320 This option adds an alternative code sequence to work around ARM
321 erratum 845719 on Cortex-A53 parts up to r0p4.
323 When running a compat (AArch32) userspace on an affected Cortex-A53
324 part, a load at EL0 from a virtual address that matches the bottom 32
325 bits of the virtual address used by a recent load at (AArch64) EL1
326 might return incorrect data.
328 The workaround is to write the contextidr_el1 register on exception
329 return to a 32-bit task.
330 Please note that this does not necessarily enable the workaround,
331 as it depends on the alternative framework, which will only patch
332 the kernel if an affected CPU is detected.
336 config ARM64_ERRATUM_843419
337 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
341 This option builds kernel modules using the large memory model in
342 order to avoid the use of the ADRP instruction, which can cause
343 a subsequent memory access to use an incorrect address on Cortex-A53
346 Note that the kernel itself must be linked with a version of ld
347 which fixes potentially affected ADRP instructions through the
357 default ARM64_4K_PAGES
359 Page size (translation granule) configuration.
361 config ARM64_4K_PAGES
364 This feature enables 4KB pages support.
366 config ARM64_64K_PAGES
369 This feature enables 64KB pages support (4KB by default)
370 allowing only two levels of page tables and faster TLB
371 look-up. AArch32 emulation is not available when this feature
377 prompt "Virtual address space size"
378 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
379 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
381 Allows choosing one of multiple possible virtual address
382 space sizes. The level of translation table is determined by
383 a combination of page size and virtual address space size.
385 config ARM64_VA_BITS_39
387 depends on ARM64_4K_PAGES
389 config ARM64_VA_BITS_42
391 depends on ARM64_64K_PAGES
393 config ARM64_VA_BITS_48
400 default 39 if ARM64_VA_BITS_39
401 default 42 if ARM64_VA_BITS_42
402 default 48 if ARM64_VA_BITS_48
404 config CPU_BIG_ENDIAN
405 bool "Build big-endian kernel"
407 Say Y if you plan on running a kernel in big-endian mode.
410 bool "Multi-core scheduler support"
412 Multi-core scheduler support improves the CPU scheduler's decision
413 making when dealing with multi-core CPU chips at a cost of slightly
414 increased overhead in some places. If unsure say N here.
417 bool "SMT scheduler support"
419 Improves the CPU scheduler's decision making when dealing with
420 MultiThreading at a cost of slightly increased overhead in some
421 places. If unsure say N here.
424 int "Maximum number of CPUs (2-4096)"
426 # These have to remain sorted largest to smallest
430 bool "Support for hot-pluggable CPUs"
432 Say Y here to experiment with turning CPUs off and on. CPUs
433 can be controlled through /sys/devices/system/cpu.
435 source kernel/Kconfig.preempt
441 config ARCH_HAS_HOLES_MEMORYMODEL
442 def_bool y if SPARSEMEM
444 config ARCH_SPARSEMEM_ENABLE
446 select SPARSEMEM_VMEMMAP_ENABLE
448 config ARCH_SPARSEMEM_DEFAULT
449 def_bool ARCH_SPARSEMEM_ENABLE
451 config ARCH_SELECT_MEMORY_MODEL
452 def_bool ARCH_SPARSEMEM_ENABLE
454 config HAVE_ARCH_PFN_VALID
455 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
457 config HW_PERF_EVENTS
458 bool "Enable hardware performance counter support for perf events"
459 depends on PERF_EVENTS
462 Enable hardware performance counter support for perf events. If
463 disabled, perf events will use software events only.
465 config SYS_SUPPORTS_HUGETLBFS
468 config ARCH_WANT_GENERAL_HUGETLB
471 config ARCH_WANT_HUGE_PMD_SHARE
472 def_bool y if !ARM64_64K_PAGES
474 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
477 config ARCH_HAS_CACHE_LINE_SIZE
483 bool "Enable seccomp to safely compute untrusted bytecode"
485 This kernel feature is useful for number crunching applications
486 that may need to compute untrusted bytecode during their
487 execution. By using pipes or other transports made available to
488 the process as file descriptors supporting the read/write
489 syscalls, it's possible to isolate those applications in
490 their own address space using seccomp. Once seccomp is
491 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
492 and the task is only allowed to execute a few safe syscalls
493 defined by each seccomp mode.
500 bool "Xen guest support on ARM64"
501 depends on ARM64 && OF
504 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
506 config FORCE_MAX_ZONEORDER
508 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
511 menuconfig ARMV8_DEPRECATED
512 bool "Emulate deprecated/obsolete ARMv8 instructions"
515 Legacy software support may require certain instructions
516 that have been deprecated or obsoleted in the architecture.
518 Enable this config to enable selective emulation of these
526 bool "Emulate SWP/SWPB instructions"
528 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
529 they are always undefined. Say Y here to enable software
530 emulation of these instructions for userspace using LDXR/STXR.
532 In some older versions of glibc [<=2.8] SWP is used during futex
533 trylock() operations with the assumption that the code will not
534 be preempted. This invalid assumption may be more likely to fail
535 with SWP emulation enabled, leading to deadlock of the user
538 NOTE: when accessing uncached shared regions, LDXR/STXR rely
539 on an external transaction monitoring block called a global
540 monitor to maintain update atomicity. If your system does not
541 implement a global monitor, this option can cause programs that
542 perform SWP operations to uncached memory to deadlock.
546 config CP15_BARRIER_EMULATION
547 bool "Emulate CP15 Barrier instructions"
549 The CP15 barrier instructions - CP15ISB, CP15DSB, and
550 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
551 strongly recommended to use the ISB, DSB, and DMB
552 instructions instead.
554 Say Y here to enable software emulation of these
555 instructions for AArch32 userspace code. When this option is
556 enabled, CP15 barrier usage is traced which can help
557 identify software that needs updating.
561 config SETEND_EMULATION
562 bool "Emulate SETEND instruction"
564 The SETEND instruction alters the data-endianness of the
565 AArch32 EL0, and is deprecated in ARMv8.
567 Say Y here to enable software emulation of the instruction
568 for AArch32 userspace code.
570 Note: All the cpus on the system must have mixed endian support at EL0
571 for this feature to be enabled. If a new CPU - which doesn't support mixed
572 endian - is hotplugged in after this feature has been enabled, there could
573 be unexpected results in the applications.
578 menu "ARMv8.1 architectural features"
580 config ARM64_HW_AFDBM
581 bool "Support for hardware updates of the Access and Dirty page flags"
584 The ARMv8.1 architecture extensions introduce support for
585 hardware updates of the access and dirty information in page
586 table entries. When enabled in TCR_EL1 (HA and HD bits) on
587 capable processors, accesses to pages with PTE_AF cleared will
588 set this bit instead of raising an access flag fault.
589 Similarly, writes to read-only pages with the DBM bit set will
590 clear the read-only bit (AP[2]) instead of raising a
593 Kernels built with this configuration option enabled continue
594 to work on pre-ARMv8.1 hardware and the performance impact is
595 minimal. If unsure, say Y.
598 bool "Enable support for Privileged Access Never (PAN)"
601 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
602 prevents the kernel or hypervisor from accessing user-space (EL0)
605 Choosing this option will cause any unprotected (not using
606 copy_to_user et al) memory access to fail with a permission fault.
608 The feature is detected at runtime, and will remain as a 'nop'
609 instruction if the cpu does not implement the feature.
611 config ARM64_LSE_ATOMICS
612 bool "Atomic instructions"
614 As part of the Large System Extensions, ARMv8.1 introduces new
615 atomic instructions that are designed specifically to scale in
618 Say Y here to make use of these instructions for the in-kernel
619 atomic routines. This incurs a small overhead on CPUs that do
620 not support these instructions and requires the kernel to be
621 built with binutils >= 2.25.
630 string "Default kernel command string"
633 Provide a set of default command-line options at build time by
634 entering them here. As a minimum, you should specify the the
635 root device (e.g. root=/dev/nfs).
638 bool "Always use the default kernel command string"
640 Always use the default kernel command string, even if the boot
641 loader passes other arguments to the kernel.
642 This is useful if you cannot or don't want to change the
643 command-line options your boot loader passes to the kernel.
649 bool "UEFI runtime support"
650 depends on OF && !CPU_BIG_ENDIAN
653 select EFI_PARAMS_FROM_FDT
654 select EFI_RUNTIME_WRAPPERS
659 This option provides support for runtime services provided
660 by UEFI firmware (such as non-volatile variables, realtime
661 clock, and platform reset). A UEFI stub is also provided to
662 allow the kernel to be booted as an EFI application. This
663 is only useful on systems that have UEFI firmware.
666 bool "Enable support for SMBIOS (DMI) tables"
670 This enables SMBIOS/DMI feature for systems.
672 This option is only useful on systems that have UEFI firmware.
673 However, even with this option, the resultant kernel should
674 continue to boot on existing non-UEFI platforms.
678 menu "Userspace binary formats"
680 source "fs/Kconfig.binfmt"
683 bool "Kernel support for 32-bit EL0"
684 depends on !ARM64_64K_PAGES || EXPERT
685 select COMPAT_BINFMT_ELF
687 select OLD_SIGSUSPEND3
688 select COMPAT_OLD_SIGACTION
690 This option enables support for a 32-bit EL0 running under a 64-bit
691 kernel at EL1. AArch32-specific components such as system calls,
692 the user helper functions, VFP support and the ptrace interface are
693 handled appropriately by the kernel.
695 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
696 will only be able to execute AArch32 binaries that were compiled with
697 64k aligned segments.
699 If you want to execute 32-bit userspace applications, say Y.
701 config SYSVIPC_COMPAT
703 depends on COMPAT && SYSVIPC
707 menu "Power management options"
709 source "kernel/power/Kconfig"
711 config ARCH_SUSPEND_POSSIBLE
716 menu "CPU Power Management"
718 source "drivers/cpuidle/Kconfig"
720 source "drivers/cpufreq/Kconfig"
726 source "drivers/Kconfig"
728 source "drivers/firmware/Kconfig"
730 source "drivers/acpi/Kconfig"
734 source "arch/arm64/kvm/Kconfig"
736 source "arch/arm64/Kconfig.debug"
738 source "security/Kconfig"
740 source "crypto/Kconfig"
742 source "arch/arm64/crypto/Kconfig"