2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,potenza", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,potenza", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,potenza", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,potenza", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,potenza", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,potenza", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,potenza", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
101 compatible = "simple-bus";
102 #address-cells = <2>;
105 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
108 #address-cells = <2>;
112 compatible = "fixed-clock";
114 clock-frequency = <100000000>;
115 clock-output-names = "refclk";
118 pcppll: pcppll@17000100 {
119 compatible = "apm,xgene-pcppll-clock";
121 clocks = <&refclk 0>;
122 clock-names = "pcppll";
123 reg = <0x0 0x17000100 0x0 0x1000>;
124 clock-output-names = "pcppll";
128 socpll: socpll@17000120 {
129 compatible = "apm,xgene-socpll-clock";
131 clocks = <&refclk 0>;
132 clock-names = "socpll";
133 reg = <0x0 0x17000120 0x0 0x1000>;
134 clock-output-names = "socpll";
138 socplldiv2: socplldiv2 {
139 compatible = "fixed-factor-clock";
141 clocks = <&socpll 0>;
142 clock-names = "socplldiv2";
145 clock-output-names = "socplldiv2";
149 compatible = "apm,xgene-device-clock";
151 clocks = <&socplldiv2 0>;
152 clock-names = "qmlclk";
153 reg = <0x0 0x1703C000 0x0 0x1000>;
154 reg-names = "csr-reg";
155 clock-output-names = "qmlclk";
159 compatible = "apm,xgene-device-clock";
161 clocks = <&socplldiv2 0>;
162 clock-names = "ethclk";
163 reg = <0x0 0x17000000 0x0 0x1000>;
164 reg-names = "div-reg";
165 divider-offset = <0x238>;
166 divider-width = <0x9>;
167 divider-shift = <0x0>;
168 clock-output-names = "ethclk";
172 compatible = "apm,xgene-device-clock";
174 clocks = <ðclk 0>;
175 reg = <0x0 0x1702C000 0x0 0x1000>;
176 reg-names = "csr-reg";
177 clock-output-names = "menetclk";
180 sge0clk: sge0clk@1f21c000 {
181 compatible = "apm,xgene-device-clock";
183 clocks = <&socplldiv2 0>;
184 reg = <0x0 0x1f21c000 0x0 0x1000>;
185 reg-names = "csr-reg";
187 clock-output-names = "sge0clk";
190 sge1clk: sge1clk@1f21c000 {
191 compatible = "apm,xgene-device-clock";
193 clocks = <&socplldiv2 0>;
194 reg = <0x0 0x1f21c000 0x0 0x1000>;
195 reg-names = "csr-reg";
197 clock-output-names = "sge1clk";
200 xge0clk: xge0clk@1f61c000 {
201 compatible = "apm,xgene-device-clock";
203 clocks = <&socplldiv2 0>;
204 reg = <0x0 0x1f61c000 0x0 0x1000>;
205 reg-names = "csr-reg";
207 clock-output-names = "xge0clk";
210 sataphy1clk: sataphy1clk@1f21c000 {
211 compatible = "apm,xgene-device-clock";
213 clocks = <&socplldiv2 0>;
214 reg = <0x0 0x1f21c000 0x0 0x1000>;
215 reg-names = "csr-reg";
216 clock-output-names = "sataphy1clk";
220 enable-offset = <0x0>;
221 enable-mask = <0x06>;
224 sataphy2clk: sataphy1clk@1f22c000 {
225 compatible = "apm,xgene-device-clock";
227 clocks = <&socplldiv2 0>;
228 reg = <0x0 0x1f22c000 0x0 0x1000>;
229 reg-names = "csr-reg";
230 clock-output-names = "sataphy2clk";
234 enable-offset = <0x0>;
235 enable-mask = <0x06>;
238 sataphy3clk: sataphy1clk@1f23c000 {
239 compatible = "apm,xgene-device-clock";
241 clocks = <&socplldiv2 0>;
242 reg = <0x0 0x1f23c000 0x0 0x1000>;
243 reg-names = "csr-reg";
244 clock-output-names = "sataphy3clk";
248 enable-offset = <0x0>;
249 enable-mask = <0x06>;
252 sata01clk: sata01clk@1f21c000 {
253 compatible = "apm,xgene-device-clock";
255 clocks = <&socplldiv2 0>;
256 reg = <0x0 0x1f21c000 0x0 0x1000>;
257 reg-names = "csr-reg";
258 clock-output-names = "sata01clk";
261 enable-offset = <0x0>;
262 enable-mask = <0x39>;
265 sata23clk: sata23clk@1f22c000 {
266 compatible = "apm,xgene-device-clock";
268 clocks = <&socplldiv2 0>;
269 reg = <0x0 0x1f22c000 0x0 0x1000>;
270 reg-names = "csr-reg";
271 clock-output-names = "sata23clk";
274 enable-offset = <0x0>;
275 enable-mask = <0x39>;
278 sata45clk: sata45clk@1f23c000 {
279 compatible = "apm,xgene-device-clock";
281 clocks = <&socplldiv2 0>;
282 reg = <0x0 0x1f23c000 0x0 0x1000>;
283 reg-names = "csr-reg";
284 clock-output-names = "sata45clk";
287 enable-offset = <0x0>;
288 enable-mask = <0x39>;
291 rtcclk: rtcclk@17000000 {
292 compatible = "apm,xgene-device-clock";
294 clocks = <&socplldiv2 0>;
295 reg = <0x0 0x17000000 0x0 0x2000>;
296 reg-names = "csr-reg";
299 enable-offset = <0x10>;
301 clock-output-names = "rtcclk";
304 rngpkaclk: rngpkaclk@17000000 {
305 compatible = "apm,xgene-device-clock";
307 clocks = <&socplldiv2 0>;
308 reg = <0x0 0x17000000 0x0 0x2000>;
309 reg-names = "csr-reg";
312 enable-offset = <0x10>;
313 enable-mask = <0x10>;
314 clock-output-names = "rngpkaclk";
317 pcie0clk: pcie0clk@1f2bc000 {
319 compatible = "apm,xgene-device-clock";
321 clocks = <&socplldiv2 0>;
322 reg = <0x0 0x1f2bc000 0x0 0x1000>;
323 reg-names = "csr-reg";
324 clock-output-names = "pcie0clk";
327 pcie1clk: pcie1clk@1f2cc000 {
329 compatible = "apm,xgene-device-clock";
331 clocks = <&socplldiv2 0>;
332 reg = <0x0 0x1f2cc000 0x0 0x1000>;
333 reg-names = "csr-reg";
334 clock-output-names = "pcie1clk";
337 pcie2clk: pcie2clk@1f2dc000 {
339 compatible = "apm,xgene-device-clock";
341 clocks = <&socplldiv2 0>;
342 reg = <0x0 0x1f2dc000 0x0 0x1000>;
343 reg-names = "csr-reg";
344 clock-output-names = "pcie2clk";
347 pcie3clk: pcie3clk@1f50c000 {
349 compatible = "apm,xgene-device-clock";
351 clocks = <&socplldiv2 0>;
352 reg = <0x0 0x1f50c000 0x0 0x1000>;
353 reg-names = "csr-reg";
354 clock-output-names = "pcie3clk";
357 pcie4clk: pcie4clk@1f51c000 {
359 compatible = "apm,xgene-device-clock";
361 clocks = <&socplldiv2 0>;
362 reg = <0x0 0x1f51c000 0x0 0x1000>;
363 reg-names = "csr-reg";
364 clock-output-names = "pcie4clk";
367 dmaclk: dmaclk@1f27c000 {
368 compatible = "apm,xgene-device-clock";
370 clocks = <&socplldiv2 0>;
371 reg = <0x0 0x1f27c000 0x0 0x1000>;
372 reg-names = "csr-reg";
373 clock-output-names = "dmaclk";
378 compatible = "apm,xgene1-msi";
380 reg = <0x00 0x79000000 0x0 0x900000>;
381 interrupts = < 0x0 0x10 0x4
400 compatible = "apm,xgene-csw", "syscon";
401 reg = <0x0 0x7e200000 0x0 0x1000>;
404 mcba: mcba@7e700000 {
405 compatible = "apm,xgene-mcb", "syscon";
406 reg = <0x0 0x7e700000 0x0 0x1000>;
409 mcbb: mcbb@7e720000 {
410 compatible = "apm,xgene-mcb", "syscon";
411 reg = <0x0 0x7e720000 0x0 0x1000>;
414 efuse: efuse@1054a000 {
415 compatible = "apm,xgene-efuse", "syscon";
416 reg = <0x0 0x1054a000 0x0 0x20>;
420 compatible = "apm,xgene-edac";
421 #address-cells = <2>;
425 regmap-mcba = <&mcba>;
426 regmap-mcbb = <&mcbb>;
427 regmap-efuse = <&efuse>;
428 reg = <0x0 0x78800000 0x0 0x100>;
429 interrupts = <0x0 0x20 0x4>,
434 compatible = "apm,xgene-edac-mc";
435 reg = <0x0 0x7e800000 0x0 0x1000>;
436 memory-controller = <0>;
440 compatible = "apm,xgene-edac-mc";
441 reg = <0x0 0x7e840000 0x0 0x1000>;
442 memory-controller = <1>;
446 compatible = "apm,xgene-edac-mc";
447 reg = <0x0 0x7e880000 0x0 0x1000>;
448 memory-controller = <2>;
452 compatible = "apm,xgene-edac-mc";
453 reg = <0x0 0x7e8c0000 0x0 0x1000>;
454 memory-controller = <3>;
458 compatible = "apm,xgene-edac-pmd";
459 reg = <0x0 0x7c000000 0x0 0x200000>;
460 pmd-controller = <0>;
464 compatible = "apm,xgene-edac-pmd";
465 reg = <0x0 0x7c200000 0x0 0x200000>;
466 pmd-controller = <1>;
470 compatible = "apm,xgene-edac-pmd";
471 reg = <0x0 0x7c400000 0x0 0x200000>;
472 pmd-controller = <2>;
476 compatible = "apm,xgene-edac-pmd";
477 reg = <0x0 0x7c600000 0x0 0x200000>;
478 pmd-controller = <3>;
482 compatible = "apm,xgene-edac-l3";
483 reg = <0x0 0x7e600000 0x0 0x1000>;
487 compatible = "apm,xgene-edac-soc-v1";
488 reg = <0x0 0x7e930000 0x0 0x1000>;
492 pcie0: pcie@1f2b0000 {
495 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
496 #interrupt-cells = <1>;
498 #address-cells = <3>;
499 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
500 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
501 reg-names = "csr", "cfg";
502 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
503 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
504 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
505 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
506 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
507 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
508 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
509 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
510 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
511 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
513 clocks = <&pcie0clk 0>;
517 pcie1: pcie@1f2c0000 {
520 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
521 #interrupt-cells = <1>;
523 #address-cells = <3>;
524 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
525 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
526 reg-names = "csr", "cfg";
527 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
528 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
529 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
530 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
531 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
532 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
533 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
534 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
535 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
536 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
538 clocks = <&pcie1clk 0>;
542 pcie2: pcie@1f2d0000 {
545 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
546 #interrupt-cells = <1>;
548 #address-cells = <3>;
549 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
550 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
551 reg-names = "csr", "cfg";
552 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
553 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
554 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
555 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
556 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
557 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
558 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
559 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
560 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
561 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
563 clocks = <&pcie2clk 0>;
567 pcie3: pcie@1f500000 {
570 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
571 #interrupt-cells = <1>;
573 #address-cells = <3>;
574 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
575 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
576 reg-names = "csr", "cfg";
577 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
578 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
579 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
580 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
581 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
582 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
583 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
584 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
585 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
586 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
588 clocks = <&pcie3clk 0>;
592 pcie4: pcie@1f510000 {
595 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
596 #interrupt-cells = <1>;
598 #address-cells = <3>;
599 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
600 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
601 reg-names = "csr", "cfg";
602 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
603 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
604 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
605 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
606 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
607 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
608 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
609 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
610 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
611 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
613 clocks = <&pcie4clk 0>;
617 serial0: serial@1c020000 {
619 device_type = "serial";
620 compatible = "ns16550a";
621 reg = <0 0x1c020000 0x0 0x1000>;
623 clock-frequency = <10000000>; /* Updated by bootloader */
624 interrupt-parent = <&gic>;
625 interrupts = <0x0 0x4c 0x4>;
628 serial1: serial@1c021000 {
630 device_type = "serial";
631 compatible = "ns16550a";
632 reg = <0 0x1c021000 0x0 0x1000>;
634 clock-frequency = <10000000>; /* Updated by bootloader */
635 interrupt-parent = <&gic>;
636 interrupts = <0x0 0x4d 0x4>;
639 serial2: serial@1c022000 {
641 device_type = "serial";
642 compatible = "ns16550a";
643 reg = <0 0x1c022000 0x0 0x1000>;
645 clock-frequency = <10000000>; /* Updated by bootloader */
646 interrupt-parent = <&gic>;
647 interrupts = <0x0 0x4e 0x4>;
650 serial3: serial@1c023000 {
652 device_type = "serial";
653 compatible = "ns16550a";
654 reg = <0 0x1c023000 0x0 0x1000>;
656 clock-frequency = <10000000>; /* Updated by bootloader */
657 interrupt-parent = <&gic>;
658 interrupts = <0x0 0x4f 0x4>;
662 compatible = "apm,xgene-phy";
663 reg = <0x0 0x1f21a000 0x0 0x100>;
665 clocks = <&sataphy1clk 0>;
667 apm,tx-boost-gain = <30 30 30 30 30 30>;
668 apm,tx-eye-tuning = <2 10 10 2 10 10>;
672 compatible = "apm,xgene-phy";
673 reg = <0x0 0x1f22a000 0x0 0x100>;
675 clocks = <&sataphy2clk 0>;
677 apm,tx-boost-gain = <30 30 30 30 30 30>;
678 apm,tx-eye-tuning = <1 10 10 2 10 10>;
682 compatible = "apm,xgene-phy";
683 reg = <0x0 0x1f23a000 0x0 0x100>;
685 clocks = <&sataphy3clk 0>;
687 apm,tx-boost-gain = <31 31 31 31 31 31>;
688 apm,tx-eye-tuning = <2 10 10 2 10 10>;
691 sata1: sata@1a000000 {
692 compatible = "apm,xgene-ahci";
693 reg = <0x0 0x1a000000 0x0 0x1000>,
694 <0x0 0x1f210000 0x0 0x1000>,
695 <0x0 0x1f21d000 0x0 0x1000>,
696 <0x0 0x1f21e000 0x0 0x1000>,
697 <0x0 0x1f217000 0x0 0x1000>;
698 interrupts = <0x0 0x86 0x4>;
701 clocks = <&sata01clk 0>;
703 phy-names = "sata-phy";
706 sata2: sata@1a400000 {
707 compatible = "apm,xgene-ahci";
708 reg = <0x0 0x1a400000 0x0 0x1000>,
709 <0x0 0x1f220000 0x0 0x1000>,
710 <0x0 0x1f22d000 0x0 0x1000>,
711 <0x0 0x1f22e000 0x0 0x1000>,
712 <0x0 0x1f227000 0x0 0x1000>;
713 interrupts = <0x0 0x87 0x4>;
716 clocks = <&sata23clk 0>;
718 phy-names = "sata-phy";
721 sata3: sata@1a800000 {
722 compatible = "apm,xgene-ahci";
723 reg = <0x0 0x1a800000 0x0 0x1000>,
724 <0x0 0x1f230000 0x0 0x1000>,
725 <0x0 0x1f23d000 0x0 0x1000>,
726 <0x0 0x1f23e000 0x0 0x1000>;
727 interrupts = <0x0 0x88 0x4>;
730 clocks = <&sata45clk 0>;
732 phy-names = "sata-phy";
735 sbgpio: sbgpio@17001000{
736 compatible = "apm,xgene-gpio-sb";
737 reg = <0x0 0x17001000 0x0 0x400>;
740 interrupts = <0x0 0x28 0x1>,
749 compatible = "apm,xgene-rtc";
750 reg = <0x0 0x10510000 0x0 0x400>;
751 interrupts = <0x0 0x46 0x4>;
753 clocks = <&rtcclk 0>;
756 menet: ethernet@17020000 {
757 compatible = "apm,xgene-enet";
759 reg = <0x0 0x17020000 0x0 0xd100>,
760 <0x0 0X17030000 0x0 0Xc300>,
761 <0x0 0X10000000 0x0 0X200>;
762 reg-names = "enet_csr", "ring_csr", "ring_cmd";
763 interrupts = <0x0 0x3c 0x4>;
765 clocks = <&menetclk 0>;
766 /* mac address will be overwritten by the bootloader */
767 local-mac-address = [00 00 00 00 00 00];
768 phy-connection-type = "rgmii";
769 phy-handle = <&menetphy>;
771 compatible = "apm,xgene-mdio";
772 #address-cells = <1>;
774 menetphy: menetphy@3 {
775 compatible = "ethernet-phy-id001c.c915";
782 sgenet0: ethernet@1f210000 {
783 compatible = "apm,xgene1-sgenet";
785 reg = <0x0 0x1f210000 0x0 0xd100>,
786 <0x0 0x1f200000 0x0 0Xc300>,
787 <0x0 0x1B000000 0x0 0X200>;
788 reg-names = "enet_csr", "ring_csr", "ring_cmd";
789 interrupts = <0x0 0xA0 0x4>,
792 clocks = <&sge0clk 0>;
793 local-mac-address = [00 00 00 00 00 00];
794 phy-connection-type = "sgmii";
797 sgenet1: ethernet@1f210030 {
798 compatible = "apm,xgene1-sgenet";
800 reg = <0x0 0x1f210030 0x0 0xd100>,
801 <0x0 0x1f200000 0x0 0Xc300>,
802 <0x0 0x1B000000 0x0 0X8000>;
803 reg-names = "enet_csr", "ring_csr", "ring_cmd";
804 interrupts = <0x0 0xAC 0x4>,
808 clocks = <&sge1clk 0>;
809 local-mac-address = [00 00 00 00 00 00];
810 phy-connection-type = "sgmii";
813 xgenet: ethernet@1f610000 {
814 compatible = "apm,xgene1-xgenet";
816 reg = <0x0 0x1f610000 0x0 0xd100>,
817 <0x0 0x1f600000 0x0 0Xc300>,
818 <0x0 0x18000000 0x0 0X200>;
819 reg-names = "enet_csr", "ring_csr", "ring_cmd";
820 interrupts = <0x0 0x60 0x4>,
823 clocks = <&xge0clk 0>;
824 /* mac address will be overwritten by the bootloader */
825 local-mac-address = [00 00 00 00 00 00];
826 phy-connection-type = "xgmii";
830 compatible = "apm,xgene-rng";
831 reg = <0x0 0x10520000 0x0 0x100>;
832 interrupts = <0x0 0x41 0x4>;
833 clocks = <&rngpkaclk 0>;
837 compatible = "apm,xgene-storm-dma";
839 reg = <0x0 0x1f270000 0x0 0x10000>,
840 <0x0 0x1f200000 0x0 0x10000>,
841 <0x0 0x1b000000 0x0 0x400000>,
842 <0x0 0x1054a000 0x0 0x100>;
843 interrupts = <0x0 0x82 0x4>,
849 clocks = <&dmaclk 0>;