arch/arm64/boot/dts/apm/apm-storm.dtsi

   1 /*
   2  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   3  *
   4  * Copyright (C) 2013, Applied Micro Circuits Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 / {
  13         compatible = "apm,xgene-storm";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu@000 {
  23                         device_type = "cpu";
  24                         compatible = "apm,potenza", "arm,armv8";
  25                         reg = <0x0 0x000>;
  26                         enable-method = "spin-table";
  27                         cpu-release-addr = <0x1 0x0000fff8>;
  28                 };
  29                 cpu@001 {
  30                         device_type = "cpu";
  31                         compatible = "apm,potenza", "arm,armv8";
  32                         reg = <0x0 0x001>;
  33                         enable-method = "spin-table";
  34                         cpu-release-addr = <0x1 0x0000fff8>;
  35                 };
  36                 cpu@100 {
  37                         device_type = "cpu";
  38                         compatible = "apm,potenza", "arm,armv8";
  39                         reg = <0x0 0x100>;
  40                         enable-method = "spin-table";
  41                         cpu-release-addr = <0x1 0x0000fff8>;
  42                 };
  43                 cpu@101 {
  44                         device_type = "cpu";
  45                         compatible = "apm,potenza", "arm,armv8";
  46                         reg = <0x0 0x101>;
  47                         enable-method = "spin-table";
  48                         cpu-release-addr = <0x1 0x0000fff8>;
  49                 };
  50                 cpu@200 {
  51                         device_type = "cpu";
  52                         compatible = "apm,potenza", "arm,armv8";
  53                         reg = <0x0 0x200>;
  54                         enable-method = "spin-table";
  55                         cpu-release-addr = <0x1 0x0000fff8>;
  56                 };
  57                 cpu@201 {
  58                         device_type = "cpu";
  59                         compatible = "apm,potenza", "arm,armv8";
  60                         reg = <0x0 0x201>;
  61                         enable-method = "spin-table";
  62                         cpu-release-addr = <0x1 0x0000fff8>;
  63                 };
  64                 cpu@300 {
  65                         device_type = "cpu";
  66                         compatible = "apm,potenza", "arm,armv8";
  67                         reg = <0x0 0x300>;
  68                         enable-method = "spin-table";
  69                         cpu-release-addr = <0x1 0x0000fff8>;
  70                 };
  71                 cpu@301 {
  72                         device_type = "cpu";
  73                         compatible = "apm,potenza", "arm,armv8";
  74                         reg = <0x0 0x301>;
  75                         enable-method = "spin-table";
  76                         cpu-release-addr = <0x1 0x0000fff8>;
  77                 };
  78         };
  79
  80         gic: interrupt-controller@78010000 {
  81                 compatible = "arm,cortex-a15-gic";
  82                 #interrupt-cells = <3>;
  83                 interrupt-controller;
  84                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
  85                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
  86                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
  87                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
  88                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
  89         };
  90
  91         timer {
  92                 compatible = "arm,armv8-timer";
  93                 interrupts = <1 0 0xff01>,      /* Secure Phys IRQ */
  94                              <1 13 0xff01>,     /* Non-secure Phys IRQ */
  95                              <1 14 0xff01>,     /* Virt IRQ */
  96                              <1 15 0xff01>;     /* Hyp IRQ */
  97                 clock-frequency = <50000000>;
  98         };
  99
 100         soc {
 101                 compatible = "simple-bus";
 102                 #address-cells = <2>;
 103                 #size-cells = <2>;
 104                 ranges;
 105                 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
 106
 107                 clocks {
 108                         #address-cells = <2>;
 109                         #size-cells = <2>;
 110                         ranges;
 111                         refclk: refclk {
 112                                 compatible = "fixed-clock";
 113                                 #clock-cells = <1>;
 114                                 clock-frequency = <100000000>;
 115                                 clock-output-names = "refclk";
 116                         };
 117
 118                         pcppll: pcppll@17000100 {
 119                                 compatible = "apm,xgene-pcppll-clock";
 120                                 #clock-cells = <1>;
 121                                 clocks = <&refclk 0>;
 122                                 clock-names = "pcppll";
 123                                 reg = <0x0 0x17000100 0x0 0x1000>;
 124                                 clock-output-names = "pcppll";
 125                                 type = <0>;
 126                         };
 127
 128                         socpll: socpll@17000120 {
 129                                 compatible = "apm,xgene-socpll-clock";
 130                                 #clock-cells = <1>;
 131                                 clocks = <&refclk 0>;
 132                                 clock-names = "socpll";
 133                                 reg = <0x0 0x17000120 0x0 0x1000>;
 134                                 clock-output-names = "socpll";
 135                                 type = <1>;
 136                         };
 137
 138                         socplldiv2: socplldiv2  {
 139                                 compatible = "fixed-factor-clock";
 140                                 #clock-cells = <1>;
 141                                 clocks = <&socpll 0>;
 142                                 clock-names = "socplldiv2";
 143                                 clock-mult = <1>;
 144                                 clock-div = <2>;
 145                                 clock-output-names = "socplldiv2";
 146                         };
 147
 148                         qmlclk: qmlclk {
 149                                 compatible = "apm,xgene-device-clock";
 150                                 #clock-cells = <1>;
 151                                 clocks = <&socplldiv2 0>;
 152                                 clock-names = "qmlclk";
 153                                 reg = <0x0 0x1703C000 0x0 0x1000>;
 154                                 reg-names = "csr-reg";
 155                                 clock-output-names = "qmlclk";
 156                         };
 157
 158                         ethclk: ethclk {
 159                                 compatible = "apm,xgene-device-clock";
 160                                 #clock-cells = <1>;
 161                                 clocks = <&socplldiv2 0>;
 162                                 clock-names = "ethclk";
 163                                 reg = <0x0 0x17000000 0x0 0x1000>;
 164                                 reg-names = "div-reg";
 165                                 divider-offset = <0x238>;
 166                                 divider-width = <0x9>;
 167                                 divider-shift = <0x0>;
 168                                 clock-output-names = "ethclk";
 169                         };
 170
 171                         menetclk: menetclk {
 172                                 compatible = "apm,xgene-device-clock";
 173                                 #clock-cells = <1>;
 174                                 clocks = <&ethclk 0>;
 175                                 reg = <0x0 0x1702C000 0x0 0x1000>;
 176                                 reg-names = "csr-reg";
 177                                 clock-output-names = "menetclk";
 178                         };
 179
 180                         sge0clk: sge0clk@1f21c000 {
 181                                 compatible = "apm,xgene-device-clock";
 182                                 #clock-cells = <1>;
 183                                 clocks = <&socplldiv2 0>;
 184                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 185                                 reg-names = "csr-reg";
 186                                 csr-mask = <0x3>;
 187                                 clock-output-names = "sge0clk";
 188                         };
 189
 190                         sge1clk: sge1clk@1f21c000 {
 191                                 compatible = "apm,xgene-device-clock";
 192                                 #clock-cells = <1>;
 193                                 clocks = <&socplldiv2 0>;
 194                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 195                                 reg-names = "csr-reg";
 196                                 csr-mask = <0xc>;
 197                                 clock-output-names = "sge1clk";
 198                         };
 199
 200                         xge0clk: xge0clk@1f61c000 {
 201                                 compatible = "apm,xgene-device-clock";
 202                                 #clock-cells = <1>;
 203                                 clocks = <&socplldiv2 0>;
 204                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 205                                 reg-names = "csr-reg";
 206                                 csr-mask = <0x3>;
 207                                 clock-output-names = "xge0clk";
 208                         };
 209
 210                         xge1clk: xge1clk@1f62c000 {
 211                                 compatible = "apm,xgene-device-clock";
 212                                 status = "disabled";
 213                                 #clock-cells = <1>;
 214                                 clocks = <&socplldiv2 0>;
 215                                 reg = <0x0 0x1f62c000 0x0 0x1000>;
 216                                 reg-names = "csr-reg";
 217                                 csr-mask = <0x3>;
 218                                 clock-output-names = "xge1clk";
 219                         };
 220
 221                         sataphy1clk: sataphy1clk@1f21c000 {
 222                                 compatible = "apm,xgene-device-clock";
 223                                 #clock-cells = <1>;
 224                                 clocks = <&socplldiv2 0>;
 225                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 226                                 reg-names = "csr-reg";
 227                                 clock-output-names = "sataphy1clk";
 228                                 status = "disabled";
 229                                 csr-offset = <0x4>;
 230                                 csr-mask = <0x00>;
 231                                 enable-offset = <0x0>;
 232                                 enable-mask = <0x06>;
 233                         };
 234
 235                         sataphy2clk: sataphy1clk@1f22c000 {
 236                                 compatible = "apm,xgene-device-clock";
 237                                 #clock-cells = <1>;
 238                                 clocks = <&socplldiv2 0>;
 239                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 240                                 reg-names = "csr-reg";
 241                                 clock-output-names = "sataphy2clk";
 242                                 status = "ok";
 243                                 csr-offset = <0x4>;
 244                                 csr-mask = <0x3a>;
 245                                 enable-offset = <0x0>;
 246                                 enable-mask = <0x06>;
 247                         };
 248
 249                         sataphy3clk: sataphy1clk@1f23c000 {
 250                                 compatible = "apm,xgene-device-clock";
 251                                 #clock-cells = <1>;
 252                                 clocks = <&socplldiv2 0>;
 253                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 254                                 reg-names = "csr-reg";
 255                                 clock-output-names = "sataphy3clk";
 256                                 status = "ok";
 257                                 csr-offset = <0x4>;
 258                                 csr-mask = <0x3a>;
 259                                 enable-offset = <0x0>;
 260                                 enable-mask = <0x06>;
 261                         };
 262
 263                         sata01clk: sata01clk@1f21c000 {
 264                                 compatible = "apm,xgene-device-clock";
 265                                 #clock-cells = <1>;
 266                                 clocks = <&socplldiv2 0>;
 267                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 268                                 reg-names = "csr-reg";
 269                                 clock-output-names = "sata01clk";
 270                                 csr-offset = <0x4>;
 271                                 csr-mask = <0x05>;
 272                                 enable-offset = <0x0>;
 273                                 enable-mask = <0x39>;
 274                         };
 275
 276                         sata23clk: sata23clk@1f22c000 {
 277                                 compatible = "apm,xgene-device-clock";
 278                                 #clock-cells = <1>;
 279                                 clocks = <&socplldiv2 0>;
 280                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 281                                 reg-names = "csr-reg";
 282                                 clock-output-names = "sata23clk";
 283                                 csr-offset = <0x4>;
 284                                 csr-mask = <0x05>;
 285                                 enable-offset = <0x0>;
 286                                 enable-mask = <0x39>;
 287                         };
 288
 289                         sata45clk: sata45clk@1f23c000 {
 290                                 compatible = "apm,xgene-device-clock";
 291                                 #clock-cells = <1>;
 292                                 clocks = <&socplldiv2 0>;
 293                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 294                                 reg-names = "csr-reg";
 295                                 clock-output-names = "sata45clk";
 296                                 csr-offset = <0x4>;
 297                                 csr-mask = <0x05>;
 298                                 enable-offset = <0x0>;
 299                                 enable-mask = <0x39>;
 300                         };
 301
 302                         rtcclk: rtcclk@17000000 {
 303                                 compatible = "apm,xgene-device-clock";
 304                                 #clock-cells = <1>;
 305                                 clocks = <&socplldiv2 0>;
 306                                 reg = <0x0 0x17000000 0x0 0x2000>;
 307                                 reg-names = "csr-reg";
 308                                 csr-offset = <0xc>;
 309                                 csr-mask = <0x2>;
 310                                 enable-offset = <0x10>;
 311                                 enable-mask = <0x2>;
 312                                 clock-output-names = "rtcclk";
 313                         };
 314
 315                         rngpkaclk: rngpkaclk@17000000 {
 316                                 compatible = "apm,xgene-device-clock";
 317                                 #clock-cells = <1>;
 318                                 clocks = <&socplldiv2 0>;
 319                                 reg = <0x0 0x17000000 0x0 0x2000>;
 320                                 reg-names = "csr-reg";
 321                                 csr-offset = <0xc>;
 322                                 csr-mask = <0x10>;
 323                                 enable-offset = <0x10>;
 324                                 enable-mask = <0x10>;
 325                                 clock-output-names = "rngpkaclk";
 326                         };
 327
 328                         pcie0clk: pcie0clk@1f2bc000 {
 329                                 status = "disabled";
 330                                 compatible = "apm,xgene-device-clock";
 331                                 #clock-cells = <1>;
 332                                 clocks = <&socplldiv2 0>;
 333                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 334                                 reg-names = "csr-reg";
 335                                 clock-output-names = "pcie0clk";
 336                         };
 337
 338                         pcie1clk: pcie1clk@1f2cc000 {
 339                                 status = "disabled";
 340                                 compatible = "apm,xgene-device-clock";
 341                                 #clock-cells = <1>;
 342                                 clocks = <&socplldiv2 0>;
 343                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 344                                 reg-names = "csr-reg";
 345                                 clock-output-names = "pcie1clk";
 346                         };
 347
 348                         pcie2clk: pcie2clk@1f2dc000 {
 349                                 status = "disabled";
 350                                 compatible = "apm,xgene-device-clock";
 351                                 #clock-cells = <1>;
 352                                 clocks = <&socplldiv2 0>;
 353                                 reg = <0x0 0x1f2dc000 0x0 0x1000>;
 354                                 reg-names = "csr-reg";
 355                                 clock-output-names = "pcie2clk";
 356                         };
 357
 358                         pcie3clk: pcie3clk@1f50c000 {
 359                                 status = "disabled";
 360                                 compatible = "apm,xgene-device-clock";
 361                                 #clock-cells = <1>;
 362                                 clocks = <&socplldiv2 0>;
 363                                 reg = <0x0 0x1f50c000 0x0 0x1000>;
 364                                 reg-names = "csr-reg";
 365                                 clock-output-names = "pcie3clk";
 366                         };
 367
 368                         pcie4clk: pcie4clk@1f51c000 {
 369                                 status = "disabled";
 370                                 compatible = "apm,xgene-device-clock";
 371                                 #clock-cells = <1>;
 372                                 clocks = <&socplldiv2 0>;
 373                                 reg = <0x0 0x1f51c000 0x0 0x1000>;
 374                                 reg-names = "csr-reg";
 375                                 clock-output-names = "pcie4clk";
 376                         };
 377
 378                         dmaclk: dmaclk@1f27c000 {
 379                                 compatible = "apm,xgene-device-clock";
 380                                 #clock-cells = <1>;
 381                                 clocks = <&socplldiv2 0>;
 382                                 reg = <0x0 0x1f27c000 0x0 0x1000>;
 383                                 reg-names = "csr-reg";
 384                                 clock-output-names = "dmaclk";
 385                         };
 386                 };
 387
 388                 msi: msi@79000000 {
 389                         compatible = "apm,xgene1-msi";
 390                         msi-controller;
 391                         reg = <0x00 0x79000000 0x0 0x900000>;
 392                         interrupts = <  0x0 0x10 0x4
 393                                         0x0 0x11 0x4
 394                                         0x0 0x12 0x4
 395                                         0x0 0x13 0x4
 396                                         0x0 0x14 0x4
 397                                         0x0 0x15 0x4
 398                                         0x0 0x16 0x4
 399                                         0x0 0x17 0x4
 400                                         0x0 0x18 0x4
 401                                         0x0 0x19 0x4
 402                                         0x0 0x1a 0x4
 403                                         0x0 0x1b 0x4
 404                                         0x0 0x1c 0x4
 405                                         0x0 0x1d 0x4
 406                                         0x0 0x1e 0x4
 407                                         0x0 0x1f 0x4>;
 408                 };
 409
 410                 csw: csw@7e200000 {
 411                         compatible = "apm,xgene-csw", "syscon";
 412                         reg = <0x0 0x7e200000 0x0 0x1000>;
 413                 };
 414
 415                 mcba: mcba@7e700000 {
 416                         compatible = "apm,xgene-mcb", "syscon";
 417                         reg = <0x0 0x7e700000 0x0 0x1000>;
 418                 };
 419
 420                 mcbb: mcbb@7e720000 {
 421                         compatible = "apm,xgene-mcb", "syscon";
 422                         reg = <0x0 0x7e720000 0x0 0x1000>;
 423                 };
 424
 425                 efuse: efuse@1054a000 {
 426                         compatible = "apm,xgene-efuse", "syscon";
 427                         reg = <0x0 0x1054a000 0x0 0x20>;
 428                 };
 429
 430                 edac@78800000 {
 431                         compatible = "apm,xgene-edac";
 432                         #address-cells = <2>;
 433                         #size-cells = <2>;
 434                         ranges;
 435                         regmap-csw = <&csw>;
 436                         regmap-mcba = <&mcba>;
 437                         regmap-mcbb = <&mcbb>;
 438                         regmap-efuse = <&efuse>;
 439                         reg = <0x0 0x78800000 0x0 0x100>;
 440                         interrupts = <0x0 0x20 0x4>,
 441                                      <0x0 0x21 0x4>,
 442                                      <0x0 0x27 0x4>;
 443
 444                         edacmc@7e800000 {
 445                                 compatible = "apm,xgene-edac-mc";
 446                                 reg = <0x0 0x7e800000 0x0 0x1000>;
 447                                 memory-controller = <0>;
 448                         };
 449
 450                         edacmc@7e840000 {
 451                                 compatible = "apm,xgene-edac-mc";
 452                                 reg = <0x0 0x7e840000 0x0 0x1000>;
 453                                 memory-controller = <1>;
 454                         };
 455
 456                         edacmc@7e880000 {
 457                                 compatible = "apm,xgene-edac-mc";
 458                                 reg = <0x0 0x7e880000 0x0 0x1000>;
 459                                 memory-controller = <2>;
 460                         };
 461
 462                         edacmc@7e8c0000 {
 463                                 compatible = "apm,xgene-edac-mc";
 464                                 reg = <0x0 0x7e8c0000 0x0 0x1000>;
 465                                 memory-controller = <3>;
 466                         };
 467
 468                         edacpmd@7c000000 {
 469                                 compatible = "apm,xgene-edac-pmd";
 470                                 reg = <0x0 0x7c000000 0x0 0x200000>;
 471                                 pmd-controller = <0>;
 472                         };
 473
 474                         edacpmd@7c200000 {
 475                                 compatible = "apm,xgene-edac-pmd";
 476                                 reg = <0x0 0x7c200000 0x0 0x200000>;
 477                                 pmd-controller = <1>;
 478                         };
 479
 480                         edacpmd@7c400000 {
 481                                 compatible = "apm,xgene-edac-pmd";
 482                                 reg = <0x0 0x7c400000 0x0 0x200000>;
 483                                 pmd-controller = <2>;
 484                         };
 485
 486                         edacpmd@7c600000 {
 487                                 compatible = "apm,xgene-edac-pmd";
 488                                 reg = <0x0 0x7c600000 0x0 0x200000>;
 489                                 pmd-controller = <3>;
 490                         };
 491                 };
 492
 493                 pcie0: pcie@1f2b0000 {
 494                         status = "disabled";
 495                         device_type = "pci";
 496                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 497                         #interrupt-cells = <1>;
 498                         #size-cells = <2>;
 499                         #address-cells = <3>;
 500                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 501                                 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 502                         reg-names = "csr", "cfg";
 503                         ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 504                                   0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
 505                                   0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
 506                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 507                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 508                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 509                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
 510                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
 511                                          0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
 512                                          0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
 513                         dma-coherent;
 514                         clocks = <&pcie0clk 0>;
 515                         msi-parent = <&msi>;
 516                 };
 517
 518                 pcie1: pcie@1f2c0000 {
 519                         status = "disabled";
 520                         device_type = "pci";
 521                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 522                         #interrupt-cells = <1>;
 523                         #size-cells = <2>;
 524                         #address-cells = <3>;
 525                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 526                                 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 527                         reg-names = "csr", "cfg";
 528                         ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 529                                   0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
 530                                   0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
 531                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 532                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 533                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 534                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
 535                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
 536                                          0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
 537                                          0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
 538                         dma-coherent;
 539                         clocks = <&pcie1clk 0>;
 540                         msi-parent = <&msi>;
 541                 };
 542
 543                 pcie2: pcie@1f2d0000 {
 544                         status = "disabled";
 545                         device_type = "pci";
 546                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 547                         #interrupt-cells = <1>;
 548                         #size-cells = <2>;
 549                         #address-cells = <3>;
 550                         reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
 551                                  0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
 552                         reg-names = "csr", "cfg";
 553                         ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
 554                                   0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
 555                                   0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
 556                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 557                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 558                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 559                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
 560                                          0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
 561                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
 562                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
 563                         dma-coherent;
 564                         clocks = <&pcie2clk 0>;
 565                         msi-parent = <&msi>;
 566                 };
 567
 568                 pcie3: pcie@1f500000 {
 569                         status = "disabled";
 570                         device_type = "pci";
 571                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 572                         #interrupt-cells = <1>;
 573                         #size-cells = <2>;
 574                         #address-cells = <3>;
 575                         reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
 576                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 577                         reg-names = "csr", "cfg";
 578                         ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
 579                                   0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
 580                                   0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
 581                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 582                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 583                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 584                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
 585                                          0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
 586                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
 587                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
 588                         dma-coherent;
 589                         clocks = <&pcie3clk 0>;
 590                         msi-parent = <&msi>;
 591                 };
 592
 593                 pcie4: pcie@1f510000 {
 594                         status = "disabled";
 595                         device_type = "pci";
 596                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 597                         #interrupt-cells = <1>;
 598                         #size-cells = <2>;
 599                         #address-cells = <3>;
 600                         reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
 601                                 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
 602                         reg-names = "csr", "cfg";
 603                         ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
 604                                   0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
 605                                   0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
 606                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 607                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 608                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 609                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
 610                                          0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
 611                                          0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
 612                                          0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
 613                         dma-coherent;
 614                         clocks = <&pcie4clk 0>;
 615                         msi-parent = <&msi>;
 616                 };
 617
 618                 serial0: serial@1c020000 {
 619                         status = "disabled";
 620                         device_type = "serial";
 621                         compatible = "ns16550a";
 622                         reg = <0 0x1c020000 0x0 0x1000>;
 623                         reg-shift = <2>;
 624                         clock-frequency = <10000000>; /* Updated by bootloader */
 625                         interrupt-parent = <&gic>;
 626                         interrupts = <0x0 0x4c 0x4>;
 627                 };
 628
 629                 serial1: serial@1c021000 {
 630                         status = "disabled";
 631                         device_type = "serial";
 632                         compatible = "ns16550a";
 633                         reg = <0 0x1c021000 0x0 0x1000>;
 634                         reg-shift = <2>;
 635                         clock-frequency = <10000000>; /* Updated by bootloader */
 636                         interrupt-parent = <&gic>;
 637                         interrupts = <0x0 0x4d 0x4>;
 638                 };
 639
 640                 serial2: serial@1c022000 {
 641                         status = "disabled";
 642                         device_type = "serial";
 643                         compatible = "ns16550a";
 644                         reg = <0 0x1c022000 0x0 0x1000>;
 645                         reg-shift = <2>;
 646                         clock-frequency = <10000000>; /* Updated by bootloader */
 647                         interrupt-parent = <&gic>;
 648                         interrupts = <0x0 0x4e 0x4>;
 649                 };
 650
 651                 serial3: serial@1c023000 {
 652                         status = "disabled";
 653                         device_type = "serial";
 654                         compatible = "ns16550a";
 655                         reg = <0 0x1c023000 0x0 0x1000>;
 656                         reg-shift = <2>;
 657                         clock-frequency = <10000000>; /* Updated by bootloader */
 658                         interrupt-parent = <&gic>;
 659                         interrupts = <0x0 0x4f 0x4>;
 660                 };
 661
 662                 phy1: phy@1f21a000 {
 663                         compatible = "apm,xgene-phy";
 664                         reg = <0x0 0x1f21a000 0x0 0x100>;
 665                         #phy-cells = <1>;
 666                         clocks = <&sataphy1clk 0>;
 667                         status = "disabled";
 668                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 669                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 670                 };
 671
 672                 phy2: phy@1f22a000 {
 673                         compatible = "apm,xgene-phy";
 674                         reg = <0x0 0x1f22a000 0x0 0x100>;
 675                         #phy-cells = <1>;
 676                         clocks = <&sataphy2clk 0>;
 677                         status = "ok";
 678                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 679                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 680                 };
 681
 682                 phy3: phy@1f23a000 {
 683                         compatible = "apm,xgene-phy";
 684                         reg = <0x0 0x1f23a000 0x0 0x100>;
 685                         #phy-cells = <1>;
 686                         clocks = <&sataphy3clk 0>;
 687                         status = "ok";
 688                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 689                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 690                 };
 691
 692                 sata1: sata@1a000000 {
 693                         compatible = "apm,xgene-ahci";
 694                         reg = <0x0 0x1a000000 0x0 0x1000>,
 695                               <0x0 0x1f210000 0x0 0x1000>,
 696                               <0x0 0x1f21d000 0x0 0x1000>,
 697                               <0x0 0x1f21e000 0x0 0x1000>,
 698                               <0x0 0x1f217000 0x0 0x1000>;
 699                         interrupts = <0x0 0x86 0x4>;
 700                         dma-coherent;
 701                         status = "disabled";
 702                         clocks = <&sata01clk 0>;
 703                         phys = <&phy1 0>;
 704                         phy-names = "sata-phy";
 705                 };
 706
 707                 sata2: sata@1a400000 {
 708                         compatible = "apm,xgene-ahci";
 709                         reg = <0x0 0x1a400000 0x0 0x1000>,
 710                               <0x0 0x1f220000 0x0 0x1000>,
 711                               <0x0 0x1f22d000 0x0 0x1000>,
 712                               <0x0 0x1f22e000 0x0 0x1000>,
 713                               <0x0 0x1f227000 0x0 0x1000>;
 714                         interrupts = <0x0 0x87 0x4>;
 715                         dma-coherent;
 716                         status = "ok";
 717                         clocks = <&sata23clk 0>;
 718                         phys = <&phy2 0>;
 719                         phy-names = "sata-phy";
 720                 };
 721
 722                 sata3: sata@1a800000 {
 723                         compatible = "apm,xgene-ahci";
 724                         reg = <0x0 0x1a800000 0x0 0x1000>,
 725                               <0x0 0x1f230000 0x0 0x1000>,
 726                               <0x0 0x1f23d000 0x0 0x1000>,
 727                               <0x0 0x1f23e000 0x0 0x1000>;
 728                         interrupts = <0x0 0x88 0x4>;
 729                         dma-coherent;
 730                         status = "ok";
 731                         clocks = <&sata45clk 0>;
 732                         phys = <&phy3 0>;
 733                         phy-names = "sata-phy";
 734                 };
 735
 736                 sbgpio: sbgpio@17001000{
 737                         compatible = "apm,xgene-gpio-sb";
 738                         reg = <0x0 0x17001000 0x0 0x400>;
 739                         #gpio-cells = <2>;
 740                         gpio-controller;
 741                         interrupts =    <0x0 0x28 0x1>,
 742                                         <0x0 0x29 0x1>,
 743                                         <0x0 0x2a 0x1>,
 744                                         <0x0 0x2b 0x1>,
 745                                         <0x0 0x2c 0x1>,
 746                                         <0x0 0x2d 0x1>;
 747                 };
 748
 749                 rtc: rtc@10510000 {
 750                         compatible = "apm,xgene-rtc";
 751                         reg = <0x0 0x10510000 0x0 0x400>;
 752                         interrupts = <0x0 0x46 0x4>;
 753                         #clock-cells = <1>;
 754                         clocks = <&rtcclk 0>;
 755                 };
 756
 757                 menet: ethernet@17020000 {
 758                         compatible = "apm,xgene-enet";
 759                         status = "disabled";
 760                         reg = <0x0 0x17020000 0x0 0xd100>,
 761                               <0x0 0X17030000 0x0 0Xc300>,
 762                               <0x0 0X10000000 0x0 0X200>;
 763                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 764                         interrupts = <0x0 0x3c 0x4>;
 765                         dma-coherent;
 766                         clocks = <&menetclk 0>;
 767                         /* mac address will be overwritten by the bootloader */
 768                         local-mac-address = [00 00 00 00 00 00];
 769                         phy-connection-type = "rgmii";
 770                         phy-handle = <&menetphy>;
 771                         mdio {
 772                                 compatible = "apm,xgene-mdio";
 773                                 #address-cells = <1>;
 774                                 #size-cells = <0>;
 775                                 menetphy: menetphy@3 {
 776                                         compatible = "ethernet-phy-id001c.c915";
 777                                         reg = <0x3>;
 778                                 };
 779
 780                         };
 781                 };
 782
 783                 sgenet0: ethernet@1f210000 {
 784                         compatible = "apm,xgene1-sgenet";
 785                         status = "disabled";
 786                         reg = <0x0 0x1f210000 0x0 0xd100>,
 787                               <0x0 0x1f200000 0x0 0Xc300>,
 788                               <0x0 0x1B000000 0x0 0X200>;
 789                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 790                         interrupts = <0x0 0xA0 0x4>,
 791                                      <0x0 0xA1 0x4>;
 792                         dma-coherent;
 793                         clocks = <&sge0clk 0>;
 794                         local-mac-address = [00 00 00 00 00 00];
 795                         phy-connection-type = "sgmii";
 796                 };
 797
 798                 sgenet1: ethernet@1f210030 {
 799                         compatible = "apm,xgene1-sgenet";
 800                         status = "disabled";
 801                         reg = <0x0 0x1f210030 0x0 0xd100>,
 802                               <0x0 0x1f200000 0x0 0Xc300>,
 803                               <0x0 0x1B000000 0x0 0X8000>;
 804                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 805                         interrupts = <0x0 0xAC 0x4>,
 806                                      <0x0 0xAD 0x4>;
 807                         port-id = <1>;
 808                         dma-coherent;
 809                         clocks = <&sge1clk 0>;
 810                         local-mac-address = [00 00 00 00 00 00];
 811                         phy-connection-type = "sgmii";
 812                 };
 813
 814                 xgenet: ethernet@1f610000 {
 815                         compatible = "apm,xgene1-xgenet";
 816                         status = "disabled";
 817                         reg = <0x0 0x1f610000 0x0 0xd100>,
 818                               <0x0 0x1f600000 0x0 0Xc300>,
 819                               <0x0 0x18000000 0x0 0X200>;
 820                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 821                         interrupts = <0x0 0x60 0x4>,
 822                                      <0x0 0x61 0x4>;
 823                         dma-coherent;
 824                         clocks = <&xge0clk 0>;
 825                         /* mac address will be overwritten by the bootloader */
 826                         local-mac-address = [00 00 00 00 00 00];
 827                         phy-connection-type = "xgmii";
 828                 };
 829
 830                 xgenet1: ethernet@1f620000 {
 831                         compatible = "apm,xgene1-xgenet";
 832                         status = "disabled";
 833                         reg = <0x0 0x1f620000 0x0 0xd100>,
 834                               <0x0 0x1f600000 0x0 0Xc300>,
 835                               <0x0 0x18000000 0x0 0X8000>;
 836                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 837                         interrupts = <0x0 0x6C 0x4>,
 838                                      <0x0 0x6D 0x4>;
 839                         port-id = <1>;
 840                         dma-coherent;
 841                         clocks = <&xge1clk 0>;
 842                         /* mac address will be overwritten by the bootloader */
 843                         local-mac-address = [00 00 00 00 00 00];
 844                         phy-connection-type = "xgmii";
 845                 };
 846
 847                 rng: rng@10520000 {
 848                         compatible = "apm,xgene-rng";
 849                         reg = <0x0 0x10520000 0x0 0x100>;
 850                         interrupts = <0x0 0x41 0x4>;
 851                         clocks = <&rngpkaclk 0>;
 852                 };
 853
 854                 dma: dma@1f270000 {
 855                         compatible = "apm,xgene-storm-dma";
 856                         device_type = "dma";
 857                         reg = <0x0 0x1f270000 0x0 0x10000>,
 858                               <0x0 0x1f200000 0x0 0x10000>,
 859                               <0x0 0x1b000000 0x0 0x400000>,
 860                               <0x0 0x1054a000 0x0 0x100>;
 861                         interrupts = <0x0 0x82 0x4>,
 862                                      <0x0 0xb8 0x4>,
 863                                      <0x0 0xb9 0x4>,
 864                                      <0x0 0xba 0x4>,
 865                                      <0x0 0xbb 0x4>;
 866                         dma-coherent;
 867                         clocks = <&dmaclk 0>;
 868                 };
 869         };
 870 };